16-Bit Tft/D-Tfd Panel Timing - Epson S1D13505F00A Technical Manual

16-Bit TFT/D-TFD Panel Timing

FPFRAME
FPLINE
LINE480
R [5:1], G [5:0], B [5:1]
DRDY
FPLINE
FPSHIFT
DRDY
R [5:1]
G [5:0]
B [5:1]
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
VDP = Vertical Display Period
VNDP = Vertical Non-Display Period
HDP = Horizontal Display Period
HNDP = Horizontal Non-Display Period = HNDP
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
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VNDP VDP
LINE1
HDP
HNDP
1
1-1 1-2
1-1 1-2
1-1 1-2
Figure 7-42 16-Bit TFT/D-TFD Panel Timing
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
+ HNDP = ((REG[05h] bits [4:0]) + 1)*8Ts
1 2
EPSON
7: A.C. CHARACTERISTICS
LINE480
HNDP
2
1-640
1-640
1-640
1-75