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Description of Pins
Pin
Pin
I/O
No.
Name
1
DEFI
I
2
TAI
I
3
PDO
O
4
VV
P
SS
5
ISET
AI
6
VV
P
DD
7
FR
AI
8
V
P
SS
9
TESCLK
I
10
TESA
I
11
TESB
I
12
TESC
I
13
TESGB
I
14
TEST5
I
15
CS
I
16
TEST1
I
17
EFMO
O
18
EFMI
I
19
TEST2
I
+
20
CLV
O
–
21
CLV
O
22
V/P
O
23
HFL
I
24
TES
I
25
TOFF
O
26
TGL
O
+
27
JP
O
–
28
JP
O
29
PCK
O
30
FSEQ
O
31
V
P
DD
32
ASRES
I(I/O)
33
CONT2
I/O
Defect detection signal (DEF) input. When not used, must be connected to 0 V.
Test input. Equipped with internal pull-down resistor. Must be connected to 0V.
Internal VCO control phase comparator output
Internal VCO ground. Must be connected to 0 V.
For the PLL
PDO output current adjustment resistor connection
Internal VCO power supply
VCO frequency range adjustment
Digital system ground. Must be connected to 0 V.
Test clock input. Must be connected to V
Test operation mode control input. Must be connected to V
Test operation mode control input. Must be connected to V
Test operation mode control input. Must be connected to V
Test operation mode control input. Must be connected to V
Test input. Equipped with internal pull-down resistor. Must be connected to 0 V.
Chip select input. Equipped with internal pull-down resistor. When not controlled, must be connected to 0 V.
Test input. Must be connected to 0 V.
For slice
EFM signal output
level control
EFM signal input
Test input. Equipped with internal pull-down resistor. Must be connected to 0 V.
Disk motor control output. Can have a 3-state output depending on the command.
Rough servo/phase control automatic switching monitor output. If a high level then rough servo mode.
If a low level then phase control mode.
Track detect signal input. Schmidt input.
Tracking error signal input. Schmidt input.
Tracking off output
Tracking gain switch output. Gain is increased with low level.
Track jump control output. Can be 3-state output depending on the command.
EFM data playback clock monitor. 4.3218 MHz during phase lock.
Sync signal detect output. A high level when the sync signal detected from the EFM signal matches the
internally generated sync signal.
Digital system power supply
Reset signal input for initializing only the anti-shock control part (i.e. excluding the DSP part). Resets when
this pin is low level, and release the reset when this pin is high level. Tie this pin to the low level (i.e.,
connected to 0 V) if when using software control on the anti-shock part alone through the anti-shock part
only reset disable/release command ($F4) or the anti-shock only reset enable/inrush command ($F5).
Note: This pin is assigned as the least significant bit of the general I/O port however, use as a general I/O
pin is disabled. When the port I/O set command ($DB) is executed, the least significant bit is always "0," and
the output driver is not turned ON.
General I/O pin 2. This controls the commands from the microcontroller. When not used, either set this as
an input port and connect to 0 V, or set this as an output port and leave it open.
LC78626KE
Function
.
DD
.
DD
.
DD
.
DD
.
DD
Output pin states
during reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Undefined
—
—
Low-level output
Low-level output
—
—
High-level output
Undefined
Low-level output
Low-level output
Undefined
—
Input mode
Input mode
Continued on next page.
No. 5995-8/34
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