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Continued from preceding page.
Pin
Pin
I/O
No.
Name
70
MMC0
O
71
MMC1
O
72
MMC2
O
73
MMC3
O
74
OVF
O
75
CNTOK
O
76
WOK
I
77
PAUSE IN
I
78
AD10/CAS2
O
79
EMPN
O
80
SHOCK
I
81
DRAM3
I/O
82
DRAM2
I/O
83
DRAM1
I/O
84
DRAM0
I/O
85
OE
O
86
WE
O
87
CAS
O
88
RAS
O
89
AD9
O
90
AD8
O
91
AD7
O
92
AD6
O
93
AD5
O
94
V
P
SS
95
AD4
O
96
AD3
O
97
AD2
O
98
AD1
O
99
AD0
O
100
V
P
DD
Remaining DRAM output
Remaining DRAM output
Remaining DRAM output
Remaining DRAM output
DRAM write terminated. (An RZP pulse is output when there is an overflow or a shock.)
Data contact point detection complete signal: low→ high: detection complete. (DRAM write start).
DRAM write enable signal input: high: write enable.
Pause signal input: high: pause.
Shared function pin that functions either as a 16M DRAM address output (AD10) or as a DRAM control
signal (CAS2) used when 8M of DRAM (two 4M DRAM chips) is used. The function is switched by the
DRAM selection pins MR1 and MR2.
Remaining DRAM alarm output: low: memory low.
C2F shock detect pause signal input: low: pause shock detection.
DRAM data bus
DRAM data bus
DRAM data bus
DRAM data bus
DRAM control signal
DRAM control signal
DRAM control signal
DRAM control signal
DRAM address bus
DRAM address bus
DRAM address bus
DRAM address bus
DRAM address bus
Digital system ground. Must be connected to 0 V.
DRAM address bus
DRAM address bus
DRAM address bus
DRAM address bus
DRAM address bus
Digital system power supply
LC78626KE
Description
Output pin states
during reset
Low-level output
Low-level output
Low-level output
Low-level output
Low-level output
High-level output
—
—
Undefined
Low-level output
—
Input mode
Input mode
Input mode
Input mode
Low-level output
High-level output
Undefined
Undefined
Low-level output
Low-level output
Low-level output
Low-level output
Low-level output
—
Low-level output
Low-level output
Low-level output
Undefined
Undefined
—
No. 5995-10/34
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