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Pin Applications
The HF Signal Input Circuit
HF Signal
The PLL Clock Playback Circuit
The VCO Monitor
This is the monitor pin with an average frequency of 4.3218 MHz, which is a 1/2 frequency division from VCO.
The Sync Detect Monitor
The EFM signal goes high when the frame sync signal (the true sync signal) from the PCK matches the timing (the
interpolated sync signal) generated by the counter. This serves as the sync detect monitor (holding the high level over a
single frame).
Pin 18: EFMI, Pin 17: EFMO, Pin 1: DEFI, and Pin 20: CLV
Pin 3: PDO, Pin 5: ISET and Pin 7: FR
Frequency
and phase
comparator
Charge pump
Pin 29: PCK
Pin 30: FSEQ
LC78626KE
When an HF signal is input to the EFMI, an EFM signal (NRZ),
sliced at the optimal levels, is obtained.
As a countermeasure against defects, when the DEFI pin (Pin 1)
is high, the slice level control output EFMO pin (Pin 17) goes to
a high impedance state, and the slice level is held. However, this
is only enabled when the CLV is in phase-control mode, or in
other words, when the V/P pin (Pin 22) is low. This can be
structured from a combination with the DEF pin of LA9230/
40/50 series ICs.
* When the EFMI and CLV
then the error rate due to unnecessary radiation may increase.
It is recommended that these two lines be separated by a
ground line or by a V
The VCO circuit is equipped internally, and the PLL circuit is
structured using external resistors and external capacitors. The
ISET is the reference current for the charge pump. The PDO is
the loop filter for the VCO circuit, and the FR is the resistor that
determines the frequency range of the VCO.
Reference Values
R1 = 68 kΩ
R2 = 680 Ω
R3 = 1.2 kΩ
* It is recommended that a carbon coated resistor with a
tolerance of ±5.0% be used for R3.
+
+
signal lines are close to each other
line as a shield line.
DD
C1 = 0.1 µF (standard speed)
C1 = 0.047 µF (2× speed)
C2 = 0.1 µF
No. 5995-11/34
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