HP Visualize J200 Reference Manual page 33

Supports coherent I/O, with special transactions for DMA in either 16–byte blocks or
cacheline–sized blocks.
No aborts or retries
No dead cycles for master turn–around
Single cycle transaction issue; no separate SADD/MADD/VADD cycles
40–bit physical address support.
Peak bandwidth depends on frequency and linesize. Each memory transaction, either read or write, is
made up of a single address cycle, plus 2, 4, or 8 data cycles, for 16, 32, or 64 byte lines respectively. Thus,
as the linesize increases, more of the signal bandwidth is used for data transfer, so larger linesizes deliver a
greater effective bandwidth.
To achieve maximum frequency, the protocol is designed so that no logic needs to be done in the same
cycle as a chip crossing, and there are no OR–tied signals.
The bus is a 64–bit wide time–multiplexed address/data bus. On each data cycle, a full doubleword of data
is transmitted. On each address cycle, all information needed to issue the transaction is transmitted,
including transaction type, address, and cache index.
All split transactions are tagged with the issuing module's MASTER_ID and a transaction ID, such that
the combination of MASTER_ID, transaction ID, and return–type are unique for the duration of the
transaction. The data response is identified by the same MASTER_ID and transaction ID, so that an extra
address cycle is not needed for the data return.
Each module can report cache coherency (CCC) status on coherent transactions at its own rate, rather than
at a fixed time. Each module has a dedicated bus to report CCC status, in FIFO order, to the central host.
As long as each coherent module has reported CCC status by the time the data is ready to be returned,
there is no extra delay for CCC.
The bus does not have any "retry" or "abort" signals or transactions. Instead, it uses predictive flow
control, so that a transaction can only be issued if it can be handled. Previous busses have used a reactive
flow control that aborted transactions after they were issued when some module signaled that it couldn't
handle the transaction.
Other Features
Here are the other high points of the bus protocol:
Single cycle address transfers
No dead cycles between master changes
40–bit physical addressing
10–bit virtual index
Maximum of 8 clients per bus, with clients being a mix of processors and other devices