1. Manuals
  2. Brands
  3. HP Manuals
  4. Desktop
  5. Visualize J200
  6. Reference manual

HP Visualize J200 Reference Manual

Hp visualize j200: reference manual
Hide thumbs Also See for Visualize J200:
Table of Contents

Advertisement

Quick Links

Download this manual See also: Troubleshooting Manual, Administration Manual
For:root
Printed on:Wed, Sep 4, 1996 12:44:27
From book:skyhawk_tech_ref
Document:ch_1
Last saved on:Wed, Mar 13, 1996 11:48:41

Advertisement

Table of Contents
loading

Related Manuals for HP Visualize J200

Summary of Contents for HP Visualize J200

  • Page 1 For:root Printed on:Wed, Sep 4, 1996 12:44:27 From book:skyhawk_tech_ref Document:ch_1 Last saved on:Wed, Mar 13, 1996 11:48:41...

  • Page 2: General Information

    960MB/sec load (8 byte), 960 MB/sec single store (8 byte) Battery–backed Real–Time Clock 16 slots 32 MB minimum required Upgradeable to 768 MB at HP–UX 9.05 Upgradeable to 1 GB at HP–UX 10.0 48 bit Unified 120 page entries, additional single–entry instruction...
  • Page 3 One 25–pin HP parallel port 8–bit Single–Ended SCSI–2 interface 16–bit Fast, Wide SCSI–3 interface Keyboard port for PS2 mouse Keyboard port for HP HIL devices Audio and speaker output Microphone or audio input Functionality 1GB, low profile, 3.5–inch, Fast, Wide Differential SCSI hard disk drive 2GB, low profile, 3.5–inch, Fast, Wide Differential SCSI hard...

  • Page 4: Internal Storage Devices

    Minimum memory is 32 MB of 60 ns 4 Mbit, or 128 Mbit of 60 ns 16 Mbit DRAMs, or a combination of both. 32 MB is the minimum required for the HP–UX operating system. Each workstation has 16 memory slots, labeled 0A, 0B through 7A, 7B.

  • Page 5: Built-In Interfaces

    Built–In Interfaces System Unit Interfaces The system board’s built–in interfaces have ports on the workstation rear panel. Audio Interfaces The J Class workstations have audio input and output capability through external input and output connectors on the rear panel and through an internal speaker. The rear panel contains the Audio IN (Stereo line–in) and Mic (Mic–in), and Audio OUT (Stereo line–out) and Headphones (Headphone–out) connectors.
  • Page 6 The PS/2 connectors provide an interface for the keyboard and mouse to the system. ITF Keyboard Interface The HP HIL connector provides an interface for the ITF Keyboard to the system and all HP HIL devices. HP Parallel I/O Interface The 25–pin HP Parallel I/O interface uses Centronics interface protocols to support peripheral devices...
  • Page 7 Table 1–3. Supported AUI LAN Adapters and Devices LAN Adaptor HP 28641B ThinLAN Transceiver HP 30241A 10Base4 ThickLAN MAU RS–232 Serial I/O Interfaces The RS–232 Serial I/O (SIO) ports on the J Class accept a variety of pointing devices or peripheral devices.
  • Page 8 Small Computer Systems Interface Use the SCSI connectors to connect external SCSI devices such as DDS–format tape drives and CD–ROM drives. Consult the documentation that accompanies each SCSI device for specific information concerning its use. Refer to Appendix C of the J Class Owner’s Guide for information about connecting SCSI devices to the workstation.
  • Page 9 Single–Ended SCSI–2 The built–in SCSI–2 port is implemented using an NCR710 macrocell inside the I/O ASIC chip. This 8–bit single–ended implementation is synchronous and compatible with the current 700 series products and supports 5 MB/sec data transfer rates. The SCSI bus is terminated to 3.3 volts through 127k on the CPU board.

  • Page 10: Hardware Architecture

    Hardware Architecture The J Class is a mid–tower style designed to be easy to operate and upgrade. The features in this package are designed for user access to the majority of the system’s upgradable parts (disks, memory SIMMs, and processors) without moving the system. Figure 1–1 shows the front view of the system.

  • Page 11: Operating System

    Instant Ignition. HP–UX can also be installed from external DDS or CD–ROM drives. If the workstation is a client on LAN, HP–UX can be booted over the LAN. Table 1–7 lists the HP–UX operating systems and languages for the workstation.

  • Page 12: Product Identification

    Definition (SVID) Issue III (Base System and all Ex- tensions, with exceptions), X/Open Portability Guide Issue IV (XPG4) (Base Branding), and OSF/Motif 1.2. HP–UX 10.0 also complies with IS 9945/1 and Base Com- ponent and all Optional Components except XTI only. HP–UX 10.01 (Model J210XC only)***more info need- ed?*** Version 11 Release 5 (X11R5), OSF/Motif 1.2...

  • Page 13: Support Documentation

    HP A****–**** CPU Module, 120MHz (Model J210XC) HP A4081–69001 System PCA HP A4081–69002 EISA Backplane PCA HP A4072–69512 HCRX Z–Accelerator Board HP A4073–69001 GSC interface for use with CRX–48Z HP A4070–69504 HCRX–8 HP A4071–69507 HCRX–24 HP A4081–69009 Color Graphics Card Board Nonexchange Part Numbers HP A4081–60004 I/O Connector PCA...
  • Page 14 SCSI Tech Reference Manual HP–UX 9.05 Manuals Using your HP workstation HP Vue User’s Guide HP Vue Quick Start Guide HP–UX 9.05 Series 700 Release Notes Read Me First HP–UX 9.05 HP–UX 9.05 PCO Read Me Installing HP–UX Installing Peripherals HP–UX 10.0 Manuals...

  • Page 15: Regulatory And Safety Information

    Regulatory and Safety Information Regulatory Compliance Federal Communications Com. (FCC) 47 CFR Part 15 Subpart J, Class B VCCI Class 1 Industry Canada for Class B Product Safety Underwriters Laboratories (UL) listed UL 1950 Canadian Standards Assoc. (CSA) certified CSA 22.2 950M TUV, license to EN60950 EMKO TUE(74) DK203 Electromagnetic Compatibility (EMC) Directive...
  • Page 16 Power Source Consumption 5.3 Amps RMS max @ 220 Vac, 50 Hz Auto ranging 90 – 132 Vac or 198 – 264 Vac Line frequency 47 – 63 Hz Max. power input 664 watts Environmental Specifications...

  • Page 17: Mechanical Specifications

    Reliability Estimated Annualized Failure Rate (AFR) is based on a parts count and the failure rates of those parts in similar products. The AFR is estimated from the sum of the failure rates of the components’ assemblies. A key assumption is that AFR is constant beyond the early life of the product and before long–term wear out.
  • Page 18 System Board Assembly This board contains several daughter cards, the CPU modules (2), the Memory SIMMs (16), and the ON/OFF system status. It can be accessed and replaced from the system front. There is also a daughter board that has the LCD for system status. The following is a detailed specification of this board: Part Number: Size: Weight:...
  • Page 19 I/O Assembly The I/O board connects directly to the system back plane and contains all of the system’s external I/O connections (See Figure 1–4 in HP9000 J Class Owner’s Guide). This board is removed from the back of the system. The following is a detailed specification of this board: Part Number: Size: Weight:...

  • Page 20: Air Flow

    Electrical Data : Power For Logic Power For LCD Power Supply Current Air Flow 80 mm (3.14 in) NOTE: Clearances given are for the minimum required air flow VDD – Vss 0 min 6.5v max VDD – Vo 0 min 5.0v max (VDD = 5.0v) 1.0ma typ 3.0 ma max 160 mm (6.3 in) 80 mm (3.14 in)
  • Page 21 For:root Printed on:Wed, Sep 4, 1996 12:44:36 From book:skyhawk_tech_ref Document:ch_2 Last saved on:Fri, Apr 19, 1996 11:56:05...

  • Page 22: System Overview

    System Overview Chapter 2 contains the following system information: Functional information on the system board, including a system unit block diagram Specifications for the system board interfaces Descriptions of the 2 CPUs A description of the CPU–Memory–I/O Interconnect Functional Information The system board contains: Two processor modules 16 Memory SIMMs...

  • Page 23: Interface Specifications

    1 GB (16 mbit DRAM) Double height SIMM Interface Specifications This section contains specifications for the LAN interface, the RS–232C port, the HP Parallel port, and the PS/2 interfaces. Below is a summary of the LAN interface on the system board: Intel 82596CA LAN Controller functionality.
  • Page 24 PS/2 standards, also know as Centronics R interface. The hardware is also capable of interfacing to BiTronics type printers that transmit status information back to the workstation. Table 2–3 lists technical information for the HP Parallel interface.

  • Page 25: Central Processing Units

    PS/2 The keyboard and mouse interfaces are implemented by simple serial ports conforming to the defacto industry standard PS/2 specification. Both the keyboard and mouse have a dedicated serial port of their own. The interface ports rely on the software to provide all of their intelligence; therefore, they do not interpret the characters passing through them in either direction.
  • Page 26 Table 2–4. CPU Interface Signal and Power Bus Summary Bus Interface Table 2–5 specifies the interconnect bus signals, bussed on and off the CPU module. Table 2–5. Interconnect Bus Interface Signal List * With respect to CPU ** Arbitrated for as a group; winner drives all these signals.
  • Page 27 Test Access Port (TAP) The CPU module supports the IEEE 1149 standard. Please refer to Table 2–6 for a summary of the Test Access Port signals. These signals are routed to the modules system interface to assist in manufacturing testability. Table 2–6.

  • Page 28: Processor Module

    Table 2–9. Operating Frequency Configuration Bits for J200 and J210 Table 2–10. Operating Frequency Configuration Bits for J210XC Status[6:7] are routed directly to the power system, which senses the configuration before supplying power to the system. Each of the bits is pulled high through a resistor in the power supply. The CPU module ties the bits which should be zero to ground through a 0 ohm resistor.
  • Page 29 Megabytes/second multiprocessor memory and I/O bus. This enables high performance multiprocessor systems without requiring additional processor interface components, further improving the price/performance of a PA7200 based system. The PA7200 CPU chip is fabricated in HP’s proprietary CMOS14 technology which features 0.55 micron devices with three levels of metal interconnect...
  • Page 30 Features The PA7200 supports the following features: Feature Clock Frequency Superscalar Multiprocessor Hardware static branch prediction FP Features Feature Coprocessor Fully pipelined ALU and MPY units External Cache Features Feature Instruction/data cache 64–bit access Hashed address Parity error detection on I/D caches, correction on I–cache 32–byte cache line size, copy–back STORE policy Internal Cache Features Feature...

  • Page 31: Cache Memory

    SRAM with the correct timing specifications. The key difference between this processor’s cache implementations and that of other HP workstation models, is that the write pulse width has been shortened to one clock cycle from two. This requirement is necessary due to copy–ins from the interconnect bus that deliver a double word, compared with Previous Generation Processor bus (Pbus) that transferred one word at a time.
  • Page 32 CPU–Memory–I/O Interconnect Introduction J Class workstations support one or two processors and a single U2 I/O adapter (containing two IOAs) on a single interconnect bus that implements a snoopy coherency protocol. This section summarizes the major points of the processor–memory–I/O interconnect bus. Features The interconnect bus has the following features: Provides a price/performance competitive bus for 1–4 way (maximum of 2–way on J Class)
  • Page 33 Supports coherent I/O, with special transactions for DMA in either 16–byte blocks or cacheline–sized blocks. No aborts or retries No dead cycles for master turn–around Single cycle transaction issue; no separate SADD/MADD/VADD cycles 40–bit physical address support. Peak bandwidth depends on frequency and linesize. Each memory transaction, either read or write, is made up of a single address cycle, plus 2, 4, or 8 data cycles, for 16, 32, or 64 byte lines respectively.
  • Page 34 Split transactions Up to 64 outstanding transactions per client supported 32–byte cache line supported (restricted by memory and IO design) Snoopy coherency protocol Coherent I/O supported Address/Data and Control parity protection Supports EISA as a Lower I/O Bus...
  • Page 35 For:root Printed on:Wed, Sep 4, 1996 12:44:46 From book:skyhawk_tech_ref Document:ch_3 Last saved on:Mon, Apr 22, 1996 09:12:28...

  • Page 36: Memory System

    Memory System Major features of the design are: High–performance design (low latency, high bandwidth) 36–bit Real Addresses (32GB) Supports 4Mbit, 16Mbit and 64Mbit DRAM Technology Supports 4GB of Memory with 64Mbit DRAMs, 1GB of memory with 16Mbit DRAMs Minimum memory increment of 32MB (4Mbit DRAM technology, x4 DRAMs, 2 banks of memory on 2 SIMMs) Coherent I/O Multi–Client support via snoop coherency and Interconnect Bus...
  • Page 37 Memory System Block Diagram The J Class memory system is constructed from four major components: the Master Memory Controller, Slave Memory Controllers, plug in memory modules (SIMMs), and data accumulate/MUX chips (DRAM Data Path MUX). Figure 3–1 shows a block diagram of the J Class memory system. The basic unit of memory is called a bank.
  • Page 38 Figure 3–1. Memory System Block Diagram...
  • Page 39 Figure 3–2. J Class Memory System The master memory controller is the primary interface between the interconnect bus, the system backplane, and the memory array. It helps manage the processor–memory–I/O interconnect bus protocol, including cache coherency and arbitration, provides the programmatic interface for system memory, generates and checks memory ECC, provides buffering of memory write and read transactions from the interconnect bus to the DRAM Controllers, and provides the primary high–speed memory data path to the interconnect bus.
  • Page 40 The multibank DRAM controller provides the next level of control in the memory hierarchy, directly controlling the operation and timing of the DRAMs. Each controller (four are used) – is capable of supporting four independent, 16–byte wide banks of memory. Each bank of memory is used to assemble a 32–byte cache line using a Fast Page Mode DRAM cycle.
  • Page 41 The memory system addresses a wide range of performance and cost design centers. J Class workstations nominally support a 1024 MB (max) memory configuration (using 16 Mbit DRAM). It consists of the master memory controller, four multibank DRAM controllers, one data MUX (implemented with four data MUXes), and between two and 16 SIMMs.
  • Page 42 Figure 3–3. Memory SIMM Loading Order Memory Transaction Behavior The memory system is a large, multistream, pipeline decoupled by queues at critical points. Transactions are buffered at several points within the Master Memory Controller and the multibank DRAM Controller. Figure 3–4 shows a diagram of queue positions, as well as idle issue rates and idle latency for each component in the memory system.
  • Page 43 Figure 3–4. Memory System Queuing and Staging Points Each individual multibank DRAM Controller has its own queue. However, all multibank DRAM Controller queues operate in synchronous harmony, with each multibank DRAM Controller tracking the progress of others through its own queue. In essence, they appear as one. This implementation greatly simplifies the Master/Slave Interface (MSI) protocol, but constrains transactions to execute in exact order.
  • Page 44 When a transaction is received by the multibank DRAM Controller, it immediately begins a memory bank operation. The only circumstances preventing this are a refresh cycle being in progress, or a previous transaction that has not yet completed for that memory bank. Figure 3–5 depicts the transaction flow through the multibank DRAM Controller pipeline, showing that maximum throughput can result from the overlap of multiple memory banks and busses.
  • Page 45 Figure 3–6. The Stalled Pipeline – 192 MB/s (Fast Page Mode DRAM) Performance Considerations Figures 3–5 and 3–6 show the boundaries of memory system performance with respect to cycle time or bandwidth. In reality, the cycle time will lie somewhere in between these two points. Additionally, these factors contribute to “busy”...
  • Page 46 The theoretical maximum bandwidth available from multiple banks is just the sum of the bandwidths available from each individual bank. Table 3–1 summarizes the maximum DRAM bandwidth as a function of the number of banks. Table 3–1. DRAM Bank Bandwidth Table 3–2.
  • Page 47 registers, internal interconnects, and execution units, processor–memory–I/O interconnect bus arbitration and cache coherency responses, and memory system resources, memory banks and DRAM Data busses. The following behaviors are assumed to predict system performance. Uniform distribution of memory addresses. Homogeneity – Transactions arrival rate is a function of memory retirement rate and queue length. Transaction Flow Balance –...
  • Page 48 The primary factor determining memory system throughput and latency is the Average Cycle Time (ACT), or equivalently stated E[S] (average service time), of each transaction. The memory system ACT reflects the memory bank and bus cycle time, as well as the effect of resource contention on them – which is a function of the number of banks and busses.
  • Page 49 Figure 3–7. Data Cycle Time Versus Increasing Fast Page Mode DRAM Banks and Busses Figure 3–8 shows the bandwidth range that the memory system is capable of producing for the conditions specified for EDO DRAM.
  • Page 50 Figure 3–8. Data Cycle Time Versus Increasing EDO DRAM Banks and Busses The above graphs characterize the J Class memory system average cycle time (ACT) and bandwidth for each of the supported configurations. The indicated data points show the effect of increasing numbers of banks and busses on memory system ACT.

  • Page 51: Bandwidth Considerations

    For example, the J Class design limits the number of CCC queue entries to 10. From the above formula, the average issue rate can then be determined to be 10/11, or ~91%, of the service rate. Of course these are very rough approximations.
  • Page 52 Average memory latency (E[W]) can be roughly estimated using the ACT (or average service time E[S].) If Poisson transaction arrivals are assumed, then it may be found using the average issue rate ( ) and average retire rate ( ) as follows: For the purpose of making some comparisons, we will define the term “steady–state”...
  • Page 53 Figure 3–9. Steady–State latency for EDO DRAM (This assumes a FULL 10 entry memory queue)
  • Page 54 For:root Printed on:Wed, Sep 4, 1996 12:44:56 From book:skyhawk_tech_ref Document:ch_4 Last saved on:Tue, Mar 12, 1996 09:01:01...
  • Page 55 These systems rely on EISA to serve all of the general purpose, OEM or 3rd party, connectivity I/O needs. When higher performance is needed, HP’s proprietary GSC (Graphics System Connect) is available for throughputs exceeding EISA’s capability.
  • Page 56 Figure 4–1. J Class I/O System Architecture Graphics System Connect (GSC) GSC is an interconnect consisting primarily of 48 signals, and designed to support a wide range of functions, ranging from DMA I/O devices to host manipulated graphics controllers. Some GSC features include: GSC Features 32–bit shared address/data bus...
  • Page 57 DMA master support Sequential Transaction Request – Prefetch Deadlock resolution – Split signal Big–endian byte ordering Jumperless Address Space Selection Support for Hard Physical Addresses (HPA) Device HPAs Flex Registers Software Programmable Addresses (SPA) These features allow a greater percentage of the system I/O space to be utilized, and provide an architected means for I/O expansion.
  • Page 58 Table 4–1 is a quick reference for the parallel slave registers. Table 4–1. Parallel Slave Registers Register Register Bit Value Abreviation b ev at o Name Address ParReset slv+000 ParData slv+800 ParStatus slv+801 ParDevCtl slv+802 — slv+803 ModeCtl slv+804 IECtlStat slv+805 TDC0 slv+806...
  • Page 59 Table 4–2 shows a parallel DMA register map. Table 4–2. Parallel DMA Register Map Address Type drst+000 write only dma+000 read/write dma+001 read/write dma+008 read only dma+00A write only dma+00B write only dma+00C write only dma+00D write only dma+00E write only dma+00F read/write dma+010...
  • Page 60 If the J Class Parallel Port DMA controller gets a parity error or bus timeout while mastering a transaction, the transaction causing the error will be completed normally, but arbitration will be disabled so no more DMA can be done. The Current Address register will point to the next address to be read after the error.

  • Page 61: Ps2 Interface

    PS2 interface J Class implements the keyboard and mouse interfaces as simple serial ports conforming to the de facto industry standard PS/2 specification. Each user input device has a dedicated serial port of its own. LASI includes two ports, one for keyboard and one for mouse. The interface ports rely on the software to provide all of their intelligence.
  • Page 62 EISA interface Industry Standard Connectivity I/O (EISA) J Class relies on EISA to serve many I/O expansion needs. Examples of functionality available on EISA include 802.3, 802.5, FDDI, SCSI, VME adapters, X.25, Serial MUX, etc.. While the EISA specification allows for higher throughputs (33 MB/second for DMA Masters), J Class’s implementation supports the more modest throughputs estimated below: EISA DMA MASTER: –...
  • Page 63 This module’s purpose is to interface the GSC (System Connect) bus to the EISA bus, giving the system a standard expansion I/O bus. But because of EISA’s complexity, this module does not directly generate EISA bus signals; it generates an i486-like bus, which the “EBCU” (EISA Bus Control Unit) and “EPCU”...
  • Page 64 Functional Description Block Diagram This block diagram describes the GSC to EISA Interface. reset ctrl in bus req bus ack EISA Converter ctrl out address/ data out address/ data in Figure 4–4. i486 reset reset bus req bus ack arbitration control control address...
  • Page 65 Figure 4–5 shows the converter’s address space as seen by the CPU. CPU Address Space $FFBF FFFF $FD00 0000 $FCFF FFFF $FC50 0000 $FC4F F000 $FC10 0000 $FC0F FFFF $FC08 0000 $FC07 FFFF address scrambling $FC02 0000 $FC01 F000 $FC01 E001 $FC01 2001 $FC01 1001 $FC01 0001...
  • Page 66 Figure 4–6 shows (E)ISA memory space as seen by an EISA or ISA master (E)ISA Master Memory Address $FFFF FFFF $03C0 0000 $03BF FFFF $0100 0000 $00FF FFFF $0050 0000 $004F FFFF $0010 0000 $0008 0000 $0000 0000 Figure 4–6. (E)ISA Memory Slave Access $FFFF FFFF...

  • Page 67: Audio Subsystem

    Unsupported EISA options Besides the list of HP supported option cards above, you can install other EISA or ISA board designs. The EISA bus on J Class is an industry standard EISA as implemented by the TI chipset. See the appropriate chip data sheets for more information.
  • Page 68 PDH subsystem The Processor Dependent Hardware subsystem is the hardware that supports the PDC(firmware) in the J Class system. There are two main parts of the PDC, the Flash PROM and Scratch RAM. Scratch RAM is used by both the PDC and the Operating System to store run–time information. The Flash PROM provides storage of PDC code which is the start–up code that runs the system.
  • Page 69 For:root Printed on:Wed, Sep 4, 1996 12:45:02 From book:skyhawk_tech_ref Document:ch_5 Last saved on:Tue, Mar 12, 1996 09:01:03...

  • Page 70: Internal Mass Storage

    SCSI bus. All other devices, external or internal, must not be terminated. Use only HP K2291 terminators to ensure reliable system operation. Consult the documentation that accompanies each SCSI device for specific information concerning its use. Refer to Appendix C of the J Class Owner’s Guide for information about connecting SCSI devices to the workstation.

  • Page 71: Electrical Information

    Electrical Information Power Requirements Table 5–2. Mass Storage Power Requirements Voltage +5 V +12 V Connector Pinouts Pin No. Signal DB[0] DB[1] DB[2] DB[3] DB[4] DB[5] DB[6] DB[7] DB[P] Termpwr H = Host All odd pins are signal returns and must be connected to signal GND at the drive, except pin 25 which is left free to protect against misinsertion.
  • Page 72 Termination Strategy Any single–ended standard SCSI–2 device connecting to the system board must use a 50–pin high–density thumb screw connector on the end connecting to the system board, and a 50–pin low–density bail lock connector on the other end. If you attach a second SCSI–2 device, the cable must have low–density connectors on each end.
  • Page 73 For:root Printed on:Wed, Sep 4, 1996 12:45:05 From book:skyhawk_tech_ref Document:ch_6 Last saved on:Tue, Mar 12, 1996 09:01:06...

  • Page 74: Shipping Carton

    3. Interior Dimensions: L – 28.25 inches, W – 17.75 inches, D – 23.625 inches 4. Closure: Outer stitched seam 5. Markings: Print with ink to match GCMI No. 31 Blue Print per photomasters: 5955–6670 HP company logotype 12 1/2 inches Carton Markings and Placement Figure 6–1. Carton Side Panel Markings and Placement 5955–6677 ISO Symbols –...
  • Page 75 Figure 6–2. Package Tray – Bottom View Figure 6–3. Unpacking Pictorial...
  • Page 76 Figure 6–4. Package Pallet...
  • Page 77 For:root Printed on:Wed, Sep 4, 1996 12:45:09 From book:skyhawk_tech_ref Document:ch_7 Last saved on:Tue, Mar 12, 1996 09:01:07...

  • Page 78: Power Supply Specifications

    Power Supply Functional Information The power supply is a custom designed 484 watt switching converter with a universal AC front end operating from 120/240 V nominal source. The power supply provides five main regulated outputs: +5.1V, +4.5V, +3.4V, +12V, and –12V. It also provides one auxiliary output of +15V that is present whenever AC power is applied to the unit.
  • Page 79 Input Current (230V range) Line Frequency System Board (Dual Processor) SCSI Adapter Multi Function I/O RS232 & Centronics Multimedia HP HIL Drives – 2 x 2 GB FW Drive – CD–ROM Drive – Floppy or DDS Fans Graphics and keyboard Interface EISA...
  • Page 80 For:root Printed on:Wed, Sep 4, 1996 12:45:45 From book:skyhawk_tech_ref Document:ch_8 Last saved on:Tue, Mar 12, 1996 09:02:21...

  • Page 81: Keyboard Layout

    Keyboard Layouts Dimensions The J Class workstation supports 14 different language keyboards. Each keyboard comes with a 7.5 foot mini–DIN style cable. The physical characteristics are as follows: Length: 467 mm (18.4 in) Width: 184 mm (7.25 in) Height: 48 mm (1.9 in) Weight: 1.09 kg (2.4 lb) Japanese version:...
  • Page 82 Figure 8–1. Danish Keyboard...
  • Page 83 Figure 8–2. French Keyboard...
  • Page 84 Figure 8–3. German Keyboard...
  • Page 85 Figure 8–4. Italian Keyboard...
  • Page 86 Figure 8–5. Japanese Keyboard...
  • Page 87 Figure 8–6. Korean Keyboard...
  • Page 88 Figure 8–7. Norwegian Keyboard...
  • Page 89 Figure 8–8. Spanish Keyboard...
  • Page 90 Figure 8–9. Swedish Keyboard...
  • Page 91 Figure 8–10. Swiss Keyboard...
  • Page 92 Figure 8–11. Taiwanese Keyboard...
  • Page 93 Figure 8–12. United Kingdom Keyboard...
  • Page 94 Figure 8–13. United States Keyboard...
  • Page 95 For:root Printed on:Wed, Sep 4, 1996 12:46:15 From book:skyhawk_tech_ref Document:ch_9 Last saved on:Tue, Mar 12, 1996 09:02:22...

  • Page 96: Connector Pinouts

    Connector Pinouts Slot Connectors Table 9–1. RS–232 Connectors (2) Pin No. Signal Row F GROUND ACCESS KEY +12V M–10 LOCK* RESERVED GROUND RESERVED BE*<3> ACCESS KEY BE*<2> BE*<0> GROUND LA*<29> GROUND LA*<26> LA*<24> ACCESS KEY LA<16> LA<14> GROUND LA<10> Pin No. Signal Row B GROUND...
  • Page 97 Pin No. Signal Row E CMD* START* EXRDY EX32* GROUND ACCESS KEY EX16* SLBURST* MSBURST* W–R GROUND RESERVED RESERVED RESERVED GROUND ACCESS KEY BE*<1> LA*<31> GROUND LA*<30> LA*<28> LA*<27> LA*<25> GROUND ACCESS KEY LA<15> LA<13> LA<12> LA<11> GROUND LA<9> Pin No. Signal Row A IOCHK*...
  • Page 98 Pin No. Signal Row H LA<8> LA<6> LA<5> LA<2> ACCESS KEY D<16> D<18> GROUND D<21> D<23> D<24> GROUND D<27> ACCESS KEY D<29> MAKx* Row G LA<7> GROUND LA<4> LA<3> GROUND ACCESS KEY D<17> D<19> D<20> D<22> GROUND D<25> D<26> D<28> ACCESS KEY GROUND D<30>...
  • Page 99 The F/W SCSI connector is part number 1252–4426, a 68–pin high–density D–sub right–angle connector. Table 9–2. RS–232 Connectors (2) Signal Name 1 FW_SD12+ 2 FW_SD13+ 3 FW_SD14+ 4 FW_SD15+ 5 FW_SP1+ 6 Gnd 7 FW_SD0+ 8 FW_SD1+ 9 FW_SD2+ 10 FW_SD3+ 11 FW_SD4+ 12 FW_SD5+ 13 FW_SD6+...

This manual is also suitable for:

Visualize j210

Table of Contents