JVC UX-L40R Service Manual page 32

UX-L40R/UX-L30R
LA72723 (IC3) : RDS demodulation
1. Pin layout
VREF 1
MPXIN 2
Vdda 3
Vssa 4
5
FLOUT
CIN 6
TES 7
XOUT 8
2. Block diagram
+5V
Vdda
REFERENCE
VOLTAGE
Vssa
MPXIN
ANTI ALIASING
FILTER
TEST
3. Pin functions
Pin
Symbol
I/O
No.
1
O
VREF
MPXIN I
2
Vdda
3
Vssa
4
O
5
FLOUT
6 CIN I
TEST I
7
8 XOUT O
9
XIN I
Vssd
10
Vddd
11
I
12 MODE
13
RST I
14 O
RDDA
RDCL I/O
15
RDS-ID
16
O
READY
1-32
RDS-ID/READY
16
RDCL
15
RDDA
14
RST
13
MODE
12
Vddd
11
Vssd
10
XIN
9
FLOUT CIN
VREF
+
-
VREF
57kHz
BPF
(SCF)
SMOOTHING
FILTER
CLK(4.332MHz)
TEST
OSC
XOUT
XIN
Reference voltage output (Vdda/2)
Baseband (multiplexed) signal input
Analog power supply (+5V)
Analog ground
Subcarrier input (filter output)
Subcarrier input (comparator input)
Test input
Crystal oscillator output (4.332MHz)
Crystal oscillator input (exeternal reference input)
Digtal ground
Digtal power supply
Read mode setting (0:master,1:slave)
RDS-ID / RAM reset (positive polarity)
RDS data output
RDS clock output (master mode) / RDS clock input (slave mode)
RDS-ID / READY output (negative polarity)
CLOCK
RECOVERY
PLL
(1187.5Hz)
(57kHz)
DATA
DECODER
RAM
(128-bits)
RDS-ID
DETECT
Function
+5V
Vddd
Vssd
RDDA
RDCL
MODE
RST
RDS-ID/
READY