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LC72136N (IC2) : PLL frequency synthesizer
1. Pin layout
XT
1
22
FM/AM
2
21
CE
3
20
DI
4
19
CLOCK
5
18
DO
6
17
FM/ST/VCO
7
16
AM/FM
8
15
9
14
10
13
SDIN
11
12
2. Block diagram
1
22
16
1/2
15
3
4
C
B
2
I/F
5
6
Power
on
17
Reset
21
3. Pin function
Pin
I/O
Symbol
No.
X'tal oscillator connect (75kHz)
XT
I
1
LOW:FM mode
FM/AM
O
2
When data output/input for 4pin(input) and
I
3
CE
6pin(output): H
Input for receive the serial data from
DI
I
4
controller
Sync signal input use
I
5
CLOCK
Data output for Controller
O
DO
6
Output port
"Low": MW mode
FM/ST/VCO
O
7
Open state after the power on reset
AM/FM
O
8
Input/output port
LW
I/O
9
Input/output port
I/O
10
MW
Data input/output
I/O
SDIN
11
XT
GND
LPFOUT
LPFIN
PD
VCC
FMIN
AMIN
IFCONT
IFIN
Reference
Driver
Swallow Counter
Swallow Counter
1/16,1/17 4bit
1/16,1/17 4bit
12bit
Programmable
DriverS
Data Shift Register & Latch
7
8
2
11 13
Function
Phase
Detector
18
Charge Pump
19
20
Unlock
Detector
12
Universal
Counter
Pin
Symbol
I/O
No.
IF counter signal input
12
IFIN
I
IF signal output
13
IFCONT
O
Not use
-
14
AM Local OSC signal output
15
AMIN
I
FM Local OSC signal input
FMIN
I
16
Power suplly(VDD=4.5-5.5V)
VCC
-
17
When power ON:Reset circuit move
PLL charge pump output(H: Local OSC
18
PD
O
frequency Height than Reference frequency.
L: Low Agreement: Height impedance)
Input for active lowpassfilter of PLL
19
LPFIN
I
Output for active lowpassfilter of PLL
20
LPFOUT
O
Connected to GND
GND
-
21
X'tal oscillator(75KHz)
I
22
XT
UX-L40R/UX-L30R
Function
1-31
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