32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Channel 0: priority=very high, block count=2, block length=2
Channel 1: priority=high,
Channel 2: priority=low,
Priority: CH0 > CH1 > CH2
Priority: CH1 > CH2
Skip: CH0
CH0
CH1
Block 0
Block 0
Priority: CH0 > CH1 > CH2
Skip: n/a
Figure 185. PDMA Channel Arbitration and Scheduling Example
Transfer Request
For a peripheral-to-memory or memory-to-peripheral transfer, one peripheral hardware request will
trigger one block transaction of the dedicated PDMA channel. However, a complete data transfer
of the relevant dedicated PDMA channel will be triggered when a software request occurs. It is
recommended that the PDMA channel is configured to have a lower priority level and a smaller
block length which is requested by the software for memory-to-memory data copy applications.
Address Mode
The PDMA provides three kinds of address modes which are the linear address, circular address
and fixed address modes. These different address modes are used to support different kinds of
source and destination address arrangements. The following table shows the detailed address mode
combinations.
Table 63. PDMA Address Modes
Source Address Mode
Linear Increment / Decrement Address
Linear Increment / Decrement Address
Linear Increment / Decrement Address
Circular Increment / Decrement Address
Circular Increment / Decrement Address
Fixed Address
Fixed Address
Rev. 1.00
block count=3, block length=4
block count=3, block length=6
Priority: CH1 > CH2
Skip: CH0
CH0
CH1
CH2
Block 1
Block 1
Block 0
Priority: CH0 > CH2
Priority: CH2
Skip: CH1
Skip: CH1
509 of 576
Priority: CH1
Skip: CH2
CH1
CH2
Block 2
Block 1
Priority: CH2
Skip: n/a
Destination Address Mode
Linear Increment / Decrement Address
Circular Increment / Decrement Address
Fixed Address
Linear Increment / Decrement Address
Circular Increment / Decrement Address
Linear Increment / Decrement Address
Fixed Address
Priority: CH2
Skip: n/a
CH2
Block 2
Time
January 28, 2022
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