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Holtek HT32F12345 User Manual

Holtek HT32F12345 User Manual

32-bit microcontroller with arm cortex-m3 core

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Holtek 32-Bit Microcontroller with Arm

®

Cortex

®

-M3 Core

HT32F12345

User Manual

Revision: V1.10

Date: November 28, 2018

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Summary of Contents for Holtek HT32F12345

Page 1 Holtek 32-Bit Microcontroller with Arm ® Cortex ® -M3 Core HT32F12345 User Manual Revision: V1.10 Date: November 28, 2018...
Page 2: Table Of Contents
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table of Contents 1 Introduction ......................27 Overview ..........................27 Features ..........................28 Device Information ....................... 32 Block Diagram ........................33 2 Document Conventions ..................34 3 System Architecture ..................... 35 ®...
Page 3 ® Cortex ® -M3 MCU HT32F12345 Flash Vector Mapping Control Register – VMCR ................61 Flash Manufacturer and Device ID Register – MDID ..............62 Flash Page Number Status Register – PNSR ................63 Flash Page Size Status Register – PSSR ..................64 Device ID Register –...
Page 4 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Global Clock Status Register – GCSR ................... 96 Global Clock Interrupt Register – GCIR ..................97 PLL Configuration Register – PLLCFGR ..................99 PLL Control Register – PLLCR ..................... 100 AHB Configuration Register – AHBCFGR ..................101 AHB Clock Control Register –...
Page 5 ® Cortex ® -M3 MCU HT32F12345 Port A Output Current Drive Selection Register – PADRVR ............131 Port A Lock Register – PALOCKR ....................132 Port A Data Input Register – PADINR ................... 133 Port A Output Data Register – PADOUTR ..................133 Port A Output Set / Reset Control Register –...
Page 6 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Alternate Function ......................... 161 Lock Mechanism .......................... 161 Register Map ........................161 Register Descriptions ......................162 EXTI Source Selection Register 0 – ESSR0 ................162 EXTI Source Selection Register 1 – ESSR1 ................163 GPIO x Configuration Low Register –...
Page 7 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Data Format and Alignment ......................190 Analog Watchdog.......................... 190 Interrupts ............................190 PDMA Request ..........................191 Register Map ........................191 Register Descriptions ......................193 ADC Reset Register – ADCRST ....................193 ADC Regular Conversion Mode Register – ADCCONV ............... 194 ADC High Priority Conversion Mode Register –...
Page 8 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 14 General-Purpose Timer (GPTM) ..............224 Introduction ........................224 Features ..........................225 Functional Descriptions ..................... 225 Counter Mode ..........................225 Clock Controller ..........................227 Trigger Controller .......................... 228 Slave Controller ..........................230 Master Controller ..........................
Page 9 ® Cortex ® -M3 MCU HT32F12345 Channel 1 Capture / Compare Register – CH1CCR ..............279 Channel 2 Capture / Compare Register – CH2CCR ..............280 Channel 3 Capture / Compare Register – CH3CCR ..............281 Channel 0 Asymmetric Compare Register – CH0ACR ..............282 Channel 1 Asymmetric Compare Register –...
Page 10 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map ........................326 Register Descriptions ......................327 Timer Counter Configuration Register – CNTCFR ............... 327 Timer Mode Configuration Register – MDCFR ................328 Timer Trigger Configuration Register – TRCFR ................331 Timer Counter Register –...
Page 11 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map ........................368 Register Descriptions ......................369 RTC Counter Register – RTCCNT ....................369 RTC Compare Register – RTCCMP ..................... 370 RTC Control Register – RTCCR ....................371 RTC Status Register – RTCSR..................... 373 RTC Interrupt and Wakeup Enable Register –...
Page 12 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map ........................397 Register Descriptions ......................398 C Control Register – I2CCR ....................... 398 C Interrupt Enable Register – I2CIER ..................400 C Address Register – I2CADDR ....................402 C Status Register – I2CSR ......................402 C SCL High Period Generation Register –...
Page 13 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Interrupts and Status ........................441 PDMA Interface ..........................441 Register Map ........................441 Register Descriptions ......................442 USART Data Register – USRDR ....................442 USART Control Register – USRCR ....................443 USART FIFO Control Register – USRFCR................... 444 USART Interrupt Enable Register –...
Page 14 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map ........................471 Register Descriptions ......................473 USB Control and Status Register – USBCSR ................473 USB Interrupt Enable Register – USBIER ..................475 USB Interrupt Status Register – USBISR ..................476 USB Frame Count Register –...
Page 15 ® Cortex ® -M3 MCU HT32F12345 PDMA Interrupt Status Register 1 – PDMAISR1 ................509 PDMA Interrupt Status Clear Register 0 – PDMAISCR0 .............. 510 PDMA Interrupt Status Clear Register 1 – PDMAISCR1 ...............511 PDMA Interrupt Enable Register 0 – PDMAIER0 ................. 512 PDMA Interrupt Enable Register 1 –...
Page 16 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map ........................549 Register Descriptions ......................550 S Control Register – I2SCR ......................550 S Interrupt Enable Register – I2SIER ..................552 S Clock Divider Register – I2SCDR ................... 553 S TX Data Register – I2STXDR ....................554 S RX Data Register –...
Page 17 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Response Register n – RESPn, n = 0 ~ 3 ..................577 Data Port Register – DR ....................... 578 Present State Register – PSR ...................... 578 Control Register – CR ........................580 Clock Control Register –...
Page 18 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 List of Tables Table 1. Features and Peripheral List ....................32 Table 2. Document Conventions ......................34 Table 3. Register Map ..........................39 Table 4. Flash Memory and Option Byte ....................44 Table 5.
Page 19 ® Cortex ® -M3 MCU HT32F12345 Table 40. MCTM Register Map ......................326 Table 41. MCTM Internal Trigger Connection ..................332 Table 42. LSE Startup Mode Operating Current and Startup Time ............366 Table 43. RTCOUT Output Mode and Active Level Setting ..............367 Table 44.
Page 20 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 80. Response R7 Format ......................569 Table 81. SDIO Command Register Fields and Values ................ 571 Table 82. SDIO Register Map ....................... 572 Rev. 1.10 20 of 590 November 28, 2018...
Page 21 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 List of Figures Figure 1. Block Diagram ......................... 33 Figure 2. Cortex -M3 Block Diagram ...................... 36 ® Figure 3. Bus Architecture ........................37 Figure 4. Memory Map ..........................38 Figure 5. Flash Memory Controller Block Diagram ................. 42 Figure 6.
Page 22 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 40. Down-counting Example ...................... 226 Figure 41. Center-aligned Counting Example ..................227 Figure 42. GPTM Clock Selection Source .................... 228 Figure 43. Trigger Control Block ......................229 Figure 44. Slave Controller Diagram ....................230 Figure 45.
Page 23 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 81. Update Event 1 Dependent Repetition Mechanism Example ..........295 Figure 82. MCTM Clock Selection Source .................... 296 Figure 83. Trigger Control Block ......................297 Figure 84. Slave Controller Diagram ....................298 Figure 85.
Page 24 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 121. CH1XOR Input as Hall Sensor Interface ................323 Figure 122. MCTM PDMA Mapping Diagram ..................325 Figure 123. RTC Block Diagram ......................365 Figure 124. Watchdog Timer Block Diagram ..................375 Figure 125.
Page 25 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 162. UART Serial Data Format ....................457 Figure 163. UART Clock CK_UART and Data Frame Timing ............... 457 Figure 164. USB Block Diagram ......................467 Figure 165. Endpoint Buffer Allocation Example................... 469 Figure 166.
Page 26 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 203. I S-justified Repeat Mode Waveforms ................547 Figure 204. I S-justified Repeat Mode Waveforms (32-bit Channel Extended) ........547 Figure 205. FIFO Data Content Arrangement for Various Modes ............548 Figure 206.
Page 27: Introduction
For more information regarding pin assignment, package and electrical characteristics, please refer to the HT32F12345 datasheet. The device is a high performance and low power consumption 32-bit microcontrollers based around an Arm ®...
Page 28: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ Core ● 32-bit Arm ® Cortex ® -M3 processor core ● Up to 96 MHz operation frequency ● Single-cycle multiplication and hardware division ● Integrated Nested Vectored Interrupt Controller (NVIC) ●...
Page 29 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ▄ Analog Comparator – CMP ● Rail-to-rail comparator ● Each comparator has configurable negative inputs used for flexible voltage selection – Dedicated I/O pin – Internal voltage reference provided by 6-bit scaler ●...
Page 30 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ▄ Real Time Clock – RTC ● 32-bit up-counter with a programmable prescaler ● Alarm function ● Interrupt and Wake-up event ▄ Inter-integrated Circuit – I ● Supports both master and slave modes with a frequency of up to 1 MHz ●...
Page 31 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ● Supports byte, half-word and word data size ● Programmable CRC initial seed value ● CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit data ●...
Page 32: Device Information
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Device Information Table 1. Features and Peripheral List Peripherals HT32F12345 Main Flash (KB) Option Bytes Flash (KB) SRAM (KB) MCTM GPTM Timers BFTM USART UART Communication PDMA 12 channels SDIO GPIO Up to 51...
Page 33: Block Diagram
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Block Diagram SWCLK BOOT0 PA~PC[15:0] TRACESWO SWDIO BOOT1 PD[2:0] Powered by V DD15 TPIU SW-DP /PDR Flash Memory Flash Interface Memory : 96 MHz Cortex XTALIN Processor PDMA GPIO CKCU/ XTALOUT 4 ~ 16 MHz...
Page 34: Document Conventions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Document Conventions Unless otherwise specified, this document uses the conventions which showed as follows. Table 2. Document Conventions Notation Example Description The number string with a 0x prefix indicates a 0x5a05 hexadecimal number.
Page 35: System Architecture
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 System Architecture The system architecture of the device that includes the Arm ® Cortex ® -M3 processor, bus architecture and memory organization will be described in the following sections. The Cortex ®...
Page 36: Bus Architecture
® -M3 Block Diagram Bus Architecture The HT32F12345 device consists of four master and six slaves in the bus architecture. Cortex ® ICode, DCode, System bus and Peripheral Direct Memory Access (PDMA) are the masters, internal SRAM, internal Flash memory, AHB peripherals, external bus interface and two AHB to APB bridges are the slaves.
Page 37: Memory Organization
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Memory Flash Interface Memory ® Cortex Processor PDMA GPIO CKCU/RSTCU Control Control Control Registers Registers Registers SDIO Control/Data Device Peripherals -16/32 Registers NVIC SRAM SRAM Controller PDMA External Bus 12 Channels...
Page 38: Memory Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Memory Map 0x400F_FFFF Reserved 0x400B_8000 0x400B_0000 GPIOA~D 0xFFFF_FFFF 0x400A_C000 Reserved 0x400A_8000 Reserved Reserved 0x400A_2000 0x400A_0000 SDIO 0xE010_0000 0x4009_A000 Reserved Private peripheral bus 0x4009_8000 0xE000_0000 Reserved 0x4009_2000 Reserved 0x4009_0000 PDMA 0x7000_0000 0x4008_C000 Reserved...
Page 39: Table 3. Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 3. Register Map Start Address End Address Peripheral 0x4000_0000 0x4000_0FFF USART0 0x4000_1000 0x4000_1FFF UART0 0x4000_2000 0x4000_3FFF Reserved 0x4000_4000 0x4000_4FFF SPI0 0x4000_5000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF 0x4001_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_2FFF AFIO...
Page 40 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Start Address End Address Peripheral 0x4008_0000 0x4008_1FFF 0x4008_2000 0x4008_7FFF Reserved 0x4008_8000 0x4008_9FFF CKCU/RSTCU 0x4008_A000 0x4008_BFFF CRC-16/32 0x4008_C000 0x4008_FFFF Reserved 0x4009_0000 0x4009_1FFF PDMA Control Registers 0x4009_2000 0x4009_7FFF Reserved 0x4009_8000 0x4009_9FFF EBI Control Registers...
Page 41: Embedded Flash Memory
Flash Memory Controller section. Embedded SRAM Memory The HT32F12345 device contains up to 16 KB on-chip SRAM which is located at address 0x2000_0000. It supports bytes, half-words and full words access operations. In order to reduce the time of read-modify-write operations, the Cortex ®...
Page 42: Flash Memory Controller (Fmc)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Memory Controller (FMC) Introduction The Flash Memory Controller, FMC, provides all the necessary functions, pre-fetch buffer and branch cache for the embedded on-chip Flash memory. The figure below shows the block diagram of FMC which includes programming interface, control register, pre-fetch buffer and access interface.
Page 43: Functional Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Functional Descriptions Flash Memory Map The following figure is the Flash memory map of the system. The address ranges from 0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_0FFF is mapped to Boot Loader with a capacity of 4 KB. Additionally, the region addressed from 0x1FF0_0000 to 0x1FF0_03FF is the alias of Option Byte block with a capacity of 1 KB.
Page 44: Flash Memory Architecture
Cortex ® -M3 MCU HT32F12345 Flash Memory Architecture The Flash memory consists of 63 KB main Flash with 1 KB per page and an 4 KB Information Block for the Boot Loader. The main Flash memory contains a total of 64 pages which can be erased individually.
Page 45: Booting Configuration
® Cortex ® -M3 MCU HT32F12345 Booting Configuration The system provides three kinds of booting mode which can be selected through BOOT0 and BOOT1 pins. The BOOT0 and BOOT1 pins are sampled during a power-on reset or a system reset. Once the logic value on these pins has been determined, the first 4 words of vector will be remapped to the corresponding source according to the booting mode.
Page 46: Page Erase
® Cortex ® -M3 MCU HT32F12345 Page Erase The FMC provides a page erase function which is used to initialize the contents of a Flash memory. Any page can be erased independently without affecting others. The following steps show the access sequence of the register for a page erase operation.
Page 47: Mass Erase
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Mass Erase The FMC provides a mass erase function which is used to initialize the complete Flash memory contents to a high state. The following steps show the mass erase operation sequence. ▄...
Page 48: Word Programming
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Word Programming The FMC provides a 32-bit word programming function which is used to modify the Flash memory contents. The following steps show the word programming register access sequence. ▄ Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0] equal to 0xE or 0x6).
Page 49: Option Byte Description
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Option Byte Description The Option Byte can be treated as an independent Flash memory which base address is 0x1FF0_0000. The following table shows the function description and memory map of Option Byte.
Page 50: Page Erase / Program Protection
® Cortex ® -M3 MCU HT32F12345 Page Erase / Program Protection The FMC provides page erase / program protection functions to prevent inadvertent operations on the Flash memory. The page erase or word programming command will not be accepted by the FMC on the protected pages.
Page 51: Security Protection
Cortex ® -M3 MCU HT32F12345 Security Protection The FMC provides a security protection function to prevent illegal code / data access of the Flash memory. This function is useful for protecting the software / firmware from the illegal users. The function is activated by configuring the OB_CP [0] bit in the Option Byte.
Page 52: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map The following table shows the FMC registers and reset values. Table 10. FMC Register Map Register Offset Description Reset Value FMC Base Address = 0x4008_0000 TADR 0x000 Flash Target Address Register...
Page 53: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Flash Target Address Register – TADR This register specifies the target address of the page erase and word programming operations. Offset: 0x000 Reset value: 0x0000_0000 TADB Type/Reset 0 RW 0 RW...
Page 54: Flash Write Data Register - Wrdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Write Data Register – WRDR This register stores the data to be written into the TADR register for programming operation. Offset: 0x004 Reset value: 0x0000_0000 WRDB Type/Reset 0 RW 0 RW...
Page 55: Flash Operation Command Register - Ocmr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Operation Command Register – OCMR This register is used to specify the Flash operation commands that include word program, page erase and mass erase. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset...
Page 56: Flash Operation Control Register - Opcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Operation Control Register – OPCR This register is used for controlling the command commitment and checking the status of the FMC operations. Offset: 0x010 Reset value: 0x0000_000C Reserved Type/Reset Reserved Type/Reset...
Page 57: Flash Operation Interrupt Enable Register - Oier
® Cortex ® -M3 MCU HT32F12345 Flash Operation Interrupt Enable Register – OIER This register is used to enable or disable the FMC interrupt function. The FMC generates interrupt to the controller when corresponding interrupt enable bits are set. Offset:...
Page 58: Flash Operation Interrupt And Status Register - Oisr
Cortex ® -M3 MCU HT32F12345 Flash Operation Interrupt and Status Register – OISR This register indicates the status which is used to check if an operation has been finished or an error occurs. The status bits, bit [4:0], are available when the corresponding bits in the OIER register are set.
Page 59: Flash Page Erase / Program Protection Status Register - Ppsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions ITADF Invalid Target Address Flag 0: The target address is valid 1: The target address TADR is invalid The data in the TADR field must be within the range from 0x0000_0000 to 0x1FFF_FFFF.
Page 60: Flash Security Protection Status Register - Cpsr
Cortex ® -M3 MCU HT32F12345 Flash Security Protection Status Register – CPSR This register indicates the Flash memory security protection status. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader which is active when any kind of reset occurs.
Page 61: Flash Vector Mapping Control Register - Vmcr
Cortex ® -M3 MCU HT32F12345 Flash Vector Mapping Control Register – VMCR This register is used to control the vector mapping. The reset value of the VMCR register is determined by the external booting pins, BOOT0 and BOOT1, during the power-on reset period.
Page 62: Flash Manufacturer And Device Id Register - Mdid
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Manufacturer and Device ID Register – MDID This register is used to store the manufacture ID and device part number information which can be used as the product identity. Offset: 0x180...
Page 63: Flash Page Number Status Register - Pnsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Page Number Status Register – PNSR This register is used to indicate the Flash memory page number. Offset: 0x184 Reset value: 0x0000_00XX PNSB Type/Reset 0 RO 0 RO 0 RO 0 RO...
Page 64: Flash Page Size Status Register - Pssr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Page Size Status Register – PSSR This register is used to indicate the page size in bytes. Offset: 0x188 Reset value: 0x0000_0400 PSSB Type/Reset 0 RO 0 RO 0 RO 0 RO...
Page 65: Device Id Register - Did
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Device ID Register – DID This register is used to store the device part number information which can be used as the product identity. Offset: 0x18C Reset value: 0x000X_XXXX Reserved Type/Reset Reserved...
Page 66: Flash Pre-Fetch Control Register - Cfcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Flash Pre-fetch Control Register – CFCR This register is used for controlling the FMC cache and pre-fetch module. Offset: 0x200 Reset value: 0x0000_1091 Reserved Type/Reset Reserved Type/Reset Reserved Reserved Type/Reset DCDB Reserved...
Page 67: Sram Booting Vector Register N - Sbvtn, N = 0 ~ 3
Cortex ® -M3 MCU HT32F12345 SRAM Booting Vector Register n – SBVTn, n = 0 ~ 3 These registers specify the initial values of Stack Point, Program Counter, NMI Handler address and Hard Fault Handler address for the SRAM Booting mode.
Page 68: Custom Id Register N - Cidrn, N = 0 ~ 3
® Cortex ® -M3 MCU HT32F12345 Custom ID Register n – CIDRn, n = 0 ~ 3 This register is used to store the custom ID information which can be used as the custom identity. Offset: 0x310 (0) ~ 0x31C (3)
Page 69: Power Control Unit (Pwrcu)
® Cortex ® -M3 MCU HT32F12345 Power Control Unit (PWRCU) Introduction The power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes.
Page 70: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ Three power domains: Backup, V and 1.5 V power domains. ▄ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes. ▄ Internal Voltage regulator supplies 1.5 V voltage source.
Page 71: Vdd Power Domain
® Cortex ® -M3 MCU HT32F12345 Backup Registers and Isolation Cells Ten 32-bit registers, up to 40 bytes, are located in the Backup Domain for user application data storage. These registers are powered by V which constantly supplies power when the 1.5 V core power is switched off.
Page 72: Figure 12. Power On Reset / Power Down Reset Waveform
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Hysteresis Time POR Delay Time RSTD RESET Figure 12. Power On Reset / Power Down Reset Waveform Low Voltage Detector / Brown Out Detector The Low Voltage Detector, LVD, can detect whether the supply voltage V...
Page 73: 1.5 V Power Domain
Cortex ® -M3 MCU HT32F12345 1.5 V Power Domain The main functions that include the APB interface for the backup domain, CPU core logic, AHB / APB peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered up, the POR will generate a reset sequence (Refer to PORB) on 1.5 V power domain.
Page 74: Table 12. Enter / Exit Power Saving Modes
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 12. Enter / Exit Power Saving Modes Mode Entry Mode Mode Exit LDOOFF DMOSON Instruction SLEEPDEEP WFI: Any interrupt WFE: Any wakeup event Sleep Any interrupt (NVIC on) or Any interrupt with...
Page 75: Register Map
Cortex ® -M3 MCU HT32F12345 After a system reset, the PORSTF bit in the RSTCU GRSR register, the PDF and BAKPORF bits in the BAKSR register should be checked by software to confirm if the device is being resumed from the Power-Down mode by a backup domain power on reset, an unexpected loss of the 1.5 V power or other reset events (nRST, WDT,…).
Page 76: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Backup Domain Status Register – BAKSR This register indicates backup domain status. Offset: 0x100 Reset value: 0x0000_0001 (Reset only by Backup Domain reset) Reserved Type/Reset Reserved Type/Reset Reserved WUPF Type/Reset...
Page 77: Backup Domain Control Register - Bakcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Backup Domain Control Register – BAKCR This register provides power control bits for the Deep-Sleep and Power-Down modes. Offset: 0x104 Reset value: 0x0000_0000 (Reset only by Backup Domain reset) Reserved Type/Reset Reserved...
Page 78 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions WUPEN External WAKEUP Pin Enable 0: Disable WAKEUP pin function 1: Enable WAKEUP pin function The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function before entering the power saving mode.
Page 79: Backup Domain Test Register - Baktest
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Backup Domain Test Register – BAKTEST This register specifies a read-only value for the software to recognize whether backup domain is ready for access. Offset: 0x108 Reset value: 0x0000_0027 Reserved Type/Reset Reserved...
Page 80 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [21] LVDEWEN LVD Event Wakeup Enable 0: LVD event wakeup is disabled 1: LVD event wakeup is enabled Setting this bit to 1 will enable the LVD event wakeup function to wake up the system when a LVD condition occurs which result in the LVDF bit being asserted.
Page 81: Backup Register N - Bakregn, N = 0 ~ 9
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Backup Register n – BAKREGn, n = 0 ~ 9 This register specifies backup register n for storing data during the V power-off period. DD15 Offset: 0x200 ~ 0x224 Reset value: 0x0000_0000 (Reset only by Backup Domain reset)
Page 82: Clock Control Unit (Ckcu)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Clock Control Unit (CKCU) Introduction The Clock Control unit (CKCU) provides functions of high speed internal RC oscillator (HSI), High speed external crystal oscillator (HSE), Low speed internal RC oscillator (LSI), Low speed external crystal oscillator (LSE), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler, clock multiplexer and clock gating.
Page 83: Figure 13. Ckcu Block Diagram
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 CKREFPRE Prescaler Divider CK_REF 1 ~ 32 HSI Auto CKREFEN CK_LSE USBSRC Trimming USBPRE Controller USB Frame Pulse Prescaler = 48MHz CK_USB USBPLLSRC 1, 2 USBEN CK_USB USBPLLEN CK_USBPLL STCLK (to SysTick)
Page 84: Functional Descriptions
® Cortex ® -M3 MCU HT32F12345 Functional Descriptions High Speed External Crystal Oscillator (HSE) The high speed external 4 to 16 MHz crystal oscillator (HSE) produces a highly accurate clock source to the system clock. The related hardware configuration is shown in the following figure.
Page 85: High Speed Internal Rc Oscillator (Hsi)
Cortex ® -M3 MCU HT32F12345 The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register (GCCR). The HSERDY flag in the Global Clock Status Register (GCSR) will indicate if the high-speed external crystal oscillator is stable. While switching on the HSE, the HSE clock will still not be released until this HSERDY bit is set by the hardware.
Page 86: Figure 15. Hsi Auto Trimming Block Diagram
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Auto Trimming HSI Block Diagram Fine-Trimming Write Register ATCEN Counter Auto Trimming Register Controller TMSEL External pin (CKIN) 1 kHz /1.024 kHz USB SOF 32.768 kHz REFCLKSEL Fine-Trimming Factory Read Register Trimming Bits...
Page 87: Phase Locked Loop - Pll
Cortex ® -M3 MCU HT32F12345 Phase Locked Loop – PLL This PLL can provide 8 ~ 96 MHz clock output which is 2 ~ 24 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital...
Page 88: Usb Phase Locked Loop - Usb Pll
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 16. Feedback Divider 2 Value Mapping Feedback divider 2 setting B4 ~ B0 (PFBD) NF2 (Feedback divider 2 value) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 ….
Page 89: Table 17. Usb Pll Output Divider 2 Value Mapping
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Frequency of the PLL output clock can be determined by the following formula:             Where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16, NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8.
Page 90: Low Speed External Crystal Oscillator - Lse
Cortex ® -M3 MCU HT32F12345 Low Speed External Crystal Oscillator – LSE The low speed external crystal or ceramic resonator oscillator with 32,768 Hz frequency produces a low power but highly accurate clock source for the circuits of Real-Time-Clock peripheral, Watchdog Timer or system clock.
Page 91: System Clock (Ck_Sys) Selection
Cortex ® -M3 MCU HT32F12345 System Clock (CK_SYS) Selection After the system reset occurs, the high speed internal RC oscillator HSI is selected as the system clock (CK_SYS). The CK_SYS may come from the HSI, HSE, LSE, LSI or PLL output clock and it can be switched from one clock source to another via the System Clock Switch bits (SW) in the Global Clock Control Register (GCCR).
Page 92: Clock Output Capability
Cortex ® -M3 MCU HT32F12345 Clock Output Capability The device has the clock output capability to allow the clocks to be output on the specific external output pin CKOUT. The configuration registers of the corresponding GPIO port must be well configured in the Alternate Function I/O section, AFIO, to output the selected clock signal.
Page 93: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Global Clock Configuration Register – GCFGR This register specifies the clock source for PLL / USART / Watchdog Timer / CKOUT. Offset: 0x000 Reset value: 0x0000_0302 LPMOD Reserved Type/Reset RO...
Page 94: Global Clock Control Register - Gccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions PLLSRC PLL Clock Source Selection 0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE) 1: Internal 8 MHz RC oscillator clock is selected (HSI) Set and reset by software to control PLL clock source.
Page 95 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [16] CKMEN HSE Clock Monitor Enable 0: Disable External 4 ~ 16 MHz crystal oscillator clock monitor 1: Enable External 4 ~ 16 MHz crystal oscillator clock monitor When the hardware detects that the HSE clock stuck at a low or high state, the internal hardware will switch the system clock to the internal high speed HSI RC clock.
Page 96: Global Clock Status Register - Gcsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Global Clock Status Register – GCSR This register indicates the clock ready status. Offset: 0x008 Reset value: 0x0000_0028 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved LSIRDY LSERDY HSIRDY HSERDY PLLRDY USBPLLRDY Type/Reset...
Page 97: Global Clock Interrupt Register - Gcir
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Global Clock Interrupt Register – GCIR This register specifies interrupt enable and flag bits. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE USBPLLRDYIE CKSIE Type/Reset 0 RW...
Page 98 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [16] CKSIE Clock Stuck Interrupt Enable 0: Disable clock failure interrupt 1: Enable clock failure interrupt Set and reset by software to enable or disable the clock failure interrupt caused by clock monitor.
Page 99: Pll Configuration Register - Pllcfgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 PLL Configuration Register – PLLCFGR This register specifies the PLL configurations. Offset: 0x018 Reset value: 0x0000_0000 Reserved PFBD Type/Reset 0 RW 0 RW 0 RW PFBD POTD Reserved Type/Reset 0 RW 0 RW...
Page 100: Pll Control Register - Pllcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 PLL Control Register – PLLCR This register specifies the PLL Bypass mode. Offset: 0x01C Reset value: 0x0000_0000 PLLBPS Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions [31] PLLBPS PLL Bypass Mode Enable...
Page 101: Ahb Configuration Register - Ahbcfgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 AHB Configuration Register – AHBCFGR This register specifies the system clock frequency. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved AHBPRE Type/Reset 0 RW 0 RW Bits Field...
Page 102: Ahb Clock Control Register - Ahbccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 AHB Clock Control Register – AHBCCR This register specifies the AHB clock enable bits. Offset: 0x024 Reset value: 0x0000_00E5 Reserved Type/Reset Reserved PDEN PCEN PBEN PAEN Type/Reset 0 RW 0 RW 0 RW...
Page 103 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11] CKREFEN CK_REF Clock Enable 0: CK_REF clock is disabled 1: CK_REF clock is enabled Set and reset by software [10] USBEN USB Clock Enable 0: USB clock disabled...
Page 104: Apb Configuration Register - Apbcfgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 APB Configuration Register – APBCFGR This register specifies the ADC conversion clock frequency. Offset: 0x028 Reset value: 0x0001_0000 Reserved Type/Reset Reserved ADCDIV Type/Reset 0 RW 0 RW Reserved Type/Reset Reserved Type/Reset Bits...
Page 105: Apb Clock Control Register 0 - Apbccr0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 APB Clock Control Register 0 – APBCCR0 This register specifies the APB peripherals clock enable bits. Offset: 0x02C Reset value: 0x0000_0000 Reserved I2SEN Reserved Type/Reset Reserved Type/Reset EXTIEN AFIOEN Reserved UR1EN UR0EN...
Page 106: Apb Clock Control Register 1 - Apbccr1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions SPI1EN SPI1 Clock Enable 0: SPI1 clock is disabled 1: SPI1 clock is enabled Set and reset by software. SPI0EN SPI0 Clock Enable 0: SPI0 clock is disabled 1: SPI0 clock is enabled Set and reset by software.
Page 107 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [16] BFTM0EN BFTM0 Clock Enable 0: BFTM0 clock is disabled 1: BFTM0 clock is enabled Set and reset by software. GPTM1EN GPTM1 Clock Enable 0: GPTM1 clock is disabled 1: GPTM1 clock is enabled Set and reset by software.
Page 108: Clock Source Status Register - Ckst
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Clock Source Status Register – CKST This register specifies clock source status. Offset: 0x034 Reset value: 0x0100_0003 Reserved HSIST Type/Reset 0 RO 0 RO 0 RO Reserved HSEST Type/Reset 0 RO 0 RO...
Page 109: Apb Peripheral Clock Selection Register 0 - Apbpcsr0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 APB Peripheral Clock Selection Register 0 – APBPCSR0 This register specifies the APB peripheral clock prescaler selection. Offset: 0x038 Reset value: 0x0000_0000 UR1PCLK UR0PCLK USR1PCLK USR0PCLK Type/Reset 0 RW 0 RW 0 RW...
Page 110 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [21:20] GPTM0PCLK GPTM0 Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...
Page 111: Apb Peripheral Clock Selection Register 1 - Apbpcsr1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 APB Peripheral Clock Selection Register 1 – APBPCSR1 This register specifies APB peripheral clock prescaler selection. Offset: 0x03C Reset value: 0x0000_0000 Reserved Type/Reset Reserved I2SPCLK Reserved Type/Reset 0 RW BKPRPCLK WDTRPCLK Reserved...
Page 112: Hsi Control Register - Hsicr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [3:2] EXTIPCLK EXTI Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...
Page 113: Hsi Auto Trimming Counter Register - Hsiatcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [6:5] REFCLKSEL Reference Clock Selection 00: Select 32.768 kHz external low speed clock source (LSE) 01: Select 1 kHz USB SOF package reception 1x: Select external pin (CKIN) 1 kHz pulse This bit is selected the reference clock for the HSI Auto Trimming Controller.
Page 114: Low Power Control Register - Lpcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Low Power Control Register – LPCR This register specifies the low power control. Offset: 0x300 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved USBSLEEP Type/Reset Reserved BKISO Type/Reset Bits Field Descriptions USBSLEEP...
Page 115: Mcu Debug Control Register - Mcudbgcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 MCU Debug Control Register – MCUDBGCR This register specifies the MCU debug control. Offset: 0x304 Reset value: 0x0000_0000 Reserved Type/Reset Reserved DBTRACE DBUR1 DBUR0 DBBFTM1 DBBFTM0 Type/Reset 0 RW 0 RW 0 RW...
Page 116 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [12] DBI2C0 C0 Debug Mode Enable 0: Same behavior as in normal mode 1: I C0 timeout is frozen when the core is halted Set and reset by software.
Page 117: Reset Control Unit (Rstcu)
® Cortex ® -M3 MCU HT32F12345 Reset Control Unit (RSTCU) Introduction The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and APB unit reset. The power on reset, known as a cold reset, resets the full system during a power up.
Page 118: System Reset
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 DD15 PORRESETn SYSRESETn = 25 us *Typical. = 100 us = 150 us * This timing is dependent on the internal LDO regulator output capacitor value. Figure 20. Power On Reset Sequence...
Page 119: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Global Reset Status Register – GRSR This register specifies a variety of reset status conditions. Offset: 0x100 Reset value: 0x0000_0008 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PORSTF WDTRSTF EXTRSTF SYSRSTF...
Page 120: Ahb Peripheral Reset Register - Ahbprstr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 AHB Peripheral Reset Register – AHBPRSTR This register specifies several AHB peripherals software reset control bits. Offset: 0x104 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved SDIORST Reserved PDRST PCRST PBRST PARST...
Page 121: Apb Peripheral Reset Register 0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions USBRST USB Reset Control 0: No reset 1: Reset USB This bit is set by software and cleared to 0 by hardware automatically. DMARST Peripheral DMA (PDMA) Reset Control...
Page 122: Apb Peripheral Reset Register 1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions USR1RST USART1 Reset Control 0: No reset 1: Reset USART1 This bit is set by software and cleared to 0 by hardware automatically. USR0RST USART0 Reset Control 0: No reset 1: Reset USART0 This bit is set by software and cleared to 0 by hardware automatically.
Page 123 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [22] CMPRST Comparator Controller Reset Control 0: No reset 1: Reset CMP This bit is set by software and cleared to 0 by hardware automatically. [17] BFTM1RST BFTM1 Reset Control...
Page 124: General Purpose I/O (Gpio)
® Cortex ® -M3 MCU HT32F12345 General Purpose I/O (GPIO) Introduction There are up to 51 General Purpose I/O ports, GPIO, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15 and PD0 ~ PD2 for the device to implement the logic Input / output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirement of specific applications.
Page 125: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ Input / output direction control ▄ Input weak pull-up / pull-down control ▄ Output push-pull / open drain enable control ▄ Output set / reset control ▄ Output drive current selection ▄...
Page 126: Table 22. Afio, Gpio And I/O Pad Control Signal True Table
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 PxCFGn Input DMUX Output AFIO OENIP Control IOPAD AFIO ADEN PxDOn PxDIn PxRSTn PxDVn PxINENn PxSETn PxODn PxDIRn PxPDn PxPUn GPIO PxDIn / PxDOn (x = A ~ D): Data Input / Data Output...
Page 127: Gpio Locking Mechanism
Cortex ® -M3 MCU HT32F12345 GPIO Locking Mechanism The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR (x = A ~ D) registers are used to lock the port x and lock control options. The value 0x5FA0 is...
Page 128: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Offset Description Reset Value PCDOUTR 0x020 Port C Data Output Register 0x0000_0000 PCSRR 0x024 Port C Output Set and Reset Control Register 0x0000_0000 PCRR 0x028 Port C Output Reset Control Register...
Page 129: Port A Input Function Enable Control Register - Painer
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port A Input Function Enable Control Register – PAINER This register is used to enable or disable the GPIO Port A input function. Offset: 0x004 Reset value: 0x0000_0300 Reserved Type/Reset Reserved Type/Reset...
Page 130: Port A Pull-Down Selection Register - Papdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [15:0] PAPUn GPIO Port A pin n Pull-Up Selection Control Bits (n = 0 ~ 15) 0: Pin n pull-up function is disabled 1: Pin n pull-up function is enabled...
Page 131: Port A Open Drain Selection Register - Paodr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port A Open Drain Selection Register – PAODR This register is used to enable or disable the GPIO Port A open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 132: Port A Lock Register - Palockr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port A Lock Register – PALOCKR This register specifies the GPIO Port A lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PALKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 133: Port A Data Input Register - Padinr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port A Data Input Register – PADINR This register specifies the GPIO Port A input data. Offset: 0x01C Reset value: 0x0000_3300 Reserved Type/Reset Reserved Type/Reset PADIN Type/Reset 0 RO 0 RO 1 RO...
Page 134: Port A Output Set / Reset Control Register - Pasrr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port A Output Set / Reset Control Register – PASRR This register is used to set or reset the corresponding bit of the GPIO Port A output data. Offset: 0x024 Reset value: 0x0000_0000...
Page 135: Port A Output Reset Register - Parr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port A Output Reset Register – PARR This register is used to reset the corresponding bit of the GPIO Port A output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 136: Port B Input Function Enable Control Register - Pbiner
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port B Input Function Enable Control Register – PBINER This register is used to enable or disable the GPIO Port B input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 137: Port B Pull-Down Selection Register - Pbpdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port B Pull-Down Selection Register – PBPDR This register is used to enable or disable the GPIO Port B pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPD Type/Reset...
Page 138: Port B Output Current Drive Selection Register - Pbdrvr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port B Output Current Drive Selection Register – PBDRVR This register specifies the GPIO Port B output driving current. Offset: 0x014 Reset value: 0x0000_0000 PBDV15 PBDV14 PBDV13 PBDV12 Type/Reset 0 RW 0 RW...
Page 139: Port B Data Input Register - Pbdinr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [31:16] PBLKEY GPIO Port Block Key 0x5FA0: Port Block function is enable Others: Port B Lock function is disable To lock the Port B function, a value 0x5FA0 should be written into the PBLKEY field in this register.
Page 140: Port B Output Data Register - Pbdoutr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port B Output Data Register – PBDOUTR This register specifies the GPIO Port B output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBDOUT Type/Reset 0 RW 0 RW 0 RW...
Page 141: Port B Output Set / Reset Control Register - Pbsrr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port B Output Set / Reset Control Register – PBSRR This register is used to set or reset the corresponding bit of the GPIO Port B output data. Offset: 0x024 Reset value: 0x0000_0000...
Page 142: Port B Output Reset Register - Pbrr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port B Output Reset Register – PBRR This register is used to reset the corresponding bit of the GPIO Port B output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 143: Port C Input Function Enable Control Register - Pciner
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port C Input Function Enable Control Register – PCINER This register is used to enable or disable the GPIO Port C input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 144: Port C Pull-Down Selection Register - Pcpdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [15:0] PCPUn GPIO Port C pin n Pull-Up Selection Control Bits (n = 0 ~ 15) 0: Pin n pull-up function is disabled 1: Pin n pull-up function is enabled...
Page 145: Port C Open Drain Selection Register - Pcodr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port C Open Drain Selection Register – PCODR This register is used to enable or disable the GPIO Port C open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 146: Port C Lock Register - Pclockr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [31:0] PCDVn[1:0] GPIO Port C pin n Output Current Drive Selection Control Bits (n = 0 ~ 15) 00: 4 mA source / sink current 01: 8 mA source / sink current...
Page 147: Port C Data Input Register - Pcdinr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [15:0] PCLOCKn GPIO Port C pin n Lock Control Bits (n = 0 ~ 15) 0: Port C pin n is not locked 1: Port C pin n is locked The PCLOCKn bits are used to lock the configurations of corresponding GPIO Pins when the correct Lock Key is applied to the PCLKEY field.
Page 148: Port C Output Data Register - Pcdoutr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port C Output Data Register – PCDOUTR This register specifies the GPIO Port C output data. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCDOUT Type/Reset 0 RW 0 RW 0 RW...
Page 149: Port C Output Set / Reset Control Register - Pcsrr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port C Output Set / Reset Control Register – PCSRR This register is used to set or reset the corresponding bit of the GPIO Port C output data. Offset: 0x024 Reset value: 0x0000_0000...
Page 150: Port C Output Reset Register - Pcrr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port C Output Reset Register – PCRR This register is used to reset the corresponding bit of the GPIO Port C output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 151: Port D Input Function Enable Control Register - Pdiner
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Input Function Enable Control Register – PDINER This register is used to enable or disable the GPIO Port D input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 152: Port D Pull-Up Selection Register - Pdpur
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Pull-Up Selection Register – PDPUR This register is used to enable or disable the GPIO Port D pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 153: Port D Pull-Down Selection Register - Pdpdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Pull-Down Selection Register – PDPDR This register is used to enable or disable the GPIO Port D pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 154: Port D Open Drain Selection Register - Pdodr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Open Drain Selection Register – PDODR This register is used to enable or disable the GPIO Port D open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 155: Port D Lock Register - Pdlockr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Lock Register – PDLOCKR This register specifies the GPIO Port D lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PDLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 156: Port D Data Input Register - Pddinr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Data Input Register – PDDINR This register specifies the GPIO Port D input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved PDDIN Type/Reset 0 RO...
Page 157: Port D Output Set / Reset Control Register - Pdsrr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Output Set / Reset Control Register – PDSRR This register is used to set or reset the corresponding bit of the GPIO Port D output data. Offset: 0x024 Reset value: 0x0000_0000...
Page 158: Port D Output Reset Register - Pdrr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Port D Output Reset Register – PDRR This register is used to reset the corresponding bit of the GPIO Port D output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 159: Alternate Function Input / Output Control Unit (Afio)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Alternate Function Input / Output Control Unit (AFIO) Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each I/O pin can be configured to have up to sixteen different functions such as GPIO or IP functions by setting the GPxCFGLR or GPxCFGHR register where x is the different port name.
Page 160: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ APB slave interface for register access ▄ EXTI source selection ▄ Configurable pin function for each GPIO, up to sixteen alternative functions on each pin ▄ AFIO lock mechanism Functional Descriptions External Interrupt Pin Selection The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure.
Page 161: Alternate Function
Cortex ® -M3 MCU HT32F12345 Alternate Function Up to sixteen alternative functions can be chosen for each I/O pad by setting the PxCFGn [3:0] field in the GPxCFGLR or GPxCFGHR (n = 0 ~ 15, x = A ~ D) registers. Refer to the “Alternate function mapping”...
Page 162: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions EXTI Source Selection Register 0 – ESSR0 This register specifies the I/O selection of EXTI0 ~ EXTI7. Offset: 0x000 Reset value: 0x0000_0000 EXTI7PIN EXTI6PIN Type/Reset 0 RW 0 RW 0 RW...
Page 163: Exti Source Selection Register 1 - Essr1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EXTI Source Selection Register 1 – ESSR1 This register specifies the I/O selection of EXTI8 ~ EXTI15. Offset: 0x004 Reset value: 0x0000_0000 EXTI15PIN EXTI14PIN Type/Reset RW 0 RW 0 RW 0 RW...
Page 164: Gpio X Configuration Low Register - Gpxcfglr, X = A, B, C, D
® Cortex ® -M3 MCU HT32F12345 GPIO x Configuration Low Register – GPxCFGLR, x = A, B, C, D This low register specifies the alternate function of GPIO Port x. x = A, B, C, D Offset: 0x020, 0x028, 0x030, 0x038...
Page 165: Gpio X Configuration High Register - Gpxcfghr, X = A, B, C, D
® Cortex ® -M3 MCU HT32F12345 GPIO x Configuration High Register – GPxCFGHR, x = A, B, C, D This high register specifies the alternate function of GPIO Port x. x = A, B, C, D Offset: 0x024, 0x02C, 0x034, 0x03C...
Page 166: Nested Vectored Interrupt Controller (Nvic)
® Cortex ® -M3 MCU HT32F12345 Nested Vectored Interrupt Controller (NVIC) Introduction In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled integrated section, which is named as Nested Vectored Interrupt Controller (NVIC) is provided by the Cortex -M3.
Page 167 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Exception Interrupt Exception Vector Priority Description Type Number Number Address — — 0x04C Reserved Configurable 0x050 RTC global interrupt Configurable 0x054 FMC global interrupt EVWUP Configurable 0x058 EXTI event wakeup interrupt LPWUP...
Page 168 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Exception Interrupt Exception Vector Priority Description Type Number Number Address USART0 Configurable 0x0FC USART0 global interrupt USART1 Configurable 0x100 USART1 global interrupt UART0 Configurable 0x104 UART0 global interrupt UART1 Configurable 0x108 UART1 global interrupt —...
Page 169: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ 16 system Cortex -M3 exceptions ® ▄ Up to 64 Maskable peripheral interrupts ▄ 16 programmable priority levels (4 bits for interrupt priority setting) ▄ Non-Maskable interrupt ▄ Low-latency exception and interrupt handling ▄...
Page 170 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Offset Description Reset Value ICPR64_95 0x288 Irq 64 to 95 Clear Pending Register 0x0000_0000 IABR0_31 0x300 Irq 0 to 31 Active Bit Register 0x0000_0000 IABR32_63 0x304 Irq 32 to 63 Active Bit Register...
Page 171: External Interrupt / Event Controller (Exti)
® Cortex ® -M3 MCU HT32F12345 External Interrupt / Event Controller (EXTI) Introduction The External Interrupt / Event Controller, EXTI, comprises 16 edge detectors which can generate a wake-up event or interrupt requests independently. In interrupt mode there are five trigger types...
Page 172: Functional Descriptions
® Cortex ® -M3 MCU HT32F12345 Functional Descriptions Wakeup Event Management In order to wakeup the system from the power saving mode, the EXTI controller provides a function which can monitor external events and send them to the CPU core and the Clock Control Unit, CKCU.
Page 173: External Interrupt / Event Line Mapping
Cortex ® -M3 MCU HT32F12345 External Interrupt / Event Line Mapping All GPIO pins can be selected as EXTI trigger sources by configuring the EXTInPIN [3:0] field in the AFIO ESSRn (n = 0 ~ 1) register to trigger an interrupt or event. Refer to the AFIO section for more details.
Page 174: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map The following table shows the EXTI registers and reset values. Table 28. EXTI Register Map Register Offset Description Reset Value EXTI Base Address = 0x4002_4000 EXTICFGR0 0x000 EXTI Interrupt 0 Configuration Register...
Page 175: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions EXTI Interrupt Configuration Register n – EXTICFGRn, n = 0 ~ 15 This register is used to specify the de-bounce function and select the trigger type. Offset: 0x000 (0) ~ 0x03C (15)
Page 176: Exti Interrupt Control Register - Exticr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EXTI Interrupt Control Register – EXTICR This register is used to control the EXTI interrupt. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN...
Page 177: Exti Interrupt Edge Status Register - Extiedgesr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EXTI Interrupt Edge Status Register – EXTIEDGESR This register indicates the polarity of a detected EXTI edge. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS...
Page 178: Exti Interrupt Wakeup Control Register - Extiwakupcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR This register is used to control the EXTI interrupt and wakeup function. Offset: 0x050 Reset value: 0x0000_0000 EVWUPIEN Reserved Type/Reset Reserved Type/Reset EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN...
Page 179: Exti Interrupt Wakeup Polarity Register - Extiwakuppolr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR This register is used to select the EXTI line interrupt wakeup polarity. 0x054 Offset: Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL...
Page 180: Analog To Digital Converter (Adc)
® Cortex ® -M3 MCU HT32F12345 Analog to Digital Converter (ADC) Introduction A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are a total of 14 multiplexed channels including 12 external channels on which the external analog signal can be supplied and 2 internal channels.
Page 181: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ 12-bit SAR ADC engine ▄ Up to 1 MSPS conversion rate ● 1 μs at 84 MHz, 1.17 μs at 96 MHz ▄ 12 external analog input channels ▄ 2 internal analog input channels for reference voltage detection ▄...
Page 182: Functional Descriptions
® Cortex ® -M3 MCU HT32F12345 Functional Descriptions ADC Clock Setup The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details. Notes that ADC peripheral needs keeping at least two ADC clock cycles to switch between power-on and power off stage (ADEN bit = ‘0’).
Page 183: Figure 29. One Shot Conversion Mode
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 High Priority Conversion: ▄ The converted data will be stored in the 16-bit ADCHDRy (y = 0 ~ 3) registers. ▄ The ADC high priority single sample end of conversion event raw status flag, ADIRAWHS, in the ADCIRAW register will be set when the conversion is finished.
Page 184: Figure 30. Continuous Conversion Mode
® Cortex ® -M3 MCU HT32F12345 Continuous Conversion Mode In Continuous Conversion Mode, repeated conversion cycle will start automatically without requiring additional A/D start trigger signals after a channel group conversion has completed. When the A/D conversion mode field ADMODE [1:0] is set to 0x2 or ADHMODE [1:0] is set to...
Page 185 ® Cortex ® -M3 MCU HT32F12345 Discontinuous Conversion Mode Regular group The A/D converter will operate in the Discontinuous Conversion Mode for regular groups when the A/D conversion mode bit field ADMODE [1:0] in the ADCCONV register is set to 0x3. The regular group to be converted can have up to 12 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 2.
Page 186: Figure 31. Regular Group Discontinuous Conversion Mode
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Discontinuous Conversion Mode (ex: Sequence Length = 8, Subgroup Length = 3 ) Cycle Cycle Subgroup 0 Subgroup 1 Subgroup 2 Subgroup 0 Start of Conversion Single sample End of Conversion Subgroup End...
Page 187: Start Conversion On External Event
Cortex ® -M3 MCU HT32F12345 Example: A/D subgroup length = 2 (ADHSUBL = 1) and sequence length = 3 (ADHSEQL = 2), channels to be converted = 4, 7 and 1 – specific converting sequence as defined in the ADCHLST register, ▄...
Page 188: High Priority Group Management
Cortex ® -M3 MCU HT32F12345 In addition to the internal trigger sources, the A/D converter can be triggered to start a conversion by an external trigger event. The external trigger event is derived from the external lines EXTIn. If the external trigger enable bit, ADEXTI or ADHEXTI, is set to 1 and the corresponding EXTI line is selected by configuring the ADEXTIS or ADHEXTIS bit for regular group or high priority group, the A/D converter will start a conversion when an EXTI line active edge occurs.
Page 189: Figure 33. High Priority Group Management
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ◆ Regular Group : Sequence Length=5, Subgroup Length=3, discontinuous conversion mode ◆ High Priority Group : Sequence Length=3, one shot conversion mode Regular Group Cycle Regular Group Cycle Conversion Aborted High Priority Group...
Page 190: Data Format And Alignment
Cortex ® -M3 MCU HT32F12345 Data Format and Alignment The A/D Conversion result can have different output data format, selected by configuring the ADOFE and ADAL bits in the ADCOFRn (n = 0 ~ 11) registers, which is shown as following table.
Page 191: Pdma Request
Cortex ® -M3 MCU HT32F12345 After a conversion has completed, the 12-bit digital data will be stored in the associated ADCDRy or ADCHDRy register and the value of the data valid flag, named as ADVLDy or ADHVLDy, will be changed from low to high. The converted data should be read by the application program, after which the data valid flag ADVLDy or ADHVLDy will be automatically changed from high to low.
Page 192 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Offset Description Reset Value ADCOFR7 0x04C ADC Input 7 Offset Register 0x0000_0000 ADCOFR8 0x050 ADC Input 8 Offset Register 0x0000_0000 ADCOFR9 0x054 ADC Input 9 Offset Register 0x0000_0000 ADCOFR10 0x058 ADC Input 10 Offset Register...
Page 193: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions ADC Reset Register – ADCRST ADC software reset register. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved ADRST Type/Reset Bits Field Descriptions ADRST ADC Software Reset...
Page 194: Adc Regular Conversion Mode Register - Adcconv
Cortex ® -M3 MCU HT32F12345 ADC Regular Conversion Mode Register – ADCCONV This register specifies the mode setting, queue length, and subgroup length of ADC regular conversion mode. Note that once the content of ADCCONV is changed, the regular conversion in progress will be aborted and ADC will be reset.
Page 195: Adc High Priority Conversion Mode Register - Adchconv
Cortex ® -M3 MCU HT32F12345 ADC High Priority Conversion Mode Register – ADCHCONV This register specifies the mode setting, queue length, and subgroup length of ADC high priority conversion mode. Note that once the content of ADCHCONV is changed, the high priority conversion in progress will be aborted and ADC will be reset.
Page 196: Adc Regular Conversion List Register 0 - Adclst0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Regular Conversion List Register 0 – ADCLST0 This register specifies the conversion sequence order No.0 ~ No.3 of the ADC regular group. Offset: 0x010 Reset value: 0x0000_0000 Reserved ADSEQ3 Type/Reset 0 RW...
Page 197: Adc Regular Conversion List Register 1 - Adclst1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Regular Conversion List Register 1 – ADCLST1 This register specifies the conversion sequence order No.4 ~ No.7 of the ADC regular group. Offset: 0x014 Reset value: 0x0000_0000 Reserved ADSEQ7 Type/Reset 0 RW...
Page 198: Adc Regular Conversion List Register 2 - Adclst2
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Regular Conversion List Register 2 – ADCLST2 This register specifies the conversion sequence order No.8 ~ No.11 of the ADC regular group. Offset: 0x018 Reset value: 0x0000_0000 Reserved ADSEQ11 Type/Reset 0 RW...
Page 199: Adc High Priority Conversion List Register - Adchlst
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC High Priority Conversion List Register – ADCHLST This register specifies the conversion sequence order No.0 ~ No.3 of the ADC high priority group. Offset: 0x020 Reset value: 0x0000_0000 Reserved ADHSEQ3 Type/Reset...
Page 200: Adc Input Offset Register N - Adcofrn, N = 0 ~ 11
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Input Offset Register n – ADCOFRn, n = 0 ~ 11 This register specifies the ADC input channel n offset together with the offset cancellation function enable control. Offset: 0x030 ~ 0x05C...
Page 201: Adc Input Sampling Time Register N - Adcstrn, N = 0 ~ 11
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Input Sampling Time Register n – ADCSTRn, n = 0 ~ 11 This register specifies the sampling time of ADC channel n. Offset: 0x070 ~ 0x09C Reset value: 0x0000_0000 Reserved Type/Reset...
Page 202: Adc High Priority Conversion Data Register Y - Adchdry, Y = 0 ~ 3
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC High Priority Conversion Data Register y – ADCHDRy, y = 0 ~ 3 This register specifies the high priority conversion data of ADC sequence order ADHSEQy in the ADCHLST register. Offset:...
Page 203: Adc Regular Trigger Control Register - Adctcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Regular Trigger Control Register – ADCTCR This register contains the ADC start conversion trigger enable bits of the regular conversion. Offset: 0x100 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 204: Adctsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Regular Trigger Source Register – ADCTSR This register contains the trigger source selection and the software trigger bit of the regular conversion. Offset: 0x104 Reset value: 0x0000_0000 Reserved Type/Reset 0 RW...
Page 205: Adc High Priority Trigger Control Register - Adchtcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC High Priority Trigger Control Register – ADCHTCR This register contains the ADC start conversion trigger enable bits of the high priority conversion. Offset: 0x110 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...
Page 206: Adc High Priority Trigger Source Register - Adchtsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC High Priority Trigger Source Register – ADCHTSR This register contains the trigger source selection and the software trigger bit of the high priority conversion. Offset: 0x114 Reset value: 0x0000_0000 Reserved HTME...
Page 207: Adc Watchdog Control Register - Adcwcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Watchdog Control Register – ADCWCR This register provides the control bits and status of the ADC watchdog function. Offset: 0x120 Reset value: 0x0000_0000 Reserved ADUCH Type/Reset 0 RO 0 RO 0 RO...
Page 208: Adc Watchdog Lower Threshold Register - Adcltr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Watchdog Lower Threshold Register – ADCLTR This register specifies the lower threshold of the ADC watchdog function. Offset: 0x124 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ADLT Type/Reset 0 RW...
Page 209: Adc Interrupt Enable Register - Adcier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Interrupt Enable Register – ADCIER This register contains the ADC interrupt enable bits. Offset: 0x130 Reset value: 0x0000_0000 Reserved ADIEHO ADIEO Type/Reset 0 RW Reserved ADIEU ADIEL Type/Reset 0 RW Reserved...
Page 210: Adc Interrupt Raw Status Register - Adciraw
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC Interrupt Raw Status Register – ADCIRAW This register contains the ADC interrupt raw status bits. Offset: 0x134 Reset value: 0x0000_0000 Reserved ADIRAWHO ADIRAWO Type/Reset Reserved ADIRAWU ADIRAWL Type/Reset Reserved ADIRAWHC ADIRAWHG ADIRAWHS...
Page 211: Adc Interrupt Status Register - Adcisr
Cortex ® -M3 MCU HT32F12345 ADC Interrupt Status Register – ADCISR This register contains the ADC interrupt status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.
Page 212 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions ADISRHS ADC High Priority Single EOC Interrupt Status 0: ADC high priority single end of conversion interrupt is not occurred or high priority single end of conversion interrupt is disabled...
Page 213: Adc Interrupt Clear Register - Adciclr
Cortex ® -M3 MCU HT32F12345 ADC Interrupt Clear Register – ADCICLR This register provides the clear bits used to clear the interrupt raw and interrupt status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.
Page 214: Adc Dma Request Register - Adcdmar
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADC DMA Request Register – ADCDMAR This register contains the ADC DMA request enable bits. Offset: 0x140 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ADDMAHC ADDMAHG ADDMAHS Type/Reset 0 RW 0 RW...
Page 215: Comparator (Cmp)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Comparator (CMP) Introduction Two general purpose comparators, CMP, are implemented within the devices. They can be configured either as standalone comparators or combined with the different kinds of peripheral IP. Each comparator is capable of asserting interrupts to the NVIC or wake up the CPU from the Sleep or Deep Sleep mode through EXTI wakeup event management unit.
Page 216: Functional Descriptions
® Cortex ® -M3 MCU HT32F12345 Functional Descriptions Comparator Inputs and Output The I/O pins used as comparator inputs or output must be configured in the AFIO controller registers. The detail comparator I/Os information will be referred in pin assignment table in the datasheet.
Page 217: Interrupts And Wakeup
® Cortex ® -M3 MCU HT32F12345 Interrupts and Wakeup The comparator can generate an interrupt when its output waveform generates a rising or falling edge and its corresponding interrupt enables control bit is also set. For example, when a comparator output rising edge occurs, the comparator rising edge flag bit CMPRF in the Comparator Transition Flag Register CMPTFR will be set.
Page 218: Power Mode And Hysteresis
® Cortex ® -M3 MCU HT32F12345 Power Mode and Hysteresis The comparator response time can be programmed to meet the trade-off between the power consumption and application requirement. The bit CMPSM in CMPCR register can be programmed as “0” to get the comparator in the low speed mode and low power consumption.
Page 219: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Comparator Control Register n – CMPCRn, n = 0 ~ 1 This register contains the comparator and comparator voltage reference control bits. Offset: 0x000 (n = 0), 0x100 (n = 1)
Page 220 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 [13:11] CMPOSEL Comparator 0 Output Selection 000: No selection 001: GPTM0 capture channel 3 010: MCTM0 capture channel 3 011: MCTM0 break input 1 100: ADC trigger input Other: Reserved Comparator 1 Output Selection...
Page 221: Comparator Voltage Reference Value Register N - Cvrvalrn, N = 0 ~ 1
® Cortex ® -M3 MCU HT32F12345 Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 ~ 1 The register is used to set the level of comparator voltage reference. Offset: 0x004 (n = 0), 0x104 (n = 1)
Page 222: Comparator Interrupt Enable Register N - Cmpiern, N = 0 ~ 1
® Cortex ® -M3 MCU HT32F12345 Comparator Interrupt Enable Register n – CMPIERn, n = 0 ~ 1 The register is used to enable the comparator n interrupt when the comparator output transition event occurs. Offset: 0x008 (n = 0), 0x108 (n = 1)
Page 223: Comparator Transition Flag Register N - Cmptfrn, N = 0 ~ 1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Comparator Transition Flag Register n – CMPTFRn, n = 0 ~ 1 This register contains the comparator n transition detection enable and flag. Offset: 0x00C (n = 0), 0x10C (n = 1)
Page 224: General-Purpose Timer (Gptm)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 General-Purpose Timer (GPTM) Introduction The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture / Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.
Page 225: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ 16-bit up/down auto-reload counter ▄ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536 ▄ Up to 4 independent channels for: ●...
Page 226: Figure 39. Up-Counting Example
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 CK_PSC CNT_EN CK_CNT CNTR CRR Shadow Register PSCR PSCR Shadow Register PSC_CNT Counter Overflow Update Event Flag Write a new value Software clearing Update the new value Figure 39. Up-counting Example Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction.
Page 227: Clock Controller
® Cortex ® -M3 MCU HT32F12345 Center-Align Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.
Page 228: Trigger Controller
® Cortex ® -M3 MCU HT32F12345 ▄ STIED: The counter prescaler can count during each rising edge of the STI signal. This mode can be se- lected by setting the SMSEL field to 0x7 in the MDCFR register, here the counter will act as an event counter.
Page 229: Figure 43. Trigger Control Block
Cortex ® -M3 MCU HT32F12345 generate a clock pulse at each trigger signal rising edge to stimulate some GPTM functions which are triggered by a trigger signal rising edge. Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux...
Page 230: Slave Controller
Cortex ® -M3 MCU HT32F12345 Slave Controller The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register.
Page 231: Figure 46. Gptm In Pause Mode
Cortex ® -M3 MCU HT32F12345 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.
Page 232: Master Controller
® Cortex ® -M3 MCU HT32F12345 Master Controller The GPTMs and MCTMs can be linked together internally for timer synchronization or chaining. When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source, selected by the MMSEL field in the MDCFR register, to trigger or drive another GPTM or MCTM which is configured in the Slave Mode.
Page 233: Figure 50. Capture / Compare Block Diagram
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 APB Bus Interface CHxCCR (Preload Register) CHxPSC Write CHxCCR Capture Compare Capture Transfer Compare Transfer Controller Controller Update Event Read CHxCCR CHxCCR (Shadow Register) CHxCCS CHxCCS Capture CHxCCG CHxPRE CHxCCR CHxE TM_CNT Figure 50.
Page 234: Figure 52. Pwm Pulse Width Measurement Example
Cortex ® -M3 MCU HT32F12345 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the GTn_ CHx pins (TIx). The following example shows how to configure the GPTMn operated in the input capture mode to measure the high pulse width and the input period on the GTn_CH0 pin using channel 0 and channel 1.
Page 235: Input Stage
Cortex ® -M3 MCU HT32F12345 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal (TI0) can be chosen to come from the GTn_CH0 signal or the Excusive-OR function of the GTn_CH0, GTn_CH1 and GTn_CH2 signals.
Page 236: Output Stage
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 TRCED CH2CCS CLKIN GTn_CH2 TI2FP Filter TI2S2 Edge TI2S2ED fsampling TI2FN Detection CH2PSC TI2F CH2PRESCALER CH2P CH2CAP Event TI3S2 Edge TI3S2ED CH2PSC Detection TI2S3 Edge TI2S3ED Detection CH3P CH3PSC TI3FP GTn_CH3 CH3PRESCALER...
Page 237: Figure 56. Toggle Mode Channel Output Reference Signal (Chxpre = 0)
Cortex ® -M3 MCU HT32F12345 Channel Output Reference Signal When the GPTM is used in the compare match output mode, the CHxOREF signal (Channel x Output Reference signal) is defined by setting the CHxOM bits. The CHxOREF signal has several types of output function.
Page 238: Figure 57. Toggle Mode Channel Output Reference Signal (Chxpre = 1)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Counter Value CHxOM=0x03, CHxPRE=1 (Output toggle, preload enable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF (Update Event) Figure 57. Toggle Mode Channel Output Reference Signal (CHxPRE = 1)
Page 239: Figure 59. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Counter Value Counter Value CHxCCR CHxCCR CHxOM = 0x06 100% CHxOREF CHxOREF CHxCCIF CHxCCIF CHxOM = 0x07 CHxOREF Figure 59. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode CRR = 5...
Page 240: Update Management
® Cortex ® -M3 MCU HT32F12345 Update Management The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event is generated when counter overflow/underflow, the software update control bit is triggered or an update event from the slave controller is generated.
Page 241: Table 32. Counting Direction And Encoding Signals
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 TRCED TI0SRC CLKIN Edge Detection GTn_CH0 TI0BED TI0XOR GTn_CH1 Edge GTn_CH2 Detection CH0CCS CLKIN TI0S0 TI0S0ED Edge TI0FP TI0FN Detection Filter fsampling CH0PSC CH0P CH0PRESCALER CH0CAP Event TI0F TI1S0ED TI1S0 Edge CH0PSC...
Page 242: Digital Filter
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Quadrature Decoder Counting on Both TI0 & TI1 Down (CH0P = 0, CH1P = 0) Figure 63. Both TI0 and TI1 Quadrature Decoder Counting Digital Filter The digital filters are embedded in the input stage and clock controller block for the GTn_CH0 ~ GTn_CH3 and GTn_ETI pins respectively.
Page 243: Clearing The Chxoref When Etif Is High
Cortex ® -M3 MCU HT32F12345 Clearing the CHxOREF when ETIF is high The CHxOREF signal can be forced to 0 when the ETIF signal is set to a high level by setting the REFxCE bit to 1 in the CHxOCFR register. The CHxOREF signal will not return to its active level until the next update event occurs.
Page 244: Single Pulse Mode
Cortex ® -M3 MCU HT32F12345 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.
Page 245: Figure 67. Immediate Active Mode Minimum Delay
Cortex ® -M3 MCU HT32F12345 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register.
Page 246: Asymmetric Pwm Mode
® Cortex ® -M3 MCU HT32F12345 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.
Page 247: Figure 69. Pausing Gptm1 Using The Gptm0 Ch0Oref Signal
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Master GPTM0 CLKIN GPTM0 CH0OREF GPTM0 CNTR Slave GPTM1 GPTM1 CNTR GPTM1 TEVIF Software clearing Figure 69. Pausing GPTM1 Using the GPTM0 CH0OREF Signal Using one timer to trigger another timer start counting ▄...
Page 248: Figure 71. Trigger Gptm0 And Gptm1 With The Gptm0 Ch0 Input
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Starting two timers synchronously in response to an external trigger ▄ Configure GPTM0 to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x01). ▄...
Page 249: Trigger Adc Start
Cortex ® -M3 MCU HT32F12345 Trigger ADC Start To interconnect with the Analog-to-digital Converter, the GPTM can output the MTO signal or the channel output GTn_CHx (x = 0 ~ 3) signal to be used as the Analog-to-Digital Converter input trigger signal.
Page 250: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map The following table shows the GPTM registers and reset values. Table 33. Register Map of GPTM Register Offset Description Reset Value GPTM0 Base Address = 0x4006_E000 GPTM1 Base Address = 0x4006_F000...
Page 251: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the GPTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...
Page 252: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions UEVDIS Update event Disable control 0: Enable the update event request by one of following events: - Counter overflow/underflow UEVG - Setting the - Update generation through the slave mode...
Page 253 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. MMSEL [2:0] Mode Descriptions...
Page 254 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the Disable mode internal clock The counter uses the clock pulse generated from the interaction between the TI0 and Quadrature TI1 signals to drive the counter prescaler.
Page 255: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Trigger Configuration Register – TRCFR This register specifies the GPTM external clock setting and the trigger source selection. Offset: 0x008 Reset value: 0x0000_0000 Reserved ECME Type/Reset Reserved ETIPOL Type/Reset Reserved ETIPSC...
Page 256: Table 34. Gptm Internal Trigger Connection
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11:8] External Trigger Filter These bits define the frequency divided ratio that is used to sample the GTn_ETI signal. The digital filter in the GPTM is an N-event counter where N means how many valid transitions are necessary to output a filtered signal.
Page 257: Timer Counter Register - Ctr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Counter Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved...
Page 258: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...
Page 259: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 260: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [17:16] CH1CCS Channel 1 Capture / Compare Selection 00: Channel 1 is configured as an output 01: Channel 1 is configured as an input derived from the TI1 signal...
Page 261 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [19:18] CH2PSC Channel 2 Capture Input Source Prescaler Setting These bits define the effective events of the channel 2 capture input. Note that the prescaler is reset once the Channel 2 Capture / Compare Enable bit, CH2E, in the Channel Control register named CHCTR is cleared to 0.
Page 262: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 3 Input Configuration Register – CH3ICFR This register specifies the channel 3 input mode configuration. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH3PSC CH3CCS Type/Reset 0 RW 0 RW 0 RW...
Page 263: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [3:0] TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divided ratio used to sample the TI3 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are nevessary to output a filtered signal.
Page 264 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH0PRE Channel 0 Capture / Compare Register (CH0CCR) Preload Enable 0: CH0CCR preload function is disabled The CH0CCR register can be immediately assigned a new value when the CH0PRE bit is cleared to 0 and the updated CH0CCR value is used immediately.
Page 265: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE REF1CE...
Page 266: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 267 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH2IMAE Channel 2 Immediate Active Enable 0: No action 1: Single pulse Immediate Active Mode is enabled The CH2OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values.
Page 268: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE REF3CE...
Page 269 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 270: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...
Page 271: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P Reserved...
Page 272: Timer Pdma/Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer PDMA/Interrupt Control Register – DICTR This register contains the timer PDMA and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE Reserved UEVDE Type/Reset Reserved CH3CCDE CH2CCDE CH1CCDE CH0CCDE...
Page 273: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH2CCIE Channel 2 Capture / Compare Interrupt Enable 0: Channel 2 interrupt is disabled 1: Channel 2 interrupt is enabled CH1CCIE Channel 1 Capture / Compare Interrupt Enable 0: Channel 1 interrupt is disabled...
Page 274 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH3CCG Channel 3 Capture / Compare Generation 0: No action 1: Capture / Compare event is generated on channel 3 A Channel 3 Capture / Compare event can be generated by setting this bit. It is cleared by hardware automatically.
Page 275: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIF Reserved UEVIF Type/Reset CH3OCF CH2OCF CH1OCF CH0OCF CH3CCIF...
Page 276 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH0OCF Channel 0 Over-Capture Flag 0: No over-capture event is detected 1: Capture event occurs again when the CH0CCIFbit is already set and it is not yet cleared by software This flag is set by hardware and cleared by software writing a ‘0’.
Page 277: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Counter Register – CNTR This register stores the timer counter value. Offset: 0x080 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CNTV Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 278: Timer Counter Reload Register - Crr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...
Page 279: Channel 1 Capture / Compare Register - Ch1Ccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 1 Capture / Compare Register – CH1CCR This register specifies the timer channel 1 Capture / Compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW...
Page 280: Channel 2 Capture / Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 2 Capture / Compare Register – CH2CCR This register specifies the timer channel 2 Capture / Compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW...
Page 281: Channel 3 Capture / Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 3 Capture / Compare Register – CH3CCR This register specifies the timer channel 3 Capture / Compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW...
Page 282: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...
Page 283: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...
Page 284: Basic Function Timer (Bftm)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Basic Function Timer (BFTM) Introduction The Basic Function Timer Module, BFTM, is a 32-bit up-counting counter designed to measure time intervals, generate one shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes.
Page 285: Functional Description
Cortex ® -M3 MCU HT32F12345 Functional Description The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations.
Page 286: One Shot Mode
Cortex ® -M3 MCU HT32F12345 One Shot Mode By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program.
Page 287: Trigger Adc Start
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Trigger ADC Start When a BFTM compare match event occurs, a compare match interrupt f lag, MIF, will be generated which can be used as an A/D Converter input trigger source. Register Map The following table shows the BFTM registers and their reset values.
Page 288: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions BFTM Control Register – BFTMCR This register specifies the overall BFTM control bits. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved MIEN Type/Reset 0 RW 0 RW...
Page 289: Bftm Status Register - Bftmsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 BFTM Status Register – BFTMSR This register specifies the BFTM status. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions BFTM Compare Match Interrupt Flag...
Page 290: Bftm Compare Value Register - Bftmcmpr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 BFTM Compare Value Register – BFTMCMPR The register specifies the BFTM compare value. Offset: 0x00C Reset value: 0xFFFF_FFFF Type/Reset 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW...
Page 291: Motor Control Timer (Mctm)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Motor Control Timer (MCTM) Introduction The Motor Control Timer consists of one 16-bit up/down-counter, four 16-bit Capture / Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR), one 8-bit Repetition Counter (REPR) and several control / status registers. It can be used for a variety of purposes which include general time measurement, input signal pulse width measurement, output waveform generation for signals such as single pulse generation or PWM generation, including dead time insertion.
Page 292: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ 16-bit up/down auto-reload counter ▄ 16-bit programmable prescaler that allows division the counter clock frequency by any factor between 1 and 65536 ▄ Up to 4 independent channels for: ●...
Page 293: Functional Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Functional Descriptions Counter Mode Up-Counting In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0.
Page 294: Figure 79. Down-Counting Example
® Cortex ® -M3 MCU HT32F12345 Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value.
Page 295: Figure 80. Center-Aligned Counting Example
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 CK_PSC CNT_EN CK_CNT CNTR CRR Shadow Register Counter Overflow Counter Underflow Update Event 1 Flag Software clearing Write a new value Software clearing Figure 80. Center-aligned Counting Example Repetition Down-counter Operation The update event 1 is usually generated at each overflow or underflow event occurrence. However, when the repetition operation is active by assigning a non-zero value into the REPR register, the update event is only generated if the REPR counter has reached zero.
Page 296: Clock Controller
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Clock Controller The following describes the Timer Module clock controller which determines the internal prescaler counter clock source. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...
Page 297: Trigger Controller
Cortex ® -M3 MCU HT32F12345 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level and edge trigger conditions. The active polarity of the external trigger input signal MTn_ETI can be configured by the External Trigger Polarity control bit, ETIPOL, in the MCTM Trigger Configuration Register TRCFR.
Page 298: Slave Controller
Cortex ® -M3 MCU HT32F12345 Slave Controller The MCTM can be synchronised with an internal / external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which are selected by the SMSEL field in the MDCFR register.
Page 299: Figure 86. Mctm In Pause Mode
Cortex ® -M3 MCU HT32F12345 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start / stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level.
Page 300: Master Controller
® Cortex ® -M3 MCU HT32F12345 Master Controller The MCTMs and GPTMs can be linked together internally for timer synchronisation or chaining. When one MCTM is configured to be in the Master Mode, the MCTM Master Controller will generate a Master Trigger Output (MTO) signal which can reset, start, stop the Slave counter or be a clock source of the Slave Counter.
Page 301: Channel Controller
® Cortex ® -M3 MCU HT32F12345 Channel Controller The MCTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented through the read/write preload register.
Page 302: Figure 92. Pwm Pulse Width Measurement Example
Cortex ® -M3 MCU HT32F12345 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the MTn_ CHx pins, TIx. The following example shows how to configure the MCTM when operated in the input capture mode to measure the high pulse width and the input period on the MTn_CH0 pin using channel 0 and channel 1.
Page 303: Input Stage
Cortex ® -M3 MCU HT32F12345 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal, TI0, can be chosen to come from the MTn_CH0 signal or the Excusive-OR function of the MTn_CH0, MTn_CH1 and MTn_CH2 signals.
Page 304: Output Stage
Cortex ® -M3 MCU HT32F12345 Output Stage The MCTM supports complementary outputs for channels 0, 1 and 2 with dead time insertion. The MCTM channel 3 output function is almost the same as that of GPTM channel 3 except for the break function.
Page 305: Table 36. Compare Match Output Setup
Cortex ® -M3 MCU HT32F12345 Channel Output Reference Signal When the MCTM is used in the compare match output mode, the CHxOREF signal (Channel x Output Reference signal) is defined by the CHxOM bit setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register.
Page 306: Figure 97. Toggle Mode Channel Output Reference Signal - Chxpre = 1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Counter Value CHxOM=0x03, CHxPRE=1 (Output toggle, preload enable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF UEV1 (Update Event 1) Figure 97. Toggle Mode Channel Output Reference Signal – CHxPRE = 1...
Page 307: Figure 99. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Counter Value Counter Value CHxCCR CHxCCR CHxOM = 0x06 100% CHxOREF CHxOREF CHxCCIF CHxCCIF CHxOM = 0x07 CHxOREF CHxOREF Figure 99. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode...
Page 308: Figure 101. Dead-Time Insertion Performed For Complementary Outputs
Cortex ® -M3 MCU HT32F12345 Dead Time Generator An an 8-bit dead time generator function is included for channels 0 ~ 2. The dead time insertion is enabled by setting both the CHxE and CHxNE bits. The relationship between the CHxO and CHxNO signals with respect to the CHxOREF signal is as follows: ▄...
Page 309: Figure 102. Mctm Break Signal Bolck Diagram
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 BKP0 BKF0 BKE0 BRKG BRK0IF CKFAIL Delay MTn_BRK0 Line Filter Break Event sample (BEV) BK1SEL BKF1 BKE1 BKP1 CMPx Break Interrupt Delay MTn_BRK1 MTn_ETI (NVIC) Line Filter BRK1IF sample BRKIE Figure 102. MCTM Break Signal Bolck Diagram...
Page 310: Figure 104. Channel 3 Output With A Break Event Occurrence
Cortex ® -M3 MCU HT32F12345 When using the break function, the channel output enable signals and output levels are changed depending on several control bits which include the CHMOE, CHOSSI, CHOSSR, CHxOIS and CHxOISN bits. Once a break event occurs, the output enable bit CHMOE will be cleared asynchronously.
Page 311: Figure 105. Channel 0 ~ 2 Complementary Outputs With A Break Event Occurrence
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Break event CHMOE CHxOREF CHxP = 0, CHxOIS =0 CHxO Dead-time CHxNP = 0, CHxOISN =1 CHxNO Dead-time Dead-time CHxP = 0, CHxOIS =1 CHxO Dead-time Dead-time CHxNP = 1, CHxOISN=1 CHxNO Dead-time Figure 105.
Page 312: Figure 107. Hardware Protection When Both Chxo And Chxno Are In Active Condition
Cortex ® -M3 MCU HT32F12345 The CHxO and CHxNO complementary outputs should not be set to an active level at the same time. The hardware will protect the MCTM circuitry to force only one channel output to be in the active state.
Page 313: Update Management
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 37. Output Control Bits for Complementary Output with a Break Event Occurrence Control bit Output status CHMOE CHOSSI CHOSSR CHxE CHxNE MT_CHx Pin output state MT_CHxN Pin output state Output disabled - floating...
Page 314: Figure 108. Update Event 1 Setup Diagram
® Cortex ® -M3 MCU HT32F12345 Update Event 1 The UEV1DIS bit in the CNTCFR register can determine whether an update event 1 occurs or not. When the update event 1 occurs, the corresponding update event interrupt will be generated depending upon whether the update event 1 interrupt generation function is enabled or not by configuring the UGDIS bit in the CNTCFR register.
Page 315: Quadrature Decoder
® -M3 MCU HT32F12345 An update event 2 can be generated by setting the software update bit, UEV2G, in the EVGR register or by the rising edge of the STI signal if the COMUS bit is set in the CTR register.
Page 316: Table 38. Counting Direction And Encoding Signals
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 38. Counting Direction and Encoding Signals TI0S0 TI1S1 Counting mode Level Rising Falling Rising Falling TI1S1 = High Down — — Counting on TI0 only (SMSEL = 0x01) TI1S1 = Low Down —...
Page 317: Digital Filter
Cortex ® -M3 MCU HT32F12345 Digital Filter The digital filters are embedded in the input stage and clock controller block for the MTn_CH0 ~ MTn_CH3 and MTn_ETI pins. The digital filter in the MCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal.
Page 318: Single Pulse Mode
Cortex ® -M3 MCU HT32F12345 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.
Page 319: Figure 116. Immediate Active Mode Minimum Delay
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Counter Value ETIPSC = 0 Up-Counting Mode ETF = 0 CKDIV = 0 CHxCCR Time CLKIN MTn_ETI Counter Start Time CHxIMAE CHxOREF (PWM1) Minimum delay (PWM2) Figure 116. Immediate Active Mode Minimum Delay Rev.
Page 320: Asymmetric Pwm Mode
® Cortex ® -M3 MCU HT32F12345 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be genetated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.
Page 321: Figure 118. Pausing Gptm0 Using The Mctm0 Ch0Oref Signal
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Master MCTM0 CLKIN MCTM0 CH0OREF MCTM0 CNTR Slave GPTM0 GPTM0 CNTR GPTM0 TEVIF Software clearing Figure 118. Pausing GPTM0 Using the MCTM0 CH0OREF Signal Using one timer to trigger another timer to start counting ▄...
Page 322: Figure 120. Trigger Mctm0 And Gptm0 With The Mctm0 Ch0 Input
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Starting two timers synchronously in response to an external trigger ▄ Configure MCTM0 to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x01). ▄...
Page 323: Figure 121. Ch1Xor Input As Hall Sensor Interface
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Using one timer as a hall sensor interface to trigger another timer with update event 2 ▄ GPTM0: ● Configure channel 0 to choose an input XOR function (TI0SRC = 1) ●...
Page 324: Trigger Adc Start
Cortex ® -M3 MCU HT32F12345 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the MCTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal.
Page 325: Pdma Request
® Cortex ® -M3 MCU HT32F12345 PDMA Request The MCTM has a PDMA data transfer interface. There are certain events which can generate PDMA requests if the corresponding enable control bits are set to 1 to enable the PDMA access.
Page 326: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map The following table shows the MCTM registers and reset values. Table 40. MCTM Register Map Register Offset Description Reset Value MCTM0 Base Address = 0x4002_C000 MCTM1 Base Address = 0x4002_D000...
Page 327: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the MCTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...
Page 328: Timer Mode Configuration Register - Mdcfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions UGDIS Update event 1 interrupt generation disable control 0: Any of the following events will generate an update PDMA request or interrupt - Counter overflow / underflow - Setting the UEV1G bit...
Page 329 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronise the other slave timer. MMSEL [2:0] Mode Descriptions...
Page 330 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the Disable mode internal clock The counter uses the clock pulses generated from the interaction between the TI0 and Quadrature TI1 signals to drive the counter prescaler.
Page 331: Timer Trigger Configuration Register - Trcfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Trigger Configuration Register – TRCFR This register specifies the MCTM external clock setting and the trigger source selection. Offset: 0x008 Reset value: 0x0000_0000 Reserved ECME Type/Reset Reserved ETIPOL Type/Reset Reserved ETIPSC...
Page 332: Table 41. Mctm Internal Trigger Connection
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11:8] External Trigger Filter These bits define the frequency divided ratio that is used to sample the MTn_ETI signal. The digital filter in the MCTM is an N-event counter where N means how many valid transitions are necessary to output a filtered signal.
Page 333: Timer Counter Register - Ctr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Counter Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE), Capture / Compare control bit and Channel PDMA selection bit (CHCCDS). Offset: 0x010 Reset value: 0x0000_0000...
Page 334: Channel 0 Input Configuration Register - Ch0Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...
Page 335: Channel 1 Input Configuration Register - Ch1Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 336: Channel 2 Input Configuration Register - Ch2Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [17:16] CH1CCS Channel 1 Capture / Compare Selection 00: Channel 1 is configured as an output 01: Channel 1 is configured as an input derived from the TI1 signal...
Page 337 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [19:18] CH2PSC Channel 2 Capture Input Source Prescaler Setting These bits define the effective events of the channel 2 capture input. Note that the prescaler is reset once the Channel 2 Capture / Compare Enable bit, CH2E, in the Channel Control register named CHCTR is cleared to 0.
Page 338: Channel 3 Input Configuration Register - Ch3Icfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 3 Input Configuration Register – CH3ICFR This register specifies the channel 3 input mode configuration. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH3PSC CH3CCS Type/Reset 0 RW 0 RW 0 RW...
Page 339: Channel 0 Output Configuration Register - Ch0Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [3:0] TI3F Channel 3 Input Source TI3 Filter Setting These bits define the frequency divide ratio used to sample the TI3 signal. The digital filter in the GPTM is an N-event counter where N is defined as how many...
Page 340 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH0PRE Channel 0 Capture / Compare Register (CH0CCR) Preload Enable 0: CH0CCR preload function is disabled The CH0CCR register can be immediately assigned a new value when the CH0PRE bit is cleared to 0 and the updated CH0CCR value is used immediately.
Page 341: Channel 1 Output Configuration Register - Ch1Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE REF1CE...
Page 342: Channel 2 Output Configuration Register - Ch2Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 343 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH2IMAE Channel 2 Immediate Active Enable 0: No action 1: Single pulse Immediate Active Mode enabled The CH2OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values.
Page 344: Channel 3 Output Configuration Register - Ch3Ocfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE REF3CE...
Page 345: Channel Control Register - Chctr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...
Page 346 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH3E Channel 3 Capture / Compare Enable - Channel 3 is configured as an input (CH3CCS = 0x01 / 0x02 / 0x03) 0: Input Capture Mode disabled 1: Input Capture Mode enabled - Channel 3 is configured as an output (CH3CCS = 0x00) 0: Off –...
Page 347: Channel Polarity Configuration Register - Chpolr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH0E Channel 0 Capture / Compare Enable - Channel 0 is configured as an input (CH0CCS = 0x01 / 0x02 / 0x03) 0: Input Capture Mode disabled 1: Input Capture Mode enabled - Channel 0 is configured as an output (CH0CCS = 0x00) 0: Off –...
Page 348: Channel Break Configuration Register - Chbrkcfr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH1NP Channel 1 Capture / Compare Complementary Polarity 0: Channel 1 Output is active high 1: Channel 1 Output is active low CH1P Channel 1 Capture / Compare Polarity (CH1CCS = 0x01 / 0x02 / 0x03)
Page 349: Channel Break Control Register - Chbrkctr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH2OIS MTn_CH2O Output Idle State 0: Channel 2 output CH2O = 0 after a dead time when CHMOE = 0 1: Channel 2 output CH2O = 1 after a dead time when CHMOE = 0...
Page 350 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [20] CHOSSI Channel Off State Selection for Idle Mode (CHMOE = 0) 0: When inactive, MTn_CHxO / MTn_CHxNO output disable – not driven by timer 1: When inactive, MTn_CHxO / MTn_CHxNO output enabled with their idle level depending upon the condition of the the CHxOIS and CHxOISN bits.
Page 351 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11:8] BKF0 Break 0 Input Filter Setting These bits define the frequency ratio used to sample the MTn_BRK0 signal. The digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
Page 352: Timer Pdma / Interrupt Control Register - Dictr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer PDMA / Interrupt Control Register – DICTR This register contains the timer PDAM and interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved TEVDE UEV2DE UEV1DE Type/Reset 0 RW 0 RW...
Page 353: Timer Event Generator Register - Evgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions UEV2IE Update event 2 Interrupt Enable 0: Update event 2 interrupt is disabled 1: Update event 2 interrupt is enabled UEV1IE Update event 1 Interrupt Enable 0: Update event 1 interrupt is disabled...
Page 354 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions UEV2G Update Event 2 Generation The update event 2 UEV2 can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Update the CHxE, CHxNE and CHxOM bits when COMPRE bit in CTR...
Page 355: Timer Interrupt Status Register - Intsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRK1IF BRK0IF TEVIF UEV2IF UEV1IF Type/Reset 0 W0C 0 W0C...
Page 356 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH2OCF Channel 2 Over-capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH2CCIF bit is already set and it is not...
Page 357: Timer Counter Register - Cntr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions CH0CCIF Channel 0 Capture / Compare Interrupt Flag - Channel 0 is configured as an output 0: No match event occurs 1: The contents of the counter CNTR have matched the content of the CH0CCR...
Page 358: Timer Prescaler Register - Pscr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...
Page 359: Timer Repetition Register - Repr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timer Repetition Register – REPR This register specifies the timer repetition counter value. Offset: 0x08C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset REPV Type/Reset 0 RW 0 RW 0 RW...
Page 360: Channel 1 Capture / Compare Register - Ch1Ccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 1 Capture / Compare Register – CH1CCR This register specifies the timer channel 1 capture / compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW...
Page 361: Channel 2 Capture / Compare Register - Ch2Ccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 2 Capture / Compare Register – CH2CCR This register specifies the timer channel 2 capture / compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW...
Page 362: Channel 3 Capture / Compare Register - Ch3Ccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 3 Capture / Compare Register – CH3CCR This register specifies the timer channel 3 capture / compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW...
Page 363: Channel 0 Asymmetric Compare Register - Ch0Acr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...
Page 364: Channel 2 Asymmetric Compare Register - Ch2Acr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...
Page 365: Real Time Clock (Rtc)
® Cortex ® -M3 MCU HT32F12345 Real Time Clock (RTC) Introduction The Real Time Clock, RTC, circuitry includes the APB interface, a 32-bit up-counter, a control register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in the Backup Domain, as shown shaded in the accompanying figure, except for the APB interface.
Page 366: Functional Descriptions
® Cortex ® -M3 MCU HT32F12345 Functional Descriptions RTC Related Register Reset The RTC registers can only be reset by either a Backup Domain power on reset, PORB, or by a Backup Domain software reset by setting the BAKRST bit in the BAKCR register. Other reset events have no effect to clear the RTC registers.
Page 367: Interrupt And Wakeup Control
® -M3 MCU HT32F12345 is set to a decimal value of 60 and the CMPCLR bit is set to 1, then the CMFLAG bit will be set every minute. In addition, the OVFLAG bit in the RTCSR register will be set when the RTC counter overflows.
Page 368: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ROWM ROES RTCOUT Output Waveform RTCCMP RTCCNT Compare RTCOUT (ROAP = 0) match RTCOUT (ROAP = 1) ROLF → (Level mode) RTCCMP RTCCNT RTCOUT (ROAP = 0) Second clock RTCOUT (ROAP = 1) ROLF →...
Page 369: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions RTC Counter Register – RTCCNT This register defines a 32-bit up counter which is incremented by the CK_SECOND clock. Offset: 0x000 Reset value: 0x0000_0000 RTCCNTV Type/Reset 0 RO 0 RO...
Page 370: Rtc Compare Register - Rtccmp
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 RTC Compare Register – RTCCMP This register defines a specific value to be compared with the RTC counter value. Offset: 0x004 Reset value: 0x0000_0000 (Reset by Backup Domain reset only) RTCCMPV Type/Reset...
Page 371: Rtc Control Register - Rtccr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 RTC Control Register – RTCCR This register specifies a range of RTC circuitry control bits. Address: 0x008 Reset value: 0x0000_0F04 (Reset by Backup Domain reset only) Reserved Type/Reset Reserved ROLF ROAP ROWM...
Page 372 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11:8] RPRE RTC Clock Prescaler Select CK_SECOND = CK_RTC / 2 RPRE 0000: CK_SECOND = CK_RTC / 2 0001: CK_SECOND = CK_RTC / 2 0010: CK_SECOND = CK_RTC / 2 …...
Page 373: Rtc Status Register - Rtcsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 RTC Status Register – RTCSR This register stores the counter flags. Offset: 0x00C Reset value: 0x0000_0000 (Reset by Backup Domain reset and RTCEN bit change from 1 to 0) Reserved Type/Reset Reserved...
Page 374: Rtc Interrupt And Wakeup Enable Register - Rtciwen
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 RTC Interrupt and Wakeup Enable Register – RTCIWEN This register contains the interrupt and wakeup enable bits. Offset: 0x010 Reset value: 0x0000_0000 (Reset by Backup Domain reset only) Reserved Type/Reset Reserved Type/Reset...
Page 375: Watchdog Timer (Wdt)
® Cortex ® -M3 MCU HT32F12345 Watchdog Timer (WDT) Introduction The Watchdog timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog timer can be operated in a reset mode. The Watchdog timer will generate a reset when the counter counts down to a zero value.
Page 376: Functional Description
Cortex ® -M3 MCU HT32F12345 Functional Description The Watchdog timer is formed from a 12-bit count-down and a fixed 3-bit prescaler. The largest time-out period is 16 seconds, using the LSE or LSI clock and a 1/128 maximum prescaler value.
Page 377: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Reset occurred (If WDTRSTEN = 1) C ounter value 0xFFF Reset not occurred (If WDTRSTEN = 0) WDTV Reload is not allowed WDTD . . . Reload is allowed Time Reload counter when Reload counter when counter >...
Page 378: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions Watchdog Timer Control Register – WDTCR This register is used to reload the Watchdog timer. Offset: 0x000 Reset value: 0x0000_0000 RSKEY Type/Reset 0 WO 0 WO 0 WO 0 WO...
Page 379: Watchdog Timer Mode Register 0 - Wdtmr0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Watchdog Timer Mode Register 0 – WDTMR0 This register specifies the Watchdog timer counter reload value and reset enable control. Offset: 0x004 Reset value: 0x0000_0FFF Reserved Type/Reset Reserved WDTEN Type/Reset WDTSHLT WDTRSTEN Reserved...
Page 380: Watchdog Timer Mode Register 1 - Wdtmr1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Watchdog Timer Mode Register 1 – WDTMR1 This register specifies the Watchdog delta value and the prescaler selection. Offset: 0x008 Reset value: 0x0000_7FFF Reserved Type/Reset Reserved Type/Reset Reserved WPSC WDTD Type/Reset 1 RW...
Page 381: Watchdog Timer Status Register - Wdtsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Watchdog Timer Status Register – WDTSR This register specifies the Watchdog timer status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTERR WDTUF Type/Reset 0 WC Bits Field...
Page 382: Watchdog Timer Protection Register - Wdtpr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Watchdog Timer Protection Register – WDTPR This register specifies the Watchdog timer protect key configuration. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PROTECT Type/Reset 0 RW 0 RW 0 RW...
Page 383: Watchdog Timer Clock Selection Register - Wdtcsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Watchdog Timer Clock Selection Register – WDTCSR This register specifies the Watchdog timer clock source selection and lock configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTLOCK...
Page 384: Inter-Integrated Circuit
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Inter-Integrated Circuit (I Introduction The I C Module is an internal circuit allowing communication with an external I C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL.
Page 385: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ Two wire I C serial interface ● Serial data line (SDA) and serial clock (SCL) ▄ Multiple speed modes ● Standard mode – 100 kHz ● Fast mode – 400 kHz ●...
Page 386: Data Validity
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 STOP Condition START Condition Figure 127. START and STOP Condition Data Validity The data on the SDA line must be stable during the high period of the SCL clock. The SDA data state can only be changed when the clock signal on the SCL line is in a low state.
Page 387: 10-Bits Address Format
® Cortex ® -M3 MCU HT32F12345 The slave address can be assigned through the ADDR field in the I2CADDR register. The slave device sends back the acknowledge bit (ACK) if its slave address matches the transmitted address sent by master.
Page 388: Data Transfer And Acknowledge
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Ack A7 Data S = START condition Sr = Repeated-START condition W = Write command R = Read command Ack = Acknowledge A9 ~ A0 = 10-bits Address Figure 131. 10-bits Addressing Read Receive Mode...
Page 389: Clock Synchronization
® Cortex ® -M3 MCU HT32F12345 Clock Synchronization Only one master device can generate the SCL clock under normal operation. However when there is more than one master trying to generate the SCL clock, the clock should be synchronized so that the data output can be compared.
Page 390: General Call Address
Cortex ® -M3 MCU HT32F12345 General Call Address The general call addressing function can be used to address all the devices connected to the I bus. The master device can activate the general call function by writing a value “00” into the TAR and setting the RWD bit to 0 in the I2CTAR register on the addressing frame.
Page 391: Figure 135. Master Transmitter Timing Diagram
® Cortex ® -M3 MCU HT32F12345 Master Transmitter Mode Start condition Users write the target slave device address and communication direction into the I2CTAR register after setting the I2CEN bit in the I2CCR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs.
Page 392 ® Cortex ® -M3 MCU HT32F12345 Master Receiver Mode Start condition The target slave device address and communication direction must be written into the I2CTAR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs. In order to send the following address frame, the STA flag must be cleared to 0 if it has been set to 1.The...
Page 393: Figure 136. Master Receiver Timing Diagram
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 7-bits Master Receiver Address Data1 Data2 DataN ADRS RXDNE RXDNE RXDNE RXDNE BEH1 BEH1 BEH2 BEH2 BEH3 BEH4 10-bits Master Receiver Header Address ADRS #1 BEH1 BEH1 Header Data1 Data2 DataN RXDNE...
Page 394: Figure 137. Slave Transmitter Timing Diagram
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 7-bits Slave Transmitter Address Data1 Data2 DataN TXDE TXDE TXDE ADRS RXNACK BEH1 BEH2 BEH2 BEH2 BEH3 BEH4 10-bits Slave Transmitter Header Address ADRS #1 BEH1 Header Data1 Data2 DataN TXDE TXDE...
Page 395: Conditions Of Holding Scl Line
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 7-bits Slave Receiver Address Data1 Data2 DataN ADRS RXDNE RXDNE RXDNE BEH1 BEH2 BEH2 BEH3 BEH2 10-bits Slave Receiver Header Address Data1 Data2 DataN ADRS RXDNE RXDNE RXDNE BEH1 BEH2 BEH2 BEH2...
Page 396: I 2 C Timeout Function
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 C Timeout Function In order to reduce the occurrence of I C lockup problem due to the reception of erroneous clock source, a timeout function is provided. If the I C bus clock source is not received for a certain timeout period, then a corresponding I C timeout flag will be asserted.
Page 397: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Map The following table shows the I C registers and reset values. Table 47. I C Register Map Register Offset Description Reset Value I2C0 Base Address = 0x4004_8000 I2C1 Base Address = 0x4004_9000...
Page 398: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions C Control Register – I2CCR This register specifies the corresponding I C function enable control. Offset: 0x000 (0) Reset value: 0x0000_2000 Reserved Type/Reset Reserved Type/Reset SEQFILTER COMBFILTEREN ENTOUT Reserved DMANACK...
Page 399 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions RXDMAE DMA Mode RX Request Enable Control 0: RX DMA request disabled 1: RX DMA request enabled If the data register is not empty in the receiver mode and the RXDMAE bit is set to 1, the relevant PDMA channel will be activated to move the data from the data register to a specific location which is defined in the corresponding PDMA register.
Page 400: I 2 C Interrupt Enable Register - I2Cier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 C Interrupt Enable Register – I2CIER This register specifies the corresponding I C interrupt enable bits. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved RXBFIE TXDEIE RXDNEIE Type/Reset 0 RW 0 RW...
Page 401 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions ARBLOSIE Arbitration Loss Interrupt Enable Bit in the I2C multi-master mode 0: Interrupt disabled 1: Interrupt enabled When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by hardware.
Page 402: I 2 C Address Register - I2Caddr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 C Address Register – I2CADDR This register specifies the I C device address. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ADDR Type/Reset 0 RW ADDR Type/Reset 0 RW 0 RW...
Page 403 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [21] TXNRX Transmitter / Receiver Mode 0: Receiver mode 1: Transmitter mode Read only bit. [20] MASTER Master Mode 0: I C is in the slave mode or idle...
Page 404 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [10] BUSERR Bus Error Flag 0: No bus error has occurs 1: Bus error has occurred This bit is set by hardware when the I C interface detects a misplaced START or STOP condition in a transfer process.
Page 405: I 2 C Scl High Period Generation Register - I2Cshpgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions START Condition Transmit 0: No START condition detected 1: START condition is transmitted in master mode This bit is only available for the master mode and is cleared automatically after the I2CSR register is read.
Page 406: I 2 C Scl Low Period Generation Register - I2Cslpgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 C SCL Low Period Generation Register – I2CSLPGR This register specifies the I C SCL clock low period interval. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SLPG Type/Reset 0 RW...
Page 407: I 2 C Data Register - I2Cdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 48. I C Clock Setting Example × [ (SHPG + d) + (SLPG + d) ] (where d = 6) PCLK SHPG + SLPG value at PCLK C Clock 8 MHz...
Page 408: I 2 C Target Register - I2Ctar
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 C Target Register – I2CTAR This register specifies the target device address to be communicated. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW Type/Reset 0 RW...
Page 409: I 2 C Address Mask Register - I2Caddmr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 C Address Mask Register – I2CADDMR This register specifies which bit of the I C address is masked and not compared with corresponding bit of the received address frame. Offset: 0x020 Reset value: 0x0000_0000...
Page 410: I 2 C Timeout Register - I2Ctout
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [9:0] ADDSR Address Snoop Once the I2CEN bit is enabled, the calling address value on the I C bus will automatically be loaded into this ADDSR field. C Timeout Register – I2CTOUT This register specifies the I C Timeout counter preload value and clock prescaler ratio.
Page 411: Serial Peripheral Interface (Spi)
® Cortex ® -M3 MCU HT32F12345 Serial Peripheral Interface (SPI) Introduction The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are serial data input and output lines MISO and MOSI, the clock line SCK, and the slave select line SEL.
Page 412: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ Master or slave mode ▄ Master mode speed up to f PCLK ▄ Slave mode speed up to f PCLK ▄ Programmable data frame length up to 16 bits ▄...
Page 413: Spi Serial Frame Format
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 SPI Serial Frame Format The SPI interface format is base on the Clock Polarity, CPOL, and the Clock Phase, CPHA, configurations. ▄ Clock Polarity Bit – CPOL When the Clock Polarity bit is cleared to 0, the SCK line idle state is LOW. When the Clock Polarity bit is set to 1, the SCK line idle state is HIGH.
Page 414: Figure 142. Spi Continuous Data Transfer Timing Diagram - Cpol = 0, Cpha = 0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 142 shows the continuous data transfer timing diagram of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO...
Page 415: Figure 144. Spi Continuous Transfer Timing Diagram - Cpol = 0, Cpha = 1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 144 shows the continuous data transfer diagram timing. Note that the SEL signal must remain active until the last data transfer has completed. SEL (SELAP=0) SEL (SELAP=1) ½ SCK ½ SCK...
Page 416: Figure 146. Spi Continuous Transfer Timing Diagram - Cpol = 1, Cpha = 0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 146 shows the continuous data transfer timing of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) ½ SCK ½...
Page 417: Status Flags
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Figure 148 shows the continuous data transfer timing of this format. Note that the SEL signal must remain active until the last data transfer has completed. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO Data1 Data2 Figure 148.
Page 418: Table 50. Spi Mode Fault Trigger Conditions
Cortex ® -M3 MCU HT32F12345 Mode Fault – MF The mode fault flag can be used to detect SPI bus usage in the SPI multi-master mode. For the multi-master mode, the SPI module is configured as a master device and the SEL signal is setup as an input signal.
Page 419: Table 51. Spi Master Mode Sel Pin Status
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 51. SPI Master Mode SEL Pin Status SEL as Input – SELOEN = 0 SEL as Output – SELOEN = 1 Multi-master Support Not support Use another GPIO to replace the...
Page 420: Register Map
® -M3 MCU HT32F12345 Similarly, when the receive buffer not empty flag, RXBNE, is asserted and the RXDMAE bit is set to 1, the PDMA function will be activated to move data from the SPI data register or the RX FIFO to the memory location that users designated until the RXBNE flag is cleared to 0.
Page 421: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions SPI Control Register 0 – SPICR0 This register specifies the SEL control and the SPI enable bits. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SELHT GUADT Type/Reset 0 RW...
Page 422: Spi Control Register 1 - Spicr1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions SSELC Software Slave Select Control 0: Set the SEL output to an inactive state 1: Set the SEL output to an active state The application Software can setup the SEL output to an active or inactive state by configuring the SSELC bit.
Page 423 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [14] MODE Master or Slave Mode 0: Slave mode 1: Master mode [13] SELM Slave Select Mode 0: SEL signal is controlled by software – asserted or de-asserted by the SSELC 1: SEL signal is controlled by hardware –...
Page 424: Spi Interrupt Enable Register - Spiier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 SPI Interrupt Enable Register – SPIIER This register contains the corresponding SPI interrupt enable control bit. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset TOIEN SAIEN MFIEN ROIEN WCIEN...
Page 425: Spi Clock Prescaler Register - Spicpr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions TXBEIEN TX Buffer Empty Interrupt Enable 0: Disable 1: Enable The TX buffer empty interrupt request will be generated when the TXBE flag and the TXBEIEN bit are set. In the FIFO mode, the interrupt request being generated depends upon the TX FIFO trigger level setting.
Page 426: Spi Data Register - Spidr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 SPI Data Register – SPIDR This register stores the SPI received or transmitted Data. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 427 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions BUSY SPI Busy flag 0: SPI not busy 1: SPI busy In the master mode, this flag is reset when the TX buffer and TX shift register are both empty and is set when the TX buffer or the TX shift register are not empty.
Page 428: Spi Fifo Control Register - Spifcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 SPI FIFO Control Register – SPIFCR This register contains the related SPI FIFO control including the FIFO enable control and the FIFO trigger level selections. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset...
Page 429: Spi Fifo Status Register - Spifsr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 SPI FIFO Status Register – SPIFSR This register contains the relevant SPI FIFO status. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset RXFS TXFS Type/Reset 0 RO 0 RO...
Page 430: Spi Fifo Time Out Counter Register - Spiftocr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 SPI FIFO Time Out Counter Register – SPIFTOCR This register stores the SPI RX FIFO time out counter value. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW...
Page 431: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Universal Synchronous Asynchronous Receiver Transmitter (USART) Introduction The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.
Page 432: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ Supports both asynchronous and clocked synchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate clock frequency up to (f / 16) MHz for asynchronous mode and (f...
Page 433: Baud Rate Generation
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 7-Bit Data Format (WLS[1:0]=0x00,PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Stop Bit 8-Bit Data Format (WLS[1:0]=0x01,PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6...
Page 434: Hardware Flow Control
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 53. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz Baud rate CK_USART = 48 MHz Kbps Actual Deviation Error rate 20000 0.00% 5000 0.00% 19.2 19.2 2500 0.00% 57.6 57.6...
Page 435: Figure 154. Usart Rts Flow Control
Cortex ® -M3 MCU HT32F12345 RTS Flow Control In the RTS flow control, the USART RTS pin is active with a logic low state when the receive data register is empty. It means that the receiver is ready to receive a new data. When the RX FIFO reaches the trigger level which is specified by configuring the RXTL field in the USRFCR register, the USART RTS pin is inactive with a logic high state.
Page 436: Irda
® Cortex ® -M3 MCU HT32F12345 IrDA The USART IrDA mode is provided half-duplex point-to-point wireless communication. The USART module includes an integrated modulator and demodulator which allow a wireless communication using infrared transceivers. The transmitter specifies a logic data ‘0’ as a ‘high’...
Page 437: Figure 157. Usart I/O And Irda Block Diagram
Cortex ® -M3 MCU HT32F12345 IrDA receiver demodulation operation can function properly. The IrDAPSC value can be adjusted to meet the USART baud rate setting to filter the IrDA received glitch noise of which the width is smaller than the prescaler setting duration.
Page 438: Rs485 Mode
® Cortex ® -M3 MCU HT32F12345 RS485 Mode The RS485 mode of USART provides the data on interface is transmitted over a 2-wire twisted pair bus. The RS485 transceiver interprets the voltage levels of the differential signals with respect to a third common voltage. Without this common reference, the transceiver may interpret the differential signals incorrectly.
Page 439: Synchronous Master Mode
Cortex ® -M3 MCU HT32F12345 RS485 Normal Multi-drop Operation Mode – NMM When the RS485 mode is configured as an addressable slave, it will operate in the Normal Multi- drop Operation Mode, NMM. This mode is enabled when the RSNMM field is set in the RS485CR register.
Page 440: Figure 160. 8-Bit Format Usart Synchronous Waveform
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Note: The USART supports the synchronous master mode only: it cannot receive or send data related to an input clock. The USART CTS/SCK clock is always an output. (CPS=1,WLS[1:0]=0x01,PBE=0) Clock (CPO=0) Clock (CPO=1)
Page 441: Interrupts And Status
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Interrupts and Status The USART can generate interrupts when the following event occurs and corresponding interrupt enable bits are set: ▄ Receive FIFO time-out interrupt: An interrupt will be generated when the USART receive FIFO does not receive a new data package during the specified time-out interval.
Page 442: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions USART Data Register – USRDR The register is used to access the USART transmitted and received FIFO data. Offset : 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...
Page 443: Usart Control Register - Usrcr
Cortex ® -M3 MCU HT32F12345 USART Control Register – USRCR The register specifies the serial parameters such as data length, parity, and stop bit for the USART. It also contains the USART enable control bits together with the USART mode and data transfer mode selections.
Page 444: Usart Fifo Control Register - Usrfcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [10] Number of “STOP bit” 0: One “ STOP bit” is generated in the transmitted data 1: Two “STOP bit” is generated when 8-bit and 9-bit word length is selected...
Page 445 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [27:24] RXFS RX FIFO Status The RXFS field shows the current number of data contained in the RX FIFO. 0000: RX FIFO is empty 0001: RX FIFO contains 1 data...
Page 446: Usart Interrupt Enable Register - Usrier
Cortex ® -M3 MCU HT32F12345 USART Interrupt Enable Register – USRIER This register is used to enable the related USART interrupt function. The USART module generates interrupts to the controller when the corresponding events occur and the corresponding interrupt enable bits are set.
Page 447: Usart Status & Interrupt Flag Register - Usrsifr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions PEIE Parity Error Interrupt Enable 0: Disable interrupt 1: Enable interrupt If this bit is set to 1, an interrupt is generated when the PEI bit is set in the USRSIFR register.
Page 448 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11] CTSS CTS Clear-To-Send Status 0: CTS pin is inactive 1: CTS pin is active and kept at a logic low state [10] CTSC CTS Status Change Flag This bit is set whenever the CTS input pin status has been changed and an Interrupt is generated if the CTSIE = 1 in the USRIER register.
Page 449: Usart Timing Parameter Register - Usrtpr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions Overrun Error Indicator An overrun error will occur only after the RX FIFO is full and when the next character has been completely received in the RX shift register. The character in the shift register will be overwritten, if a new character is received in the RX shift register after an overrun event occurs, but the data in the RX FIFO will not be overwritten.
Page 450: Usart Irda Control Register - Irdacr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USART IrDA Control Register – IrDACR This register is used to control the IrDA mode of USART. Offset : 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset IrDAPSC Type/Reset 0 RW 0 RW...
Page 451: Usart Rs485 Control Register - Rs485Cr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USART RS485 Control Register – RS485CR This register is used to control the RS485 mode of USART. Offset : 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset ADDMATCH Type/Reset Reserved RSAAD RSNMM...
Page 452: Usart Synchronous Control Register - Syncr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USART Synchronous Control Register – SYNCR This register is used to control the USART synchronous mode. Offset : 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Reserved CLKEN Type/Reset...
Page 453: Usart Divider Latch Register - Usrdlr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USART Divider Latch Register – USRDLR The register is used to determine the USART clock divided ratio to generate the appropriate baud rate. Offset : 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved...
Page 454: Usart Test Register - Usrtstr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USART Test Register – USRTSTR This register controls the USART debug mode. Offset : 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0]...
Page 455: Universal Asynchronous Receiver Transmitter (Uart)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Universal Asynchronous Receiver Transmitter (UART) Introduction The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.
Page 456: Features
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Features ▄ Supports asynchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate clock frequency up to (f / 16) MHz PCLK ▄ Fully programmable serial communication functions including: ●...
Page 457: Baud Rate Generation
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 7-Bit Data Format (WLS[1:0]=0x00, PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Stop Bit 8-Bit Data Format (WLS[1:0]=0x01, PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4...
Page 458: Interrupts And Status
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 56. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz Baud rate CK_UART = 48 MHz Kbps Actual Deviation Error rate 20000 0.00% 5000 0.00% 19.2 19.2 2500 0.00% 57.6 57.6...
Page 459: Pdma Interface
Cortex ® -M3 MCU HT32F12345 PDMA Interface The PDMA interface is integrated in the UART. The PDMA function can be enabled by setting the TXDMAEN or RXDMAEN bit in the URCR register to 1 in the transmit or receive mode respectively.
Page 460: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions UART Data Register – URDR The register is used to access the UART transmitted and received data. Offset : 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset...
Page 461: Uart Control Register - Urcr
Cortex ® -M3 MCU HT32F12345 UART Control Register – URCR The register specifies the serial parameters such as data length, parity, and stop bit for the UART. It also contains the UART enable control bits together with the UART mode and data transfer mode selections.
Page 462: Uart Interrupt Enable Register - Urier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [9:8] Word Length Select 00: 7 bits 01: 8 bits 10: 9 bits 11: Reserved RXDMAEN UART RX DMA Enable 0: Disabled 1: Enabled TXDMAEN UART TX DMA Enable...
Page 463: Uart Status & Interrupt Flag Register - Ursifr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions FEIE Framing Error Interrupt Enable 0: Disable interrupt 1: Enable interrupt If this bit is set to 1, an interrupt is generated when the FEI bit is set in the URSIFR register.
Page 464 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions Transmit Complete 0: Either the transmit data register (TDR) or transmit shift register (TSR) is not empty 1: Both the transmit data register (TDR) and transmit shift register (TSR) are...
Page 465: Uart Divider Latch Register - Urdlr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 UART Divider Latch Register – URDLR The register is used to determine the UART clock divided ratio to generate the appropriate baud rate. Offset : 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved...
Page 466: Uart Test Register - Urtstr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 UART Test Register – URTSTR This register controls the UART debug mode. Offset : 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0]...
Page 467: Usb Device Controller (Usb)
® Cortex ® -M3 MCU HT32F12345 USB Device Controller (USB) Introduction The USB device controller is compliant with the USB 2.0 full-speed specification. There is one control endpoint know as Endpoint 0 and seven configurable endpoints (EP1 ~ EP7). A 1024- byte EP_SRAM is used for the endpoint buffers.
Page 468: Functional Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Functional Descriptions Endpoints The USB Endpoint 0 is the only bidirectional endpoint dedicated to USB control transfer. The device also contains seven unidirectional endpoints for other USB transfer types. There are three endpoints (EP1 ~ EP3) which supports a single buffering function which is used for Bulk and Interrupt IN or OUT data transfer.
Page 469: Serial Interface Engine - Sie
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 1,024 bytes EP_SRAM 0x3FF Not used space: 158 words 0x188 Endpoint 5 buffer 1: 64 bytes Double-buffered 0x148 Bulk OUT endpoint Endpoint 5 buffer 0: 64 bytes 0x108 Endpoint 4 buffer 1:...
Page 470: Figure 166. Double-Buffering Operation Example
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 IN Transaction Buffer toggled by SIE hardware Endpoint 4 Endpoint 4 Endpoint 4 Buffer Accessed by USB SIE Buf 0 Buf 1 Buf 0 1st Data packet 2nd Data packet 3rd Data packet...
Page 471: Suspend Mode And Wake-Up
Cortex ® -M3 MCU HT32F12345 Suspend Mode and Wake-up According to USB specifications, the device must enter the suspend mode after a 3 ms bus idle time. When the USB device enters the suspend mode, the current from the USB bus must not be greater than 500 μA to meet the specification suspend mode current requirements.
Page 472 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Offset Description Reset Value USBEP3IER 0x054 USB Endpoint 3 Interrupt Enable Register 0x0000_0000 USBEP3ISR 0x058 USB Endpoint 3 Interrupt Status Register 0x0000_0000 USBEP3TCR 0x05C USB Endpoint 3 Transfer Count Register 0x0000_0000...
Page 473: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions USB Control and Status Register – USBCSR This register specifies the USB control bits and USB data line status. Offset: 0x000 Reset value: 0x0000_00X6 Reserved Type/Reset Reserved Type/Reset Reserved DPWKEN...
Page 474: Table 62. Resume Event Detection
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions GENRSM Resume Request Generation Control This bit is used to generate a resume request which is sent to the USB host by writing 1 into this bit location. The USB remote wakeup function is always enabled.
Page 475: Usb Interrupt Enable Register - Usbier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USB Interrupt Enable Register – USBIER This register specifies the USB interrupt enable control. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EP7IE EP6IE EP5IE EP4IE EP3IE EP2IE EP1IE EP0IE Type/Reset...
Page 476: Usb Interrupt Status Register - Usbisr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USB Interrupt Status Register – USBISR This register specifies the USB interrupt status. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EP7IF EP6IF EP5IF EP4IF EP3IF EP2IF EP1IF EP0IF Type/Reset 0 WC...
Page 477: Usb Frame Count Register - Usbfcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions URSTIF USB Reset Interrupt Flag This bit is set by the hardware when the USB reset has been detected. When a USB reset occurs, the internal protocol state machine will be reset and an USB reset interrupt will be generated if the URSTIE bit in the USBIER register is set to 1.
Page 478: Usb Device Address Register - Usbdevar
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [16] SOFLCK Start-of-Frame Lock Flag This bit is set by the hardware when SOF packets have been received before the frame timer times out. Once this flag is set to 1, the frame number which is sent from the USB host will be loaded into the Frame Number field in the USBFCR register.
Page 479: Usb Endpoint 0 Control And Status Register - Usbep0Csr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USB Endpoint 0 Control and Status Register – USBEP0CSR This register specifies the Endpoint 0 control and status. Offset: 0x014 Reset value: 0x0000_0002 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved STLRX NAKRX...
Page 480: Usb Endpoint 0 Interrupt Enable Register - Usbep0Ier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions NAKTX NAK Status for transmission (IN) transfer This bit is toggled from 0 to 1 by the hardware circuitry, which will result in a NAK signal in the handshake phase of an IN transaction after an ACK signal has been received.
Page 481: Usb Endpoint 0 Interrupt Status Register - Usbep0Isr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions STRXIE SETUP Token Received Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt UERIE USB Error Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt STLIE STALL Transmitted Interrupt Enable Control...
Page 482 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11] ZLRXIF Zero Length Data Received Interrupt Flag This bit is set by the hardware when a zero length data packet is received. This bit is cleared by hardware when a SETUP Token is received or by writing 1.
Page 483: Usb Endpoint 0 Transfer Count Register - Usbep0Tcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USB Endpoint 0 Transfer Count Register – USBEP0TCR This register specifies the Endpoint 0 data transfer byte count. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved RXCNT Type/Reset 0 RO 0 RO...
Page 484: Usb Endpoint 0 Configuration Register - Usbep0Cfgr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 USB Endpoint 0 Configuration Register – USBEP0CFGR This register specifies the Endpoint 0 configurations. Offset: 0x024 Reset value: 0x8000_0002 EPEN Reserved EPADR Type/Reset 0 RO 0 RO 0 RO Reserved EPLEN Type/Reset...
Page 485: Usb Endpoint 1 ~ 3 Control And Status Register - Usbepncsr, N = 1 ~ 3
® Cortex ® -M3 MCU HT32F12345 USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 This register specifies the Endpoint 1 ~ 3 control and status bit. Offset: 0x028 (n = 1), 0x03C (n = 2), 0x050 (n = 3)
Page 486: Usb Endpoint 1 ~ 3 Interrupt Enable Register - Usbepnier, N = 1 ~ 3
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions DTGTX Data Toggle bit for transmission transfers. This bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. When the current data packet is transmitted...
Page 487: Usb Endpoint 1 ~ 3 Interrupt Status Register - Usbepnisr, N = 1 ~ 3
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions ODRXIE OUT Data Received Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt OTRXIE OUT Token Received Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 This register specifies the Endpoint 1 ~ 3 interrupt status.
Page 488: Usb Endpoint 1 ~ 3 Transfer Count Register - Usbepntcr, N = 1 ~ 3
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions ODRXIF OUT Data Received Interrupt Flag This bit is set by the hardware circuitry when a data packet is successfully received from the host for an OUT token and when an endpoint n ACK signal is sent to the host.
Page 489: Usb Endpoint 1 ~ 3 Configuration Register - Usbepncfgr, N = 1 ~ 3
® Cortex ® -M3 MCU HT32F12345 USB Endpoint 1 ~ 3 Configuration Register – USBEPnCFGR, n = 1 ~ 3 This register specifies the Endpoint 1 ~ 3 configurations. Offset: 0x038 (n = 1), 0x04C (n = 2), 0x060 (n = 3)
Page 490: Usb Endpoint 4 ~ 7 Control And Status Register - Usbepncsr, N = 4 ~ 7
® Cortex ® -M3 MCU HT32F12345 USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 This register specifies the Endpoint 4 ~ 7 control and status bits. Offset: 0x064 (n = 4), 0x078 (n = 5), 0x08C (n = 6), 0x0A0 (n = 7)
Page 491 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions MDBTG MCU Double Buffer Toggle bit The MDBTG bit is used to indicate which data buffer is accessed by the MCU if the double buffering function is enabled. It can be toggled to switch to the other buffer by the MCU application software after the data in the current buffer accessed by the MCU has been properly setup.
Page 492: Usb Endpoint 4 ~ 7 Interrupt Enable Register - Usbepnier, N = 4 ~ 7
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions DTGTX Data Toggle bit for transmission transfers. If the endpoint is not used for Isochronous transfer, this bit is available for usage. This bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted.
Page 493: Usb Endpoint 4 ~ 7 Interrupt Status Register - Usbepnisr, N = 4 ~ 7
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions ODOVIE OUT Data Buffer Overrun Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt ODRXIE OUT Data Received Interrupt Enable Control 0: Disable interrupt 1: Enable interrupt OTRXIE OUT Token Received Interrupt Enable Control...
Page 494: Usb Endpoint 4 ~ 7 Transfer Count Register - Usbepntcr, N = 4 ~ 7
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions ODOVIF OUT Data Buffer Overrun Interrupt flag This bit is set by the hardware circuitry when the received data byte count is larger than the endpoint OUT data buffer size.
Page 495: Usb Endpoint 4 ~ 7 Configuration Register - Usbepncfgr, N = 4 ~ 7
® Cortex ® -M3 MCU HT32F12345 USB Endpoint 4 ~ 7 Configuration Register – USBEPnCFGR, n = 4 ~ 7 This register specifies the Endpoint 4 ~ 7 configurations. Offset: 0x074 (n = 4), 0x088 (n = 5), 0x09C (n = 6), 0x0B0 (n = 7)
Page 496: Peripheral Direct Memory Access (Pdma)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Peripheral Direct Memory Access (PDMA) Introduction The Peripheral Direct Memory Access circuitry, PDMA, provides 12 unidirectional channels for dedicated peripherals to implement the peripheral-to-memory and memory-to-peripheral data transfer. The memory-to-memory data transfer such as the FLASH-to-SRAM or SRAM-to- SRAM type is also supported and requested by the application program.
Page 497: Functional Description
® Cortex ® -M3 MCU HT32F12345 Functional Description AHB Master The PDMA is an AHB master connected to other AHB peripherals such as the FLASH memory, the SRAM memory and the AHB-to-APB bridges through the bus-matrix. The CPU and PDMA can access different AHB slaves at the same time via the bus-matrix.
Page 498: Channel Transfer
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 63. PDMA Channel Assignments PDMA Channel Number (x = 0, 1) CH10 CH11 SPIx SPI0_RX SPI0_TX SPI1_RX SPI1_TX USARTx USR0_RX USR0_TX USR1_RX USR1_TX UARTx UR0_RX UR0_TX UR1_RX UR1_TX I2C1_RX I2C1_TX I2C0_RX...
Page 499: Transfer Request
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Channel 0: priority=very high, block count=2, block length=2 Channel 1: priority=high, block count=3, block length=4 Channel 2: priority=low, block count=3, block length=6 Priority : CH0 > CH1 > CH2 Priority: CH1 > CH2 Priority: CH1 >...
Page 500: Auto-Reload
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Linear Address Mode After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting. Circular Address Mode After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting.
Page 501 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Offset Description Reset Value PDMACH1CTSR 0x02C PDMA Channel 1 Current Transfer Size Register 0x0000_0000 PDMA Channel 2 Registers PDMACH2CR 0x030 PDMA Channel 2 Control Register 0x0000_0000 PDMACH2SADR 0x034 PDMA Channel 2 Source Address Register...
Page 502 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Offset Description Reset Value PDMACH9SADR 0x0DC PDMA Channel 9 Source Address Register 0x0000_0000 PDMACH9DADR 0x0E0 PDMA Channel 9 Destination Address Register 0x0000_0000 PDMACH9TSR 0x0E8 PDMA Channel 9 Transfer Size Register 0x0000_0000...
Page 503: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 11 This register is used to specify the PDMA channel n data transfer configuration. Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5), 0x090 (6), 0x0A8 (7), 0x0C0 (8),...
Page 504 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions SRCAMODn Channel n Source Address Mode selection 0: Linear address mode 1: Circular address mode In the linear address mode, the current source address value can be incremented or decremented determined by the SRCAINCn bit value during a complete transfer.
Page 505: Pdma Channel N Source Address Register - Pdmachnsadr, N = 0 ~ 11
Cortex ® -M3 MCU HT32F12345 PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 11 This register specifies the source address of the PDMA channel n. 0x004 (0), 0x01C (1), 0x034 (2), 0x04C (3), 0x064 (4), 0x07C (5), 0x094 (6), 0x0AC (7), 0x0C4...
Page 506: Pdma Channel N Transfer Size Register - Pdmachntsr, N = 0 ~ 11
Cortex ® -M3 MCU HT32F12345 PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 11 This register is used to specify the block transaction count and block transaction length. 0x010 (0), 0x028 (1), 0x040 (2), 0x058 (3), 0x070 (4), 0x088 (5), 0x0A0 (6), 0x0B8 (7), 0x0D0 (8),...
Page 507: Pdma Channel N Current Transfer Size Register - Pdmachnctsr, N = 0 ~ 11
Cortex ® -M3 MCU HT32F12345 PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 11 This register is used to indicate the current block transaction count. 0x014 (0), 0x02C (1), 0x044 (2), 0x05C (3), 0x074 (4), 0x08C (5), 0x0A4 (6), 0x0BC (7), 0x0D4...
Page 508: Pdma Interrupt Status Register 0 - Pdmaisr0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 PDMA Interrupt Status Register 0 – PDMAISR0 This register is used to indicate the corresponding interrupt status of the PDMA channel 0 ~ 5. Offset: 0x120 Reset value: 0x0000_0000 Reserved TEISTA5 TCISTA5...
Page 509: Pdma Interrupt Status Register 1 - Pdmaisr1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [ 2 5 ] , [ 2 0 ] , GEISTAn Channel n Global Transfer Interrupt Status ( n= 0 ~ 5) [ 1 5 ] , [ 1 0 ] ,...
Page 510: Pdma Interrupt Status Clear Register 0 - Pdmaiscr0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [ 2 6 ] , [ 2 1 ] , BEISTAn Channel n Block Transaction End Interrupt Status (n = 6 ~ 11) 0: No Block Transaction End Event Occurs...
Page 511: Pdma Interrupt Status Clear Register 1 - Pdmaiscr1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [ 2 7 ] , [ 2 2 ] , HTRICLRn Channel n Half Transfer Interrupt Status Clear (n = 0 ~ 5) 0: No Operation [ 1 7 ] , [ 1 2 ] ,...
Page 512: Pdma Interrupt Enable Register 0 - Pdmaier0
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [ 2 7 ] , [ 2 2 ] , HTRICLRn Channel n Half Transfer Interrupt Status Clear (n = 6 ~ 11) 0: No Operation [ 1 7 ] , [ 1 2 ] ,...
Page 513: Pdma Interrupt Enable Register 1 - Pdmaier1
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [ 2 6 ] , [ 2 1 ] , BEIEn Channel n Block Transaction End Interrupt Enable control (n = 0 ~ 5) 0: Block Transaction End interrupt is disabled...
Page 514: Extend Bus Interface (Ebi)
® Cortex ® -M3 MCU HT32F12345 Extend Bus Interface (EBI) Introduction The external bus interface is able to access external parallel interface devices such as SRAM, Flash and LCD modules. The interface is memory mapped into the internal address bus of the Cortex -M3.
Page 515: Functional Descriptions
® Cortex ® -M3 MCU HT32F12345 Functional Descriptions An overview of the EBI module is shown in Figure 170. The EBI enables internal CPU and other bus matrix master peripherals to access external memories or devices. The EBI automatically translates the internal AHB transactions into the external device protocol. In particular, if the selected external memory is 16-bit or 8-bit width, then 32-bit wide transactions on the AHB are auto split into consecutive 16-bit or 8-bit accesses.
Page 516: Non-Multiplexed 8-Bit Data 8-Bit Address Mode
Cortex ® -M3 MCU HT32F12345 Non-multiplexed 8-bit Data 8-bit Address Mode In this mode, 8-bit address and 8-bit data is supported. The address is located on the higher 8 bits of the EBI_AD lines and the data uses the lower 8 bits. This mode is set by programming the MODE field in the EBICR register to D8A8.
Page 517: Non-Multiplexed 16-Bit Data N-Bit Address Mode
Cortex ® -M3 MCU HT32F12345 Non-multiplexed 16-bit Data N-bit Address Mode In this non-multiplexed mode 16-bit data is provided on the 16 EBI_AD lines. The addresses are provided on the EBI_A lines. This mode is set by programming the MODE field in the EBICR register to D16.
Page 518: Multiplexed 16-Bit Data, 16-Bit Address Mode
Cortex ® -M3 MCU HT32F12345 Since the internal AHB address (HADDR) is a byte (8-bit) address whereas the 16-bit width of external device is addressed in words (16-bit), the address actually issued to the external device varies according to the data width as shown in the following table.
Page 519: Multiplexed 8-Bit Data, 24-Bit Address Mode
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADDRSETUP ADDRHOLD WESETUP WESTRB WEHOLD (1, 2, 3, …) (0, 1, 2, …) (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …) DATA[15:0] EBI_AD[15:0] ADDR[16:1] EBI_ALE EBI_CSn EBI_WE Figure 177. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation...
Page 520: Page Read Operation
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADDRSETUP ADDRHOLD WESETUP WESTRB WEHOLD (1, 2, 3, …) (0, 1, 2, …) (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …) ADDR[7:0] EBI_AD[15:8] ADDR[23:16] EBI_AD[7:0] DATA[7:0] ADDR[15:8] EBI_ALE...
Page 521: Figure 180. Ebi Non-Multiplexed 8-Bit Data, 8-Bit Address Mode For Page Read Operation
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 RDSETUP RDSTRB RDPG RDPG RDPG RDHOLD (0, 1, 2, …) (1, 2, 3, …) (1, 2, 3, …) (1, 2, 3, …) (1, 2, 3, …) (0, 1, 2, …) EBI_AD[15:8] ADDR3...
Page 522: Figure 183. Ebi Multiplexed 8-Bit Data, 24-Bit Address Mode For Page Read Operation
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 ADDRSETUP RDSETUP RDSTRB RDPG RDPG RDPG RDHOLD (1, 2, 3, …) (0, 1, 2, …) (1, 2, 3, …) (1, 2, 3, …) (1, 2, 3, …) (1, 2, 3, …) (0, 1, 2, …)
Page 523: Write Buffer And Ebi Status
® Cortex ® -M3 MCU HT32F12345 Write Buffer and EBI Status The EBI has a 32-bit wide write buffer. The write buffer can be used to limit stalling of an AHB write burst transaction which comes from the Cortex ®...
Page 524: Ahb Transaction Width Conversion
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 RDSETUP RDSTRB RDHOLD RDSETUP RDSTRB RDHOLD IDLE (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …) (0, 1, 2, …) (1, 2, 3, …) (0, 1, 2, …) EBI_A[N:0]...
Page 525: Ebi Bank Access
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 67. EBI Maps AHB Transactions Width to External Device Transactions Width Using Byte Lane EBI_BL [1:0] Access from AHB Master Access to External Bus Interface (EBI) External Output Output Access Address...
Page 526: Ebi Ready
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 0xFFFF_FFFF 0x7000_0000 EBI Selection Bank 0x6000_0000 EBI Bank 3 (64MB) 0x6C00_0000 0x4000_0000 EBI Bank 2 (64MB) 64 MBytes 0x6800_0000 EBI Bank 1 (64MB) 0x6400_0000 EBI Bank 0 (64MB) 0x6000_0000 SRAM 0x2000_0000 0x1F00_0000...
Page 527: Pdma Request
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 PDMA Request The EBI only supports using a software trigger for active PDMA service. Register Map The following table shows the EBI register and reset value. Table 68. Register Map of EBI...
Page 528: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions EBI Control Register – EBICR This register specifies the control setting for EBI bank. Offset: 0x000 Reset value: 0x0000_0000 IDLET BLEN3 BLEN2 BLEN1 BLEN0 Type/Reset 0 RW 0 RW 0 RW...
Page 529 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [22] ARDYEN3 Asynchronous Ready Enable 3 0: Disable EBI asynchronous ready control functionality 1: Enable EBI asynchronous ready control functionality Enable or disable the asynchronous ready functionality for bank 3.
Page 530 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11] BANKEN3 Bank 3 Enable 0: Disable 1: Enable This bit enables or disables bank 3. [10] BANKEN2 Bank 2 Enable 0: Disable 1: Enable This bit enables or disables bank 2.
Page 531: Ebi Page Control Register - Ebipcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EBI Page Control Register – EBIPCR This register specifies the EBI page read configuration setting. Offset: 0x004 Reset value: 0x0000_0F00 Reserved Type/Reset PAGEOPEN Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 532: Ebi Status Register - Ebisr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EBI Status Register – EBISR This register indicates the EBI status. Offset: 0x008 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset Reserved EBISMRST Type/Reset Reserved EBIARDY Reserved EBIBUSY Type/Reset Bits Field Descriptions EBISMRST...
Page 533: Ebi Address Timing Register N - Ebiatrn, N = 0 ~ 3
® Cortex ® -M3 MCU HT32F12345 EBI Address Timing Register n – EBIATRn, n = 0 ~ 3 This register specifies the address timing setting for bank n. (n = 0 ~ 3) Offset: 0x010 (n = 0), 0x20 (n = 1), 0x30 (n = 2), 0x40 (n = 3)
Page 534: Ebi Read Timing Register N - Ebirtrn, N = 0 ~ 3
® Cortex ® -M3 MCU HT32F12345 EBI Read Timing Register n – EBIRTRn, n = 0 ~ 3 This register specifies the read timing setting for bank n. (n = 0 ~ 3) Offset: 0x014 (n = 0), 0x24 (n = 1), 0x34 (n = 2), 0x44 (n = 3)
Page 535: Ebi Write Timing Register N - Ebiwtrn, N = 0 ~ 3
® Cortex ® -M3 MCU HT32F12345 EBI Write Timing Register n – EBIWTRn, n = 0 ~ 3 This register specifies the write timing setting for bank n. (n = 0 ~ 3) Offset: 0x018 (n = 0), 0x28 (n = 1), 0x38 (n = 2), 0x48 (n = 3)
Page 536: Ebi Parity Register N - Ebipr, N = 0 ~ 3
® Cortex ® -M3 MCU HT32F12345 EBI Parity Register n – EBIPR, n = 0 ~ 3 This register specifies the polarity of the EBI control signal for bank n. (n = 0 ~ 3) Offset: 0x01C (n = 0), 0x2C (n = 1), 0x3C (n = 2), 0x4C (n = 3)
Page 537: Ebi Interrupt Enable Register - Ebiienr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EBI Interrupt Enable Register – EBIIENR This register specifies the EBI interrupt enable. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved ACCRSTIEN ACCDISIEN ARDYTOIEN Type/Reset Bits Field Descriptions...
Page 538: Ebi Interrupt Clear Register - Ebiifcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 EBI Interrupt Clear Register – EBIIFCR This register specifies interrupt clear for the EBI interrupt. Offset: 0x058 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved ACCERRIC ARDYTOIC Type/Reset 0 WO...
Page 539: Inter-Ic Sound
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Inter-IC Sound (I Introduction The I S is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as ADCs or DACs. The I S supports a variety of data formats.
Page 540: Functional Description
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Functional Description S Master and Slave Mode The I S can operate in slave or master mode. Within the I S module the difference between these modes lies in the word select (WS) signal which determines the timing of data transmissions.
Page 541: I 2 S Clock Rate Generator
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S Clock Rate Generator The main (I2S_MCLK) and bit clock (I2S_BCLK) rates for the I S are determined by the values in the I2SCDR register. The required I S bit clock rate setting depends on the desired audio sample rate desired, the format (stereo / mono) used and the data size.
Page 542: Table 70. Recommend Fs List @ 48 Mhz Pclk
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 70. Recommend FS List @ 48 MHz PCLK 512 F 384 F 256 F 192 F 128 F 64 F Fs (Hz) 8,000 11,025 12,000 16,000 22,050 24,000 32,000 44,100 48,000 —...
Page 543: I 2 S Interface Format
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S Interface Format S-justified Stereo Mode The standard I S-justified mode is where the Most Significant Bit (MSB) of the stereo audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In the stereo mode, a low WS state indicates left channel data and a high state indicates right channel data.
Page 544: Figure 194. Left-Justified Stereo Mode Waveforms (32-Bit Channel Extended)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 BCLK Channel Left Channel Right SDO/SDI 0 forced or skipped 0 forced or skipped Sample size: 8, 16 or 24-bit (32 - Sample size) bits remaining Figure 194. Left-justified Stereo Mode Waveforms (32-bit Channel Extended)
Page 545: Figure 197. I S-Justified Mono Mode Waveforms
® Cortex ® -M3 MCU HT32F12345 S-justified Mono Mode In the I S-justified mono mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a falling edge on the WS signal.
Page 546: Figure 200. Left-Justified Mono Mode Waveforms (32-Bit Channel Extended)
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 BCLK BCLK SDO/SDI 0 forced or skipped 0 forced or skipped (32 - Sample size) 1 BCLK Sample size: 8, 16 or bits remaining 24-bit Figure 200. Left-justified Mono Mode Waveforms (32-bit Channel Extended)
Page 547: Fifo Control And Arrangement
® Cortex ® -M3 MCU HT32F12345 S-justified Repeat Mode In the I S-justified repeat mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In this mode the same data is transmitted twice, once when WS is low and again when WS is high.
Page 548: Figure 205. Fifo Data Content Arrangement For Various Modes
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 FIFO Pointer Address Mono 8-bit Data Mono 16-bit Data Mono 24-bit Data Mono 32-bit Data Stereo 8-bit Data LEFT+1 RIGHT+1 LEFT RIGHT Stereo 16-bit Data LEFT RIGHT Stereo 24-bit Data LEFT RIGHT...
Page 549: Pdma And Interrupt
® Cortex ® -M3 MCU HT32F12345 PDMA and Interrupt When the level of received data in the RX FIFO is equal to or greater than the level defined by the RXFTLS field in the I S FIFO control register (I2SFCR), the relative RXFTL flag will be set and then an I S RX PDMA request will be generated.
Page 550: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions S Control Register – I2SCR This register specifies the corresponding I S function enable control. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved MCKINV BCKINV RCSEL RCEN Type/Reset 0 RW...
Page 551 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [11] CHANNEL Stereo or Mono 0: Stereo 1: Mono Note: This bit should be configured when I S is disabled. [10] REPEAT Repeat Mode 0: Disable 1: Enable This mode is for I S-justified stereo configuration only, transmitting the mono data on both channels and receiving just the left channel data and ignoring the right.
Page 552: I 2 S Interrupt Enable Register - I2Sier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S Interrupt Enable Register – I2SIER This register contains the corresponding I S interrupt enable bits. Offset : 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved RXOVIEN RXUDIEN RXFTLIEN Reserved...
Page 553: I 2 S Clock Divider Register - I2Scdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S Clock Divider Register – I2SCDR This register specifics the I S clock divider ratio. Offset : 0x008 Reset value: 0x0000_0000 Reserved Type/Reset N_DIV Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 554: I 2 S Tx Data Register - I2Stxdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S TX Data Register – I2STXDR This register is used to specify the I S transmitted data. Offset : 0x00C Reset value: 0x0000_0000 TXDR Type/Reset 0 WO 0 WO 0 WO 0 WO...
Page 555: I 2 S Fifo Control Register - I2Sfcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S FIFO Control Register – I2SFCR This register contains the related I S FIFO control bits. Offset : 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved RXFRST TXFRST Type/Reset 0 RW...
Page 556: I 2 S Status Register - I2Ssr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S Status Register – I2SSR This register contains the relevant I S status. Offset : 0x018 Reset value: 0x0000_0809 RXFS TXFS Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO...
Page 557 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [10] RXFOV RX FIFO Overflow Flag 0: RX FIFO not overflow 1: RX FIFO overflow This bit is set by hardware and cleared by writing 1. RXFUD RX FIFO Underflow Flag...
Page 558: I 2 S Rate Counter Value Register - I2Srcntr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 S Rate Counter Value Register – I2SRCNTR This register specifics the I S rate control counter value. Offset : 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved RCNTR Type/Reset 0 RW 0 RW...
Page 559: Cyclic Redundancy Check (Crc)
® Cortex ® -M3 MCU HT32F12345 Cyclic Redundancy Check (CRC) Introduction The CRC (Cyclic Redundancy Check) calculation unit is an error detection technique test algorithm and uses to verify data transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as input and generates a 16-bit or 32-bit output remainder.
Page 560: Functional Descriptions
® Cortex ® -M3 MCU HT32F12345 Functional Descriptions This unit only enables the calculation in the CRC16, CCITT CRC16 and IEEE-802.3 CRC32 polynomial. In this unit, the generator polynomial is fixed to the numeric values for those modes; therefore, the CRC value based on other generator polynomials cannot be calculated.
Page 561: Crc With Pdma
Cortex ® -M3 MCU HT32F12345 CRC with PDMA A PDMA channel with software trigger may be used to transfer data into the CRC unit. If a huge block data is needed to calculate. The recommended PDMA model is to use the PDMA to transfer all available words of data and uses software writes to transfer the other remaining bytes.
Page 562: Register Descriptions
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Descriptions CRC Control Register – CRCCR This register specifies the corresponding CRC function enable control. Offset : 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset SUMCMPL SUMBYRV SUMBIRV DATCMPL DATBYRV DATBIRV...
Page 563: Crc Seed Register - Crcsdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 CRC Seed Register – CRCSDR This register is used to specify the CRC seed. Offset : 0x004 Reset value: 0x0000_0000 SEED Type/Reset 0 WO 0 WO 0 WO 0 WO 0 WO...
Page 564: Crc Data Register - Crcdr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 CRC Data Register – CRCDR This register is used to specify the CRC input data. Offset : 0x00C Reset value: 0x0000_0000 CRCDATA Type/Reset 0 WO 0 WO 0 WO 0 WO 0 WO...
Page 565: Sdio Host Controller (Sdio)
® Cortex ® -M3 MCU HT32F12345 SDIO Host Controller (SDIO) Introduction The SDIO Host Controller supports Multi-Media Cards (MMC), the SD Memory Cards and SD I/O cards. The SDIO communication is based on an advanced 6-pin interface composed of clock, command and 4 ×...
Page 566: Sd Clock
Cortex ® -M3 MCU HT32F12345 SD Clock The SD_CLK is a clock driven by the SDIO controller and transmitted to the card. When the CK_ AHB is operating at 96 MHz, the maximum SD_CLK frequency is 48 MHz in the high speed mode and 24 MHz in the normal speed mode.
Page 567: Sd Protocol
Cortex ® -M3 MCU HT32F12345 SD Protocol SD communication over the SD bus is based on command, response and data bit streams that are initiated by a start bit and terminated by a stop bit. On the CMD line the MSB bit is transmitted first.
Page 568: Command
Cortex ® -M3 MCU HT32F12345 Command The total length of a command is 48 bits. Each command is preceded by a start bit (0) and succeeded by an end bit (1). Each command is protected by CRC bits, so that transmission errors can be detected and the operation may be repeated.
Page 569: Data
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Table 77. Response R2 Format Bit position [135] [134] [133:128] [127:8] [7:1] Width (bits) Value ‘0’ ‘0’ ‘111111’ ‘1’ Description Start bit Transmission bit Reserved CID or CSD register CRC7 End bit Table 78.
Page 570: Figure 219. Usual Data Format For Wide Bus - Dat0~Dat3 Used
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Start bit 1st Byte 2nd Byte 3rd Byte n th Byte End bit Data Data Data Data DAT3 b7 b3 b7 b3 b7 b3 b7 b3 DAT2 b6 b2 b6 b2 b6 b2...
Page 571: Buffer Status
Cortex ® -M3 MCU HT32F12345 Buffer Status The SDIO contains an 8 × 32-bit data buffer shared by both data read and write operations. The buffer level can be checked by reading the BLSTA field in the Present State Register and the data can be read from or written into the buffer by accessing the Data Port Register.
Page 572: Register Map
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Command Abbreviation Fields and Values Description CMD6 SWITCH_FUNC CMD17 READ_SINGLE_BLOCK CMD18 READ_MULTIPLE_BLOCK CMD24 WRITE_SINGLE_BLOCK RESP_TYPE = 2 Block data DAT_PRESENT = 1 operation CMD25 WRITE_MULTIPLE_BLOCK CMD53 (Note) IO_RW_EXTEND ACMD13 SD_STATUS ACMD51 SEND_SCR Note: SD I/O card specified commands.
Page 573: Register Description
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Register Description Block Size Register – BLSIZE This register is used to configure the number of bytes in a data block. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BLSIZE...
Page 574: Block Count Register - Blcnt
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Block Count Register – BLCNT This register is used to configure the number of data blocks. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset BLCNT Type/Reset 0 RW 0 RW 0 RW...
Page 575: Transfer Mode Register - Tmr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [31:0] Command Argument This register contains the command argument which will be sent to a SD device as part of a command message. Transfer Mode Register – TMR This register is used to control the date transfer operations.
Page 576: Command Register - Cmd
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Command Register – CMD Writing to this register triggers SD command generation. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CMDIDX Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 577: Response Register N - Respn, N = 0 ~ 3
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [1:0] RTSEL Response Type Select 00: No Response 01: Response Length 136 10: Response Length 48 11: Response Length 48 – Check busy after response Index Check CRC Check...
Page 578: Data Port Register - Dr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Data Port Register – DR This 32-bit data port register is used to access the internal buffer. Offset: 0x024 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...
Page 579 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [23:20] BLSTA Buffer Level State 0000: Buffer contains no data 0001: Buffer contains 1 × 32-bit data … 1000: Buffer contains 8 × 32-bit data Others: Reserved [19] BURAW...
Page 580: Control Register - Cr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Control Register – CR This register is used to specify the speed mode and data transfer width. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved HSMEN DATWID Reserved...
Page 581: Clock Control Register - Clkcr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Clock Control Register – CLKCR This register is used to configure the SD clock frequency and enable control. Offset: 0x038 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CLKPRE Type/Reset 0 RW 0 RW...
Page 582: Timeout Control Register - Tmocr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Timeout Control Register – TMOCR This register is used to specify the data timeout counter value. Offset: 0x03C Reset value: 0x0000_0000 Reserved Type/Reset TMOVAL Type/Reset 0 RW 0 RW 0 RW 0 RW...
Page 583: Software Reset Register - Swrst
Cortex ® -M3 MCU HT32F12345 Software Reset Register – SWRST A reset pulse is generated when writing 1 to each bit of this register. Because it takes some time to complete a software reset, the SD Host Driver should confirm that these bits are 0.
Page 584: Status Register - Sr
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Status Register – SR This register contains the host controller status bits. Offset: 0x044 Reset value: 0x0000_0000 Reserved CICESTA CIDESTA CISTA Type/Reset 0 WC 0 RO Reserved DEESTA DCESTA DTESTA CIESTA CEESTA...
Page 585 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [20] DTESTA Data Timeout Error Status 0: No Error 1: Time Out This bit will be set when detecting one of the following timeout conditions. (1) Busy timeout for R1b, R5b type...
Page 586: Status Enable Register - Ser
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions TCSTA Transfer Complete Status 0: Not Complete 1: Command execution is completed This bit will be set to 1 when a read / write transfer and a command with busy have completed.
Page 587 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [20] DTESEN Data Timeout Error Status Enable 0: Masked 1: Enable [19] CIESEN Command Index Error Status Enable 0: Masked 1: Enable [18] CEESEN Command End Bit Error Status Enable...
Page 588: Interrupt Enable Register - Ier
32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Interrupt Enable Register – IER These status bits all share the same 1-bit interrupt line. Setting any of these bits to 1 enables interrupt generation. Offset: 0x04C Reset value: 0x0000_0000 Reserved CICEIEN...
Page 589 32-Bit Arm ® Cortex ® -M3 MCU HT32F12345 Bits Field Descriptions [16] CTEIEN Command Timeout Error Interrupt Enable 0: Masked 1: Enable BEIEN Buffer Empty Interrupt Enable 0: Masked 1: Enable BFIEN Buffer Full Interrupt Enable 0: Masked 1: Enable...
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