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IC101 VHiCS493264-1: DSP (CS493264) (3/3)
Pin No.
Terminal Name
43
SCLK
44
MCLK
A0, SCCLK
DATA7, EMDA7, GPIO7
DATA6, EMDA6, GPIO6
DATA5, EMDA5, GPIO5
DATA4, EMDA4, GPIO4
DATA3, EMDA3, GPIO3
DATA2, EMDA2, GPIO2
DATA1, EMDA1, GPIO1
DATA0, EMDA0, GPIO0
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Input/Output
Input
Bidirectional digital-audio output bit clock. SCLK can be an output that is derived
from MCLK to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the
MCLK rate and the digital-output configuration. SCLK can also be an input and
must be at least 48 Fs or greater. As an input, SCLK is independent of MCLK.
Input
Bidirectional master audio clock. MCLK can be an output from the CS493XX that
provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs.
MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to
derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS493XX.
6
5
4
3
7
8
9
10
11
VD2
12
CS493264
DGND2
13
14
15
16
17
18
19
20
21
Figure 45 BLOCK DIAGRAM OF IC
Function
2
1
44
43
42
41
40
39
38
37
36
35
IC101
34
33
32
31
30
29
22
23
24
25
26
27
28
– 45 –
SD-AT1000
AUDATA2
DC
DD
RESET
AGND
VA
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ, LRCLKN2
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