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1
1
2
2
3
3
14 13 12 11
9
8
1
2
3
4
5
6
7
+3.3V(D)
6
7
8
IC103
TC7WU04U
DUAL2-INPUT
NAND GATE
4
3
2
1
EX_CLK
ZD101
28 27 26 25 24 23 22 21 20 19 18
SCLKN2
LRCLKN2
29
CLKIN
30
VA
34
AGND
35
RESET
36
39
40
41
42
Figure 15 BLOCK DIAGRAM (4/10)
– 15 –
D0
17
EMAD0
16
D1
EMAD1
D2
15
EMAD2
14
D3
EMAD3
IC101
DGND2
13
CS493264
+2.5V(A)
12
VD2
DSP
D4
11
EMAD4
10
D5
EMAD5
D6
9
EMAD6
8
D7
EMAD7
7
_DSP_SCCLK
43
44
1
2
4
5
6
SD-AT1000
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