Pin States in Power Save Modes
UD[3:0], LD[3:0], LP,
XSCL, YD, WF/XSCL2
(Note 1)
UD[3:0], LD[3:0], LP,
XSCL, YD, WF/XSCL2
(Note 2)
AB[19:0], DB[15:0]
IOR#, IOW#
MEMR#, MEMW#
RESET
Notes: 1. Internal Register AUX[03], bit 5 = 1
2. Internal Register AUX[03], bit 5 = 0
S18A-A-011-01
Table 8-11 Pin States in Power Save Modes
Pin
Normal
(Active)
Active
Active
Active
Active
Active
Active
S1D13503 Series Hardware Functional Specification
Pin State
PSM1
State 1
State 2
High
High
Impedance
Impedance
Forced Low
Forced Low
Active
Active
Active
Active
Active
Active
Active
Active
PSM2
High
Impedance
Forced Low
Active
Active
Active
Active
1-53