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4. PIN DESCRIPTION
Pin name
O0 ~ O79
D0 ~ D3
XSCL
LP
EIO1, EIO2
SHL
FR
DSPOFF
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V
, V
DD
SS
V0, V2,
V3, V5
*1
*1 Be sure to connect V
Rev.2.1
I/O
Segment (column) output for LCD driving
O
The output changes at the LP falling edge.
I
Display data input
I
Display data shift clock input (Falling edge trigger)
Display data latch pulse input (Falling edge trigger)
I
Enable input/output
To be set to input or output according to the SHL input level.
I/O
The output is reset by the LP input. Upon the end of fetching of
80-bit data, the system starts up automatically to HIGH.
Shift direction selection and EIO pin I/O control input When data
is input to (D3, D2 ... D0 ) pins sequentially in order of (a3, a2,
a1, a0), (b3, b2, b1, b0) ... (t3, t2, t1, t0), the relationship
between the data and segment output becomes as shown in the
table below:
SHL
I
LOW a3 b2
HIGH t0
(Note) The relationship between the data and segment output is
determined irrespective of the number of shift clock
inputs.
I
LCD drive output AC converted signal input
Force input of blank
I
V0 level is forcibly set by entering LOW level (available with
S1D16006D01
Logic power supply
Power supply
LCD drive circuit power supply
Power supply
When used at a same potential, V
grounding them close to the IC chip.
to V
to their LCD power, respectively.
0
5
Function
O Output
79 78 77
2
1
c1 . . . t2
t1
t1
t2 . . . a1
a2 a3 Input Output
alone).
**
V
: 0 V V
DD
V
: 0 V V
DD
≥ V
V
DD
≥ V
3/9 V
5
and V
0
EPSON
S1D16006 Series
EIO
0
EIO1
EIO2
t0 Output Input
: –2.7 V to –5.5 V
SS
: –8 V to –28 V
5
≥ V
≥ 6/9 V
0
2
5
≥ V
3
5
are used by
DD
S1D16006D00
(including four NC'4)
**
S1D16006D01
(including four NC'3)
**
Number
of pins
80
4
1
1
2
1
1
1
2
4
Total: 100
1–3
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