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6.
Clock/Mode control
6.2
Registers
6.2.6
CGCKSEL (System clock selection register)
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
Bit Symbol
31-2
−
1
SYSCK
0
SYSCKFLG
2019-02-06
31
30
29
-
-
-
0
0
0
23
22
21
-
-
-
0
0
0
15
14
13
-
-
-
0
0
0
7
6
5
-
-
-
0
0
0
Type
R
Read as "0".
R/W
Selects system clock
0: high-speed
1: low-speed
Specifies system clock.
When change value of <SYSCK>, oscillation must stable High-speed oscillator (f
speed oscillator.
According to the used oscillator, corresponding CGOSCCR<XEN1>, <XEN2> or <XTEN> must be set to
"1" in advance.
R
System clock status
0: high-speed
1: low-speed
Shows the status of the system clock.
When switching the oscillator with <SYSCK>, generates time lag to complete.
If the read value from <SYSCKFLG> is the same as the value specified in <SYSCK>, the switching has
been completed.
28
27
-
-
0
0
20
19
-
-
0
0
12
11
-
-
0
0
4
3
-
-
0
0
Function
Page 52
TMPM3V6/M3V4
26
25
24
-
-
-
0
0
0
18
17
16
-
-
-
0
0
0
10
9
8
-
-
-
0
0
0
2
1
0
-
SYSCK
SYSCKFLG
0
0
0
or f
) and Low-
EHOSC
IHOSC
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