System Clock Controller; Configuration - Toshiba TLCS-870/C1 Series Manual

2.3 System clock controller

2.3.1 Configuration

The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up
counter and an operation mode control circuit.
Clock generator
XIN
High-frequency
clock oscillation
circuit
XOUT
XTIN
Low-frequency clock
oscillation circuit
XTOUT
2.3.2 Control
The system clock controller is controlled by system control register 1 (SYSCR1), system control register 2
(SYSCR2), the warm-up counter control register (WUCCR), the warm-up counter data register (WUCDR) and
the clock gear control register (CGCR).
System control register 1
SYSCR1
(0x0FDC)
Bit Symbol
Read/Write
After reset
STOP Activates the STOP mode
Selects the STOP mode release
RELM
method
Selects the port output state in the
OUTEN
STOP mode
Selects the input clock to stage 9 of
DV9CK
the divider
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0". Bit 3 is read as "1".
WUCCR
Warm-up counter
fc
Clock gear
(x1/4,x1/2,x1)
FCGCKSEL
Clock gear control register
fs
Oscillation/stop control
Figure 2-3 System Clock Controller
7 6 5
STOP RELM OUTEN
R/W R/W R/W
0 0 0
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
WUCDR
INTWUC interrupt
XEN/XTEN
STOP
TBTCR
fcgck
generator
System clock
1/4
4 3
DV9CK -
R/W R
0 1
Operate the CPU and the peripheral circuits
Stop the CPU and the peripheral circuits (activate the STOP mode)
Edge-sensitive release mode (Release the STOP mode at the rising edge
of the STOP mode release signal)
Level-sensitive release mode (Release the STOP mode at the "H" level of
the STOP mode release signal)
High impedance
Output hold
9
fcgck/2
fs/4
TMP89FM42
SYSCR1 SYSCR2
DV9CK
Operation mode
Timing
control circuit
System control register
2 1 0
- - -
R R R
0 0 0