Burst Length - Toshiba TLCS-900/H1 Series Manual

Original cmos 32-bit microcontroller

Hide thumbs Also See for TLCS-900/H1 Series:

Table of Contents

Address multiplex function

In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The

multiplex width is set by SDACR<SMUXW1:0>. Table 3.10.2 shows the relationship

between the multiplex width and low/column addresses.

<SMUXW> = 00

*AP: Auto Precharge

Burst length

When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single write.

The burst length can be selected for SDRAM read and write accesses by HDMA if the

following conditions are satisfied:

The HDMA transfer mode is an increment mode.

Transfers are made between the SDRAM and internal RAM or internal I/O.

In other cases, HDMA operation can only be performed in 1-word read/single write mode.

Use SDBLS<SDBL5:0> to set the burst length for each HDMA channel.

Table 3.10.2 Address Multiplex

SDRAM Access Cycle Address

<SMUXW> = 01

<SMUXW> = 10

Column Address