Standard Usart Registers; Table 5-12 Standard 16550-Compatible Usart Registers - GE C2K Hardware Reference Manual

Bits Field
3 - 2 FIFO_SIZE
1 TXCLK_SRC
0 SYNC

5.2.6 Standard USART Registers

Table 5-12 lists the standard 16550-compatible USART registers. The offset is from the base
address of each USART.
Standard 16550-compatible USART registers
Table 5-12
Offset DLAB
0x0 0 Receive Buffer
Transmit Buffer
0x1 0 Interrupt Enable
0x2 X Interrupt Identification
FIFO Control
0x3 X Line Control
0x4 X Modem Control
0x5 X Line Status
0x6 X Modem Status
0x7 X Scratchpad
0x0 1 Divisor Latch (LSB)
0x1 1 Divisor Latch (MSB)
USART Receive Buffer Register
The USART Receive Buffer Register holds the incoming receive data after it has been transferred
from the incoming shift register. In FIFO mode, this register contains a receive-data byte pulled
from the top of the memory buffer.
Address offset: USART_Base +0x0
DLAB: 0
Access: Read-only
Bits Field
7 - 0 RXDATA
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Default
0b00 FIFO Size—selects the transmit and receive data FIFO
buffer size.
0 Transmit Clock Source—selects the source of the trans-
mit clock in synchronous mode.
0 Synchronization Mode—selects the synchronization
mode in which USART will operate.
Register
Receive data buffer (read).
Transmit data buffer (write).
Interrupt event enable/mask.
Interrupt event status (read).
FIFO control settings (write).
Line control settings.
Modem control settings.
Line status indications.
Modem status indications.
Scratchpad data.
Least-significant byte of baud-rate divisor.
Most-significant byte of baud-rate divisor.
Default
0x00 Receive buffer data
Description
0b00 = 16 bytes
0b01 = 64 bytes
0b10 = 256 bytes
0b11 = 1024 bytes
0 = internal baud-rate generator
1 = receive clock
0 = standard asynchronous mode
1 = external clock synchronous mode
Description
Description
Resources
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