The timer units can be used in conjunction with the UARTs to measure
the width of the pulses in the datastream to provide an autobaud detect
function for a serial channel.
The timers can generate interrupts to the processor core to provide peri-
odic events for synchronization, either to the processor clock or to a count
of external signals.
In addition to the eight general-purpose programmable timers, a 9th timer
is also provided. This extra timer is clocked by the internal processor clock
and is typically used as a system tick clock for generation of operating sys-
tem periodic interrupts.
UART Ports
The processor provides two half-duplex Universal Asynchronous
Receiver/Transmitter (UART) ports, which are fully compatible with
PC-standard UARTs. The UART ports provide a simplified UART inter-
face to other peripherals or hosts, providing half-duplex, DMA-supported,
asynchronous transfers of serial data. The UART ports include support for
5 to 8 data bits; 1 or 2 stop bits; and none, even, or odd parity. The
UART ports support two modes of operation:
• Programmed I/O
The processor sends or receives data by writing or reading
I/O-mapped UART registers. The data is double buffered on both
transmit and receive.
• Direct Memory Access (DMA)
The DMA controller transfers both transmit and receive data. This
reduces the number and frequency of interrupts required to trans-
fer data to and from memory. Each of the two UARTs have two
ADSP-BF537 Blackfin Processor Hardware Reference
Introduction
1-19
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