Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual page 637

If configured for transmit, the SPI requests a DMA read from
memory. Upon a DMA grant, the DMA engine reads a word from
memory and writes to the SPI DMA FIFO. As the SPI writes data
from the SPI DMA FIFO into the
transfer on the SPI link.
6. The SPI then generates the programmed clock pulses on
simultaneously shifts data out of
For receive transfers, the value in the shift register is loaded into
the
SPI_RDBR
fers, the value in the
register at the start of the transfer.
7. In receive mode, as long as there is data in the SPI DMA FIFO (the
FIFO is not empty), the SPI continues to request a DMA write to
memory. The DMA engine continues to read a word from the SPI
DMA FIFO and writes to memory until the SPI DMA word count
register transitions from 1 to 0. The SPI continues receiving words
until SPI DMA mode is disabled.
In transmit mode, as long as there is room in the SPI DMA FIFO
(the FIFO is not full), the SPI continues to request a DMA read
from memory. The DMA engine continues to read a word from
memory and write to the SPI DMA FIFO until the SPI DMA word
count register transitions from 1 to 0. The SPI continues transmit-
ting words until the SPI DMA FIFO is empty.
See Figure 10-8 on page 10-37
For receive DMA operations, if the DMA engine is unable to keep up with
the receive datastream, the receive buffer operates according to the state of
the bit. If
GM GM = 1
receive new data from the
register. If
SPI_RDBR
data is discarded, and the
forming receive DMA, the transmit buffer is assumed to be empty (and
ADSP-BF537 Blackfin Processor Hardware Reference
SPI Compatible Port Controllers
register at the end of the transfer. For transmit trans-
register is loaded into the shift
SPI_TDBR
for additional information.
and the DMA FIFO is full, the device continues to
pin, overwriting the older data in the
MISO
, and the DMA FIFO is full, the incoming
GM = 0
register is not updated. While per-
SPI_RDBR
register, it initiates a
SPI_TDBR
and shifts data in from
MOSI
and
SCK
.
MISO
10-31