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1
~3~!'~~0
Pl'
()c€-~~:;s()r'
M()d
u
le
1:3220·-91.
OB'7
10'7
Rev
JAN···· 0
4'-(32
3.0
FUNCTIONAL DESCRIPTION
Refer t() bl()ck diagraM
(fig.
1),
scheMatic diagraMs
(figs.
2,3),
tiMing diagraMs
(figs.
4-8), COMponent location diagraM (fig.
9)
and
parts list (fig.
10) located in the appendix.
The following describes
the ()peration of the three Major sections of the Processor peA) control
and
lID,
MeMory, and video c()ntrol.
CONTROL. AND I/O SECTION
Clock
A
25.7715
MHz
crystal is
attached to the
CRTC which oscillates at the
video
d()t frequency.
This
is buffered by
the CRTC and again
by
a
74LS244 (US11) to beCOMe DRCX,
buffered dot rate clock.
This clock is
then divided by seven by the 748163 (Ub11) to produce 3.6816 MHz, which
is shaped by Q4 and its associated circuitry to
produce a
SYMMetrical
clock for the ZaOA,
which has a zero
level
<
0.4SV and
a
one level>
4.4V.
This clock is also divided by two to produce
a
1.8408
MHz
clock
which the datacoMM chip (U613) uses to produce baud rates.
lOOA
The laOA
Microprocessor perforMS the Major
control and data Manipula-
tion functions of the processor peA.
It provides addresses and control
signals to read
and write data
frOM and to both MeMory and I/O ports.
It also responds to two externally generated interrupts, NNMI and NINT,
which,
when enabled, interrupt current execution and cause the ZaOA to
branch to its interrupt service routine.
The ZBOA also responds to a
bus request signal,
NBUSREQ,
allowing the
CRTC control of the systeM
b
u
~:)es
.
At power
up
(or
reset)
the ZaOA
begins executing
instructions frOM
prograM MeMory beginning at address OOOOH.
A
routine is executed which
initializes variables and devices according to inforMation contained in
non-volatile MeM()ry (CMOS) and perforMS a self test of ROM and
RAM.
If
an error is detected a series of beeps are issued to the keyboard which
indicate the
failing ROM or RAM.
After
inintialization
the prograM
enters
a
Major 10()P responding to inputs frOM the keyboard and datacoMM
por'ts.
Three
74LS244's
(U4'7,U57,U511)
buffer
the address and control lines
frOM the
Z80A.
The 1 of a decoder,
U76,
is
used to separate prograM
MeMory into six blocks,
each
BK
bytes long.
The addressed
ROM
is en-
abled during a MeMory read by the TNRD and
TNMREQ signals ()r during an
instructi()n fetch by the NMl
signal.
Since the tiMe to read the data
in an
instruction
fetch is less than that for a MeM()ry read,
the NM1
signal was used to provide an early enable
of
the
ROM allowing it to
respond
within the required
tiMe.
ROMs with access
tiMes of 350 ns
frOM
address or 300 ns frOM enable are required
t() run
the systeM at
full speed.
[PROMs or ROMs with 450 ns
access tiMes frOM address May
be
used by installing
JUMper WS and reMoving JUMper W6,
which causes
the
ZaOA
to wait one cycle l()nger during instructi()n fetches.
The quad
latch
U610
and ass()ciated gating provides the required
wait signal to
th~:~
ZBOA.,
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