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13220
Processor Module
13220-91087/13
Rev
JAN-04-82
outputs will never be on the l80A data bus.
The cycle proceeds as for
a read operation with TNMREQ going high, shifting
1'5
through the shift
register to cOMplete the cycle.
zaOA
REFRESH
The
nature of dynaMic
RAMs
requires that
each row Must
be accessed
every two Milliseconds to guarantee the
contents of that row are held.
The
l8UA has a
built-in refresh
function to
provide
signals
which
perforM dynaMic RAM refresh without requiring extra processor overhead.
The
ZaOA
Maintains a
7
bit MeMory refresh counter which is increMented
following
each
instruction
fetch.
While
the instruction is
being
decoded and executed the refresh counter is output on address bits TAU-
TA7 while the TNRFSH and INMREQ signals are brought low, initiating the
RAS-MUX-CAS
sequence,
refreshing that row.
Since
the TNRD and TNWR
signals reMain high during the refresh cycle,
the MeMory contents
are
unaltered and the transparent latch is not enabled so that the accessed
byte does not appear on the bus.
eRTC DMA
Twice per video row,
on scan lines 6 and 14 (if starting to count froM
0),
the NBUSREQ
signal to the
ZaOA
is activated to allow the eRTC to
perforM DMA of enhanceMent and character data (see section 3.3 for More
inforMation on the eRTC).
The
ZaOA
responds to NBUSREQ at the end of
the current
Machine cycle by tristating its address
and control lines
and activating the NBUSAK line signalling that the bus is available and
will reMain so until NBUSREQ is raised.
The NBUSAK signal is inverted
and buffered
by U79 to provide both IBUSAK
(active high)
and TNBUSAK
(active low, buffered).
These signals are used to tristate the address
and control buffers
U47,
US? and US11 and enable the video
subsysteM
for DMA action.
TBUSAK enables the CRTC to place the lower 12 bits of
the DMA
address on the bus and enables the
output of the
transparent
latch,
U62,
as well as enable the load signal to
the shift register,
USiO.
TNBUSAK enables the upper four bits of the DMA address frOM U74
onto the bus and takes the recirculating line buffer,
U38,
out of the
recirculate
Mode
(see
section
3.3
for
More
inforMation
on
DMA
addressing).
ApproxiMately
four character tiMes before the start of
the
video row
the line rate clock
(LRC)
output of
the
CRTC goes high enabling the
load Signal to the shift register through the AND gate U71U.
The load
signal
is
derived
frOM the
character
rate clock,
LCGAX,
which is
delayed three
dot tiMes through U410 in order
to synchronize
the RAM
access to the video tiMing and guarantee sufficient address set up tiMe
to the RAMs.
1he load signal causes RAS-CAS shift register, U510,
to
be parallel loaded on the
next
riSing edge of DRCX
(dot rate clock).
Upon loading, the shift register output QD is high and QA is low.
THis
condition forces the output of U77 to go low, causing a's to be shifted
through the shift register.
The next three occurances of DRCX produce
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