LSIS XBF-AD04A User Manual page 273

XGB Analog edition manual
7.11 Configuration and Function of Internal Memory
An analog mix module has internal memory for data communication with XGB base unit.
7.11.1 Analog Data I/O Area
The table below presents the analog data I/O area.
Variable
_0y_ERR
_0y_RDY
_0y_CH0_ACT
_0y_CH1_ACT
_0y_CH2_ACT
_0y_CH3_ACT
_0y_CH4_ACT
_0y_CH5_ACT
_0y_CH6_ACT
_0y_CH7_ACT
_0y_CH0_ERR
_0y_CH1_ERR
_0y_CH2_ERR
_0y_CH3_ERR
_0y_CH4_ERR
_0y_CH5_ERR
_0y_CH6_ERR
_0y_CH7_ERR
_0y_CH0_DATA
_0y_CH1_DATA
_0y_CH2_DATA
_0y_CH3_DATA
_0y_CH4_DATA
_0y_CH5_DATA
_0y_CH6_DATA
_0y_CH7_DATA
_0y_CH0_IDD
_0y_CH1_IDD
_0y_CH2_IDD
_0y_CH3_IDD
_0y_CH4_IDD
_0y_CH5_IDD
_0y_CH6_IDD
_0y_CH7_IDD
_0y_ERR_CLR
Device assignment
Type
"S"or
"H"type
BIT U0y.00.0
BIT U0y.00.F %UX0.y.15
BIT U0y.01.0 %UX0.y.16
BIT U0y.01.1 %UX0.y.17
BIT U0y.01.2 %UX0.y.18
BIT U0y.01.3 %UX0.y.19
BIT U0y.01.4 %UX0.y.20
BIT U0y.01.5 %UX0.y.21
BIT U0y.01.6 %UX0.y.22
BIT U0y.01.7 %UX0.y.23
BIT U0y.01.8 %UX0.y.24
BIT U0y.01.9 %UX0.y.25
BIT U0y.01.A %UX0.y.26
BIT U0y.01.B %UX0.y.27
BIT U0y.01.C %UX0.y.28
BIT U0y.01.D %UX0.y.29
BIT U0y.01.E %UX0.y.30
BIT U0y.01.F %UX0.y.31
WORD U0y.02 %UW0.y.2
WORD U0y.03 %UW0.y.3
WORD U0y.04 %UW0.y.4
WORD U0y.05 %UW0.y.5
WORD U0y.06 %UW0.y.6
WORD U0y.07 %UW0.y.7
WORD U0y.08 %UW0.y.8
WORD U0y.09 %UW0.y.9
BIT U0y.10.0 %UX0.y.160
BIT U0y.10.1 %UX0.y.161
BIT U0y.10.2 %UX0.y.162
BIT U0y.10.3 %UX0.y.163
BIT U0y.10.4 %UX0.y.164
BIT U0y.10.5 %UX0.y.165
BIT U0y.10.6 %UX0.y.166
BIT U0y.10.7 %UX0.y.167
BIT U0y.11.0 %UX0.y.176
Description
IEC type
%UX0.y.0 Module Error
Module Ready
CH0 Active
CH1 Active
CH2 Active
CH3 Active
CH4 Active
CH5 Active
CH6 Active
CH7 Active
CH0 error
CH1 error
CH2 error
CH3 error
CH4 error
CH5 error
CH6 error
CH7 error
CH0 Output
CH1 Output
CH2 Output
CH3 Output
CH4 Output
CH5 Output
CH6 Output
CH7 Output
CH0 Disconnection flag
CH1 Disconnection flag
CH2 Disconnection flag
CH3 Disconnection flag
CH4 Disconnection flag
CH5 Disconnection flag
CH6 Disconnection flag
CH7 Disconnection flag
Error Clear Request
7 - 28
Signal
Read/
direction
Write
AD08A → CPU
Read
AD08A → CPU
Read
AD08A → CPU
Read
AD08A → CPU
Read
AD08A → CPU
Read
Read/
AD08A ↔ CPU
Write