Xilinx Vivado MIPI CSI-2 Product Manual page 79

information on MIPI IOB compliant solution and guidance, refer D-PHY Solutions (XAPP894)
[Ref 15].
A series of interoperability test scenarios listed in
using different core configurations and resolutions. All ZCU102 designs use the native MIPI
IO available in the UltraScale+ FPGA.
Table A-2: Interoperability Testing UltraScale+ Device
Sensor
Omnivision
OV13850
Sony IMX274
Sony IMX224
ON Semi AR0330
All Xilinx 7 series FPGA interop designs use the external Meticom (MC20901) based solution
which implements MIPI D-PHY IO.
Table A-3: Interoperability Testing with Xilinx 7 Series FPGA Devices
Sensor
ZC702/
Sony IMX274
xc7z020clg484-1
ZC702/
Sony IMX274
xc7z020clg484-1
ON Semi KC705/
AR0330 xc7k325tffg900-2
ON Semi KC705/
AR0330 xc7k325tffg900-2
ON Semi ZC702/
AR0330 xc7z020clg484-1
MIPI CSI-2 RX Subsystem v4.0
PG232 July 02, 2019
Appendix A: Verification, Compliance, and Interoperability
Board/Device
ZCU102/
xczu9eg-ffvb1156-2-e
ZCU102/
xczu9eg-ffvb1156-2-e
ZCU102/
xczu9eg-ffvb1156-2-e
ZCU102/
xczu9eg-ffvb1156-2-e
Board/Device Tested Configuration
576Mb/s 4 Lanes
RAW10
1152Mb/s 2 Lanes
RAW10
490Mb/s 4 Lanes
RAW10
588Mb/s 4 Lanes
RAW12
490Mb/s 4 Lanes
RAW10
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Table A-2 and Table A-3
Tested Configuration
1200Mb/s 1, 2, 4 Lanes
RAW8, RAW10, RAW12
1440Mb/s
4 Lanes
RAW10, RAW12
149Mb/s, 594Mb/s
1, 2, 4 Lanes
RAW10, RAW12
490Mb/s 4 Lanes RAW10
Calibration Mode
Auto Enable 300 MHz
clock for
IDELAYCTRL=false
Auto Enable 300 MHz
clock for
IDELAYCTRL=true
None
None
None
are validated
Resolution
480p@60fps
720p@60fps
1080p@60fps
4k@30fps
All supported modes
by sensor
All-pixel (QVGA) and
Window cropping
modes
480p@60fps
720p@60fps
1080p@60fps
Resolution
1080p@60fps
1080p@60fps
480p@60fps
720p@60fps
1080p@60fps
2304x1296@6
0fps
1080p@60fps
2304x1296@6
0fps
480p@60fps
79
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