Xilinx Vivado MIPI CSI-2 Product Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Receiver
  5. Vivado MIPI CSI-2
  6. Product manual
Xilinx Vivado MIPI CSI-2 Product Manual

Xilinx Vivado MIPI CSI-2 Product Manual

Receiver subsystem v4.0
Hide thumbs
Table of Contents

Advertisement

Quick Links

MIPI CSI-2 Receiver
Subsystem v4.0
Product Guide
Vivado Design Suite
PG232 July 02, 2019

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Vivado MIPI CSI-2 and is the answer not in the manual?

Questions and answers

Related Manuals for Xilinx Vivado MIPI CSI-2

Summary of Contents for Xilinx Vivado MIPI CSI-2

  • Page 1 MIPI CSI-2 Receiver Subsystem v4.0 Product Guide Vivado Design Suite PG232 July 02, 2019...

  • Page 2: Table Of Contents

    Implementing the Example Design ........... 70 MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 3: Table Of Contents

    Finding Help on Xilinx.com ........
  • Page 4 • Support for 1, 2, or 4 pixels per sample at 1. For a complete list of supported devices, see the Vivado IP the output as defined in the Xilinx catalog. AXI4-Stream Video IP and System Design 2. Standalone driver details can be found in the SDK directory (<install_directory>/SDK/<release>/data/embeddedsw/doc/...
  • Page 5 Figure 1-1: Subsystem Architecture The subsystem consists of the following sub-cores: • MIPI D-PHY • MIPI CSI-2 RX Controller • AXI CrossbarVideo Format Bridge • AXI IIC MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 6: Sub-Core Details

    The final extracted image is made available to the user/processor interface using the AXI4-Stream protocol. The lane management block always operates on 32-bit data received from PPI irrespective number of lanes. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 7 Error detection (D-PHY Level Errors, Packet Level Errors, Protocol Decoding Level Errors) • AXI4-Stream interface with 32/64-bit TDATA width support to offload pixel information externally • Interrupt support for indicating internal status/error information MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 8 16. When this feature is enabled, the virtual channel is deduced by combining the 2-bit VC field (LSB) and the 2-bit VCX field (MSB) from the packet header. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 9 RAW8 respectively. The video_out port width is configured as the maximum of the individual pixel widths, and rounded to the nearest byte boundary. This results in a video_out port width of 24. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 10 When the core is configured with RAW6 and two pixels per clock, the video_out port width is set to 16-bits. Within the 16-bits the RAW6 and RAW8 pixels are aligned to the most significant bits as shown in the following table: MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 11 Table 1-5: Pixel Packing for RAW10 Data Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Position RAW10 RAW10 MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 12: Applications

    Applications The Xilinx MIPI CSI-2 RX controller implements a Camera Serial Interface between a camera sensor and a programmable device performing baseband processing. Bandwidth requirement for the camera sensor interface has gone up due to the development of higher resolution cameras.

  • Page 13: Unsupported Features

    Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative. MIPI CSI-2 RX Subsystem v4.0...

  • Page 14: Standards

    D-PHY latency, MIPI RX Controller latency and VFB latency (if Video Format Bridge is included in the Subsystem). Figure 2-1 represents the latency calculation for the subsystem MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 15 1000 26(23+3) RAW10 Dual 1200 30(26+4) RAW10 Quad 22(20+2) Notes: All the calculations are made for a single lane design with a fixed video clock of 148 MHz. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 16 RAW8 Dual 1000 RAW8 Quad 1000 RAW10 Single 1000 RAW10 Dual 1200 RAW10 Quad Notes: All the calculations are made for a fixed video clock of 148 MHz. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 17: Resource Utilization

    Clock for D-PHY core. Must be 200 MHz. video_aclk Input Subsystem clock video_aresetn Input Subsystem reset. Active-Low. AXI4-Stream Video Interface when Video Format Bridge is Present video_out_tvalid Output Data valid MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 18 Specifies the Virtual Channel Identifier (VC) value of the emb_nonimg_tdest[3:0] Output embedded non-image packet emb_nonimg_tkeep[n/8-1:0] Output Specifies valid bytes emb_nonimg_tlast Output End of line emb_nonimg_tready Input Slave ready to accept data MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 19 15-2 Reserved Packet Error Start of frame video_out_tvalid Output Data valid Other Signals csirxss_csi_irq Output Interrupt (active-High) from CSI-2 RX Controller csirxss_iic_irq Output Interrupt (active-High) from AXI IIC MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 20 Chapter 2: Product Specification Table 2-5: Port Descriptions (Cont’d) Signal Name Direction Description Xilinx 7 series FPGA mipi_dphy_if Output DPHY interface rxbyteclkhs Output PPI high-speed receive byte clock system_rst_out Output Reset indication due to PLL reset (active-High) Ready signal output from IDEALYCTRL, stating delay values...

  • Page 21: Register Space

    Core Status Register Internal status of the core 0x14 Reserved 0x18 Reserved 0x1C Reserved Global Interrupt Enable 0x20 Global interrupt enable registers Register 0x24 Interrupt Status Register Interrupt status register MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 22 0x84 Image Information 2 for VC4 with VC of 4 Image information 1 of the current processing packet 0x88 Image Information 1 for VC5 with VC of 5 MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 23 Image information 2 of the current processing packet 0xD4 VC14 with VC of 14 Image Information 1 for Image information 1 of the current processing packet 0xD8 VC15 with VC of 15 MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 24 1. The short packet and line buffer FIFO full conditions take a few clocks to reflect in the register clock domain from the core clock domain due to Clock Domain Crossing (CDC) blocks. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 25 Indicates the current status of short packet Short packet FIFO Full FIFO full condition FIFO not empty: Indicates the current status Short packet FIFO not empty of short packet FIFO not empty condition MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 26: Interrupt Status Register

    Word Count (WC) value as part of ECC correction. In such case core limits processing of the packet on reduced number of bytes received through PPI interface. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 27 Asserted after an FE when the data payload Frame level error for VC2 R/W1C received between FS and FE contains errors. (ErrFrameData) The data payload errors are CRC errors. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 28 TUSER[1] port if a partial packet is being written to line buffer. Because PPI does not allow back pressure, you need to ensure that this condition does not occur. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 29 Table 2-20: CRC Error Set Condition(s) Set by the core when the computed CRC code is different than the received CRC code. Reset Sequence Write 1 to clear this bit. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 30 Write 1 to clear this bit. Priority Set condition takes priority over reset sequence. Current packet being processed does not have any impact but the payload might be Impact corrupted. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 31 Frame synchronization error for VC2 Frame level error for VC2 Frame synchronization error for VC1 Frame level error for VC1 Frame synchronization error for VC0 Frame level error for VC0 MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 32 Frame level error R/W1C Asserted after an FE when the data payload for VC13 received between FS and FE contains errors. The data payload errors are CRC errors. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 33 Frame level error R/W1C Asserted after an FE when the data payload for VC6 received between FS and FE contains errors. The data payload errors are CRC errors. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 34 Description 31–6 Reserved Reserved Detection of Stop state Stop state Active-High signal indicates that the lane module is currently in stop state Reserved Reserved Reserved Reserved Reserved Reserved MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 35 The AXI IIC registers are available when Include IIC is selected in the Vivado IDE. For details about AXI IIC registers, see the AXI IIC Bus Interface v2.0 LogiCORE IP Product Guide (PG090) [Ref MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 36 The MIPI D-PHY registers are available when D-PHY Register Interface is selected in Vivado IDE. For details about MIPI D-PHY registers, see the MIPI D-PHY LogiCORE IP Product Guide (PG202) [Ref MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 37: General Design Guidelines

    Shared Logic provides a flexible architecture that works both as a stand-alone subsystem and as part of a larger design with one of more subsystem instances. This minimizes the MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 38 CSI-2 RX Subsystem. The shared logic comprises a PLL and some BUFGs (maximum of 4). X-Ref Target - Figure 3-1 Figure 3-1: Shared Logic Included in the Subsystem X-Ref Target - Figure 3-2 Figure 3-2: Shared Logic Outside the Subsystem MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 39 MIPI CSI-2 RX Subsystem with shared logic included (MIPI_CSI_SS_Master) to the instance of another MIPI CSI-2 RX Subsystem without shared logic (MIPI_CSI_SS_Slave00 and MIPI_CSI_SS_Slave01) for UltraScale+ devices. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 40 CSI-2 or D-PHY instances in a system. For more information on implementing multiple interfaces in the same HP IO Bank, see UltraScale Architecture SelectIO Resources (UG571) [Ref 16]. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 41 MIPI CSI-2 TX Subsystem need to be configured using Include Shared Logic in Core option under Shared Logic tab. The master and slave can be configured with the different line rate when sharing IMPORTANT: clkoutphy within IO bank. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 42: I/O Planning

    IP cores (csi2_rx_slave1 to csi2_rx_slave7) with different line rates. The master and slave cores can be configured with the different line rate when sharing Note: clkoutphy within IO bank. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 43 For example, HP IO Bank 67 on ZCU102 UltraScale+ device has eight clock capable pins as shown below, which allows eight MIPI CSI-2 RX interfaces to use same HP IO Bank. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 44: Clocking

    Pixels per clock option from Single to Dual or Quad. The MIPI CSI-2 RX Subsystem clocking structure is illustrated in Figure 3-7 Table 3-2. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 45 Core clock = 125*3/4 = 93.75 MHz Pixel Internal pixel clock For 8 bpp clock = core (1)(2) clock clock/(32/8) For 24 bpp clock = core clock /(32/24) MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 46 The following example illustrates this- MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 47: Resets

    Connected to s_axi_aresetn core Connected to m_axis_aresetn core MIPI CSI-2 RX Controller port port Connected to s_axi_aresetn core Inverted signal connected to core_rst MIPI D-PHY port core port MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 48: Protocol Description

    MIPI D-PHY starts with 0x44A1_0000. AXI IIC IP Core Programming See the AXI IIC Bus Interface v2.0 LogiCORE IP Product Guide (PG090) [Ref 5] for AXI IIC IP core programming details. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 49 4. Do not send the new updated lanes traffic until the read from Protocol Configuration registers reflects the new value. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 50 MIPI D-PHY IP Core Programming See the MIPI D-PHY LogiCORE IP Product Guide (PG202) [Ref 3] for MIPI D-PHY IP core programming details. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 51: Customizing And Generating The Subsystem

    [Ref 11] Customizing and Generating the Subsystem This section includes information about using Xilinx tools to customize and generate the subsystem in the Vivado Design Suite. If you are customizing and generating the subsystem in the Vivado IP integrator, see the...
  • Page 52 The Board tab page provides board automation related parameters. The subsystem board configuration screen is shown in Figure 4-1. Board Interface: Select the board parameters. • Custom: Allows user to configure custom values (no board automation support). MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 53: Configuration Tab

    The Configuration tab page provides core related configuration parameters. The subsystem configuration screen is shown in Figure 4-2. X-Ref Target - Figure 4-2 Figure 4-2: Subsystem Customization Screen - Configuration MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 54 MIPI CSI-2 RX IP core. For the rest of MIPI CSI-2 RX cores, this option should be unselected. This option is applicable only for 7 Series MIPI CSI-2 RX IP configurations. Note: MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 55 21. Shared Logic Tab The Shared Logic tab page provides shared logic inclusion parameters. The subsystem shared logic configuration screen is shown in Figure 4-3. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 56 Shared Logic: Select whether the PLL are included in the core or in the example design. Values are: • Include Shared Logic in core • Include Shared Logic in example design MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 57 The Pin Assignment tab page allows to select pins. The subsystem pin assignment configuration screen is shown in Figure 4-4. This tab is not available for Xilinx 7 Series device configurations. Note: X-Ref Target - Figure 4-4 Figure 4-4: Subsystem Customization Screen - Pin Assignment HP IO Bank Selection: Select the HP I/O bank for clock lane and data lane implementation.
  • Page 58 Design Topology: Application example design configuration type. Select MIPI_Video_Pipe_Camera_to_Display to view the flow from camera receive path to display path either on HDMI monitor or MIPI DSI display. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 59 Hidden parameter which can be Note: HS_SETTLE Parameter (ns) C_HS_SETTLE_NS used to set HS_SETTLE value. Can be set through Tcl flow. C_CSI_FILTER_USERDATA Filter User Defined data types False TYPE MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 60: Constraining The Subsystem

    For details about family/device specific line rate support refer UltraScale Architecture SelectIO Resources User Guide (UG571)[Ref 16] . See the respective Xilinx 7 series FPGA family device data sheet for details on the upper line rate limits. Clock Frequencies See Clocking.
  • Page 61 I/O pin LOC for the pins that are selected during IP customization. No I/O pin LOC are provided for Xilinx 7 series FPGA designs. You will have to manually select the clock capable I/O for Xilinx 7 series FPGA RX clock lane and restrict the I/O selection within the I/O bank.

  • Page 62: Simulation

    Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 11]. Synthesis and Implementation For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 63: Application Example Design Overview

    IMX274 image sensor. Processed images are displayed on either the HDMI monitor or MIPI DSI Display. A block diagram of the MIPI CSI-2 Rx Subsystem Application Example Design is shown in Figure 5-1. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 64 You must have the hardware evaluation license for the following IPs to build the complete Note: design: MIPI CSI-2 RX Subsystem ° MIPI DSI TX Subsystem ° HDMI Subsystem ° Test pattern generator ° MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 65: Setup Details

    X-Ref Target - Figure 5-2 Figure 5-2: Connect Ribbon Cable to AUO Display Panel 2. Connect the other end of the ribbon cable to the LI-IMX274MIPI-FMC Camera sensor module. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 66 Switch on the HDMI monitor, and select HDMI as input source. e. Connect USB-UART type A to micro USB cable from the host PC to the UART micro USB port of board. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 67 Connect the USB UART and JTAG programming cables to the Windows host computer where xsdb and hw_server are running. 4. Connect the power supply cable and turn on the ZCU102 board. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 68 Figure 5-5: ZCU 102 Board 5. Start a Hyper Terminal program on the host PC with the following settings: Baud rate: 115200 ° Data Bits: 8 ° Parity: None ° MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 69 2. Go to Imports directory under the Application Example Design project Example: E:/myip/myip_ex/imports: 3. Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx DesignTools > Vivado 2019.1 > Vivado 2019.1 Tcl Shell. 4. Invoke Xilinx System Debugger.

  • Page 70: Implementing The Example Design

    4. In the Project Type page, specify the type of project to create as RTL Project, make sure to uncheck the Do not specify sources at this time option, and click Next. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 71 Figure 5-7: Vivado IDE - Create New Project 8. In the Default Part dialog box, click Boards to specify the board for the target device (ZCU102 supported). Then click Next. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 72 9. Review the New Project Summary page. Verify that the data appears as expected, per the steps above, and click Finish. X-Ref Target - Figure 5-9 Figure 5-9: Vivado IDE - New Project Summary MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 73 ° selected in ‘Application Example Design’ tab. You can rename the IP component name. ° 11. Configure MIPI CSI-2 Rx Subsystem ‘Application Example Design’ tab, then click OK. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 74 Figure 5-11: Vivado IDE - Customize IP The Generate Output Products dialog box appears. Click Generate. You may optionally click Skip if you want to skip generating the output products. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 75 12. Right click on the MIPI CSI-2 Rx Subsystem component under Design source, and click Open IP Example Design. As this step involves the generation of complete system involving multiple subsystems, it Note: would take some time to completely build the design. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 76 Bitstream to validate the design on board or use the IPI system as a reference for camera capture to video display path. Click Generate Output Products option to see the available synthesis options. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 77 Short duration of flickering appears while changing available options such as resolution change from the Application Menu. • Sometimes, MIPI DSI Display goes blank when you switch from HDMI to DSI. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 78: Hardware Validation

    Zynq 7000 ZC702 Xilinx 7 series FPGA devices do not have a native MIPI IOB support. You will have to target either the HR bank I/O or the HP bank I/O for the MIPI IP implementation. For more MIPI CSI-2 RX Subsystem v4.0...
  • Page 79 ON Semi AR0330 490Mb/s 4 Lanes RAW10 720p@60fps xczu9eg-ffvb1156-2-e 1080p@60fps All Xilinx 7 series FPGA interop designs use the external Meticom (MC20901) based solution which implements MIPI D-PHY IO. Table A-3: Interoperability Testing with Xilinx 7 Series FPGA Devices Sensor Board/Device...
  • Page 80 Appendix A: Verification, Compliance, and Interoperability All Xilinx 7 series FPGA loopback designs use the XM107 [Ref 19] loopback card. Table A-4: Loopback Testing with Xilinx 7 Series FPGA Devices Clock Selection Board/Device Line Rate Lanes Calibration Mode (C_EN_CLK300M) AC701/ xc7a200tfbg676-2...

  • Page 81: Finding Help On Xilinx.com

    Answer Records Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

  • Page 82: Debug Tools

    • Summary of the issue encountered A filter search is available after results are returned to further target the results. For the MIPI CSI-2 Receiver Subsystem Master Answer Record see Xilinx Answer 65242. Technical Support Xilinx provides technical support at the...

  • Page 83: Hardware Debug

    Debug instructions: ° Verify MIPI DPHY packet count registers. If the packet counts at MIPI DPHY level are not getting reported, debug connections/paths from source to MIPI DPHY Input MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 84: Interface Debug

    The main subsystem clocks are toggling and that the enables are also asserted. • If the simulation has been run, verify in simulation and/or a debug feature capture that the waveform is correct for accessing the AXI4-Lite interface. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 85 The side band information are optionally sent by the sensor. Please refer to the Low Level Note: Protocol section of MIPI CSI-2 standard v2.0 [Ref 1] for more details. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...
  • Page 86 Appendix B: Debugging Figure B-1: Sideband Information (TUSER) Timing Diagram MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 87: Xilinx Resources

    Support. Documentation Navigator and Design Hubs Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado® IDE, select Help > Documentation and Tutorials.

  • Page 88: References

    16. UltraScale Architecture SelectIO Resources User Guide (UG571) 17. UltraScale Architecture PCB Design User Guide (UG583) 18. LI-IMX274MIPI-FMC product page: LI-IMX274MIPI-FMC 19. FMC XM107 Loopback Card User Guide (UG539) MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019 www.xilinx.com...

  • Page 89: Revision History

    • Video Format Bridge core changes to support RAW8 and User Defined Byte-based Data at all times along with the Vivado IDE selected data type. 11/18/2015 Initial Xilinx release. MIPI CSI-2 RX Subsystem v4.0 Send Feedback PG232 July 02, 2019...

  • Page 90: Please Read: Important Legal Notices

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

Table of Contents

Save PDF