Pioneer HD-V9000 Service Manual page 81

5
QQ
3 7 63 1515 0
GNDD
02
6277
ONTROLLER
TE
L 13942296513
www
.
TP2573
G D C _ S C L K
12F
NDD
5
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C 2 5 4 5
C C G 1 1 9 2 - A
10u/10
GNDD R 2 5 5 9
3 3
1 8
2 7
1 2 8 6
3
M D 1 3
1 2 7
4 5
M D 1 2
R 2 5 5 7 3 3
1 2 6
1 8
M D 1 1
1 2 5
2 7
M D 1 0
1 2 4
3 6
M D 9
1 2 3
4 5
M D 8
R 2 5 6 0 3 3
1 2 2
1 8
M D 7
1 2 1
2 7
M D 6
1 2 0
3 6
M D 5
M D 4 1 1 9
4 5
C 2 5 3 8
1 1 8
V S S 1 2
1 1 7 0 . 1 u / 1 6
R 2 5 6 1
V D D L 1 0
3 3
1 1 6
1 8
M D 3
1 1 5
2 7
M D 2
1 1 4
3 6
M D 1
0 . 1 u / 1 6
1 1 3
4 5
M D 0
1 1 2
V D D H 6
C 2 5 3 9
1 1 1
C L K S E L 1
1 1 0
C L K S E L 0
C 2 5 4 0
1 0 9
V S S 1 1
0 . 1 u / 1 6
1 0 8
V D D L 9
L 2 5 0 2
C T F 1 6 2 9 - A
1 0 7
P L L V D D
1 0 6
S
1 0 5
C L K
1 0 4
V S S 1 0
1 0 3
P L L V S S
1 0 2 13.5MHz
X R S T
1 0 1
C K M
1 0 0
HOST_FLASH_ADRS25
A 2 5
9 9
HOST_FLASH_ADRS24
A 2 4
9 8 C 2 5 4 1 HOST_FLASH_ADRS23
A 2 3
9 7
V D D L 8
0 . 1 u / 1 6
9 6 HOST_FLASH_ADRS22
A 2 2
9 5
HOST_FLASH_ADRS21
A 2 1
9 4
HOST_FLASH_ADRS20
A 2 0
9 3
HOST_FLASH_ADRS19
A 1 9
9 2
HOST_FLASH_ADRS18
A 1 8
9 1
HOST_FLASH_ADRS17
A 1 7
9 0
HOST_FLASH_ADRS16
A 1 6
8 9
V S S 9
C 2 5 4 2
8 8 HOST_FLASH_ADRS15
A 1 5
8 7
V D D L 7
0 . 1 u / 1 6
8 6 HOST_FLASH_ADRS14
A 1 4
8 5
HOST_FLASH_ADRS13
A 1 3
8 4
HOST_FLASH_ADRS12
A 1 2
8 3 C 2 5 4 3
HOST_FLASH_ADRS11
A 1 1
8 2
V D D H 5
0 . 1 u / 1 6
8 1
HOST_FLASH_ADRS10
A 1 0
8 0
HOST_FLASH_ADRS9
A 9
7 9
HOST_FLASH_ADRS8
A 8
7 8 HOST_FLASH_ADRS7
A 7
7 7 HOST_FLASH_ADRS6
A 6
7 6
V D D L 6
C 2 5 4 4
7 5
V S S 8
0 . 1 u / 1 6
7 4
HOST_FLASH_ADRS5
A 5
7 3
HOST_FLASH_ADRS4
A 4
7 2
HOST_FLASH_ADRS3
A 3
7 1
HOST_FLASH_ADRS2
A 2
7 0 TP2595
D R A C K
6 9 TP2596
D T A C K
6 8
X W E 3
6 7
X W E 2
6 6
X W E 1
6 5
X W E 0
GNDD
GNDD
NOTES
NM is Standby
RS1/16SS***J
x ao u163
CKSSYB***K F/V
y
(CH) CCSSCH***J F/V
(SR) CKSRYB***K F/V
RAB4CQ***J
i
6
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8
A
7/18
DECM SERVICE ASSY (DXX2610)
• GDC BLOCK
MINT SDRAM BUS
TP2597
GDC_DATA_MD15
TP2598
GDC_DATA_MD14
TP2599
GDC_DATA_MD13
GDC_DATA_MD0
TP2600
GDC_DATA_MD12
GDC_DATA_MD1
TP2601
GDC_DATA_MD11
GDC_DATA_MD2
TP2602
GDC_DATA_MD10
GDC_DATA_MD3
TP2603
GDC_DATA_MD9
TP2604
GDC_DATA_MD8
TP2605
GDC_DATA_MD7
GDC_DATA_MD4
TP2606
GDC_DATA_MD6
GDC_DATA_MD5
TP2607
GDC_DATA_MD5
GDC_DATA_MD6
TP2608
GDC_DATA_MD4
GDC_DATA_MD7
TP2609
GDC_DATA_MD3
GDC_DQM0
TP2610
V+3R3D_GDC
GDC_DATA_MD2
GDC_MWE
TP2611
GDC_DATA_MD1
GDC_MCAS
TP2612
GDC_DATA_MD0
GDC_MRAS
TP2632
GDC_ADRS_MA12
TP2633
GDC_ADRS_MA13
TP2634
GDC_ADRS_MA10
V+1R8D_GDC
R 2 5 6 3
GDC_ADRS_MA0
0
GDC_ADRS_MA1
GNDD
GDC_ADRS_MA2
CKM Clock mode
GDC_ADRS_MA3
L: Output from internal
PLL selected
H: Host CPU bus clock selected
GNDD
INPUT CLK = 13.5MHz
CLKSEL1 : L
CLKSEL0 : L
G D C _ S C L K
8L
G D C _ S
15I
G D C _ X R S T
15I
GNDD
Q Q
3 6 7 1 3 1 5
GDC_DATA_MD16
GDC_DATA_MD17
GDC_DATA_MD18
GDC_DATA_MD19
GDC_DATA_MD20
GDC_DATA_MD21
GDC_DATA_MD22
GDC_DATA_MD23
GDC_DQM2
GDC_MWE
GDC_MCAS
GDC_MRAS
GDC_ADRS_MA12
GDC_ADRS_MA13
GDC_ADRS_MA10
GDC_ADRS_MA0
GDC_ADRS_MA1
GDC_ADRS_MA2
R 2 5 6 9 N M
GDC_ADRS_MA3
R 2 5 7 0 N M
R 2 5 7 3 N M
R 2 5 7 1 N M
HOST_R/#W
# R E S E T _ M I N T _ X R S T
A 1/18
1:10L
# R E S E T _ M I N T _ S
1:10L
co
.
HD-V9000
7
9 4 2 8
V+3R3D_GDC
C 2 5 6 3
CCG1192-A-T
10u/10
C 2 5 5 2
I C 2 5 0 4
1 u / 1 0 (SR)
1 54
V D D 1 VSS3
2 53
C 2 5 5 3
D Q 0 DQ15
R 2 5 9 4
52
8 3
1
V D D Q 1 VSSQ4
0 . 1 u / 1 6
51
4
2 7
DQ14
D Q 1
50
5
3 6 C 2 5 6 6
D Q 2 DQ13
6 49
4 5
V S S Q 1 VDDQ4
0 . 1 u / 1 6
7 4 8
5 6
D Q 3 D Q 1 2
8 4 7
R 2 5 9 5 D Q 4 D Q 1 1
9 4 6
1 8
V D D Q 2 V S S Q 3
C 2 5 5 4
1 0 4 5
2 7 0 . 1 u / 1 6
D Q 5 D Q 1 0
1 1 4 4
3 6 C 2 5 6 7
D Q 6 D Q 9
1 2 4 3
5
4
V S S Q 2 V D D Q 3
0 . 1 u / 1 6
C 2 5 5 5 1 3 4 2
5 6
D Q 7 D Q 8
1 4 4 1
V D D 2 V S S 2
1 u / 1 0 (SR)
1 5 4 0
TP2615
L D Q M N C 2
1 6 3 9
W E U D Q M
R 2 5 5 1 0
1 7 3 8
100MHz
C A S C L K
1 8 3 7
GDC_CKE
R A S C K E
1 9 3 6
TP2616
C S N C 1
2 0 3 5
B A 0 A 1 1
2 1 3 4
B A 1 A 9
2 2 3 3
A 1 0 / A P A 8
2 3 3 2
A 0 A 7
2 4 3 1
A 1 A 6
2 5 3 0
A 2 A 5
2 6 2 9
A 3 A 4
2 7
2 8
V D D 3 V S S 1
C 2 5 5 6
H Y 5 7 V 2 8 1 6 2 0 F T P - H
1 u / 1 0 (SR)
(128Mb SDRAM)
SDRAM (LOWER)
GNDD
V+3R3D_GDC
C 2 5 6 4
CCG1192-A-T
10u/10
C 2 5 5 7
I C 2 5 0 5
1 u / 1 0 (SR)
1 54
V D D 1 VSS3
0 5 8 2 9 9 4
2 53
C 2 5 5 8
R 2 5 9 8 D Q 0 DQ15
3 52
1 8
V D D Q 1 VSSQ4
0 . 1 u / 1 6
4 51
2 7
D Q 1 DQ14
50
6 5 C 2 5 6 8
3
D Q 2 DQ13
49
6
4 5
V S S Q 1 VDDQ4
0 . 1 u / 1 6
7 4 8
5 6
D Q 3 D Q 1 2
C 2 5 5 9 8 4 7
R 2 5 9 9 D Q 4 D Q 1 1
9 4 6
1 8
V D D Q 2 V S S Q 3
0 . 1 u / 1 6
1 0 4 5
2 7
D Q 5 D Q 1 0
1 1 4 4
3 6 C 2 5 6 9
D Q 6 D Q 9
1 2 4 3
4 5
V S S Q 2 V D D Q 3
0 . 1 u / 1 6
1 3 4 2
C 2 5 6 0
5 6
D Q 7 D Q 8
1 4 4 1
V D D 2 V S S 2
1 u / 1 0 (SR)
1 5 4 0
TP2617
L D Q M N C 2
1 6 3 9
W E U D Q M
R 2 5 5 0 0
1 7 3 8 100MHz
C A S C L K
1 8 3 7
GDC_CKE
R A S C K E
1 9 3 6
TP2618
C S N C 1
2 0 3 5
B A 0 A 1 1
2 1 3 4
B A 1 A 9
2 2 3 3
A 1 0 / A P A 8
2 3 3 2
A 0 A 7
2 4 3 1
A 1 A 6
2 5 3 0
A 2 A 5
2 6 2 9
A 3 A 4
2 7 2 8
V D D 3 V S S 1
C 2 5 6 1
H Y 5 7 V 2 8 1 6 2 0 F T P - H
1 u / 1 0 (SR)
(128Mb SDRAM)
SDRAM (UPPER)
GNDD
R 2 5 8 0
3 3
R 2 5 8 1
3 3 UNUSED
V+3R3D_GDC
C 2 5 6 5
N M
TP2619
IC2506
NM
TP2613
1 8
R 2 5 8 2 R 2 5 8 3
N C 0 N C 2
N M N M
2 7
I N 1 V C C
3 6
N C 1 R S T O U T
4 5
G N D 0 C d
GNDD
m
7
8
9 9
A
R 2 5 8 5
4 . 7 k
GDC_CKE
R 2 5 9 7
8 GDC_DATA_MD15
1
GDC_DATA_MD14
2 7
B
GDC_DATA_MD13
3 6
4 5 GDC_DATA_MD12
5 6
R 2 5 9 6
1 8 GDC_DATA_MD11
2 7 GDC_DATA_MD10
3 6 GDC_DATA_MD9
5 GDC_DATA_MD8
4
5 6
GDC_DQM1
GDC_MCLKOI
GDC_ADRS_MA11
GDC_ADRS_MA9
GNDD
GDC_ADRS_MA8
GDC_ADRS_MA7
GDC_ADRS_MA6
GDC_ADRS_MA5
GDC_ADRS_MA4
C
2 8 9 9
R 2 6 0 1
1 8 GDC_DATA_MD31
2 7 GDC_DATA_MD30
6 GDC_DATA_MD29
3
GDC_DATA_MD28
4 5
5 6
R 2 6 0 0
1 8 GDC_DATA_MD27
2 7 GDC_DATA_MD26
3 6 GDC_DATA_MD25
4 5 GDC_DATA_MD24
5 6
GDC_DQM3
D
GDC_MCLKOI
GDC_ADRS_MA11
GDC_ADRS_MA9
GNDD
GDC_ADRS_MA8
GDC_ADRS_MA7
GDC_ADRS_MA6
GDC_ADRS_MA5
GDC_ADRS_MA4
TP2620
G D C _ X R S T
12F
TP2621
G D C _ S
12F
R 2 5 8 7
N M
E
F
A
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