Power On Reset (Por) / Power Down Reset (Pdr); Figure 8. Pdr_On Timings Example - ST STM32F4 Series Application Note

AN4488
Figure 8. PDR_ON timings example (not to scale, (not needed for STM32F410xx,
STM32F411xx, STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx,
Selection of PDR_ON voltage supervisor
Voltage supervisor should have the following characteristics
•
Reset output active-high push-pull (output driving high when voltage is below trip
point)
•
Supervisor trip point including tolerances and hysteresis should fit the expected V
range.
Notice that supervisor spec usually specify trip point for falling supply, so hysteresis
should be added to check the power on phase.
Example:
–
–
3.2.2

Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from
1.8 V.
The device remains in the Reset mode as long as V
V
POR/PDR
STM32F469xx and STM32F479xx)
Voltage regulator 1.8V +/- 5% mean V
Supervisor specified at 1.66V +/- 2.5% with an hysteresis of 0.5% mean
- rising trip max = 1.71V (1.66V + 2.5% + 0.5%)
- falling trip min = 1.62V (1.66V - 2.5%).
, without the need for an external reset circuit. For more details concerning the
Reset and power supply supervisor
min1.71V
DD
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AN4488 Rev 7
is below a specified threshold,
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