ST STM32F4 Series Application Note
  1. Manuals
  2. Brands
  3. ST Manuals
  4. Motherboard
  5. STM32F4 Series
  6. Application note

ST STM32F4 Series Application Note

Getting started with mcu hardware development
Hide thumbs Also See for STM32F4 Series:
Table of Contents

Advertisement

Quick Links

See also: Programming Manual
Getting started with STM32F4xxxx MCU hardware development
Introduction
This application note is intended for system designers who require an overview of the
hardware implementation of the development board, with focus on features like
• power supply
• package selection
• clock management
• reset control
• boot mode settings
• debug management.
This document shows how to use the high-density high-performance microcontrollers listed
in
Table
1, and describes the minimum hardware resources required to develop an
application based on those products.
Detailed reference design schematics are also contained in this document, together with
descriptions of the main components, interfaces and modes.
Microcontrollers
October 2018
Table 1. Applicable products
Type
Part numbers and Product lines
STM32F401xB / STM32F401xC
STM32F401xD / STM32F401xE
STM32F405/415 line
STM32F407/417 line
STM32F410x8 / STM32F410xB
STM32F411xC / STM32F411xE
STM32F412xE / STM32F412xG
STM32F413/423 line
STM32F427/437 line
STM32F429/439 line
STM32F446 line
STM32F469/479 line
AN4488 Rev 7
AN4488
Application note
1/50
www.st.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32F4 Series and is the answer not in the manual?

Questions and answers

Related Manuals for ST STM32F4 Series

Summary of Contents for ST STM32F4 Series

  • Page 1 Part numbers and Product lines STM32F401xB / STM32F401xC STM32F401xD / STM32F401xE STM32F405/415 line STM32F407/417 line STM32F410x8 / STM32F410xB STM32F411xC / STM32F411xE Microcontrollers STM32F412xE / STM32F412xG STM32F413/423 line STM32F427/437 line STM32F429/439 line STM32F446 line STM32F469/479 line October 2018 AN4488 Rev 7 1/50 www.st.com...

  • Page 2: Table Of Contents

    Contents AN4488 Contents Reference documents ........6 Power supplies .
  • Page 3 AN4488 Contents 5.2.3 SWJ debug port connection with standard JTAG connector ..30 Clocks ........... . 32 HSE OSC clock .
  • Page 4 List of tables AN4488 List of tables Table 1. Applicable products ............1 Table 2.
  • Page 5 STM32 ST-LINK Utility ........

  • Page 6: Reference Documents

    The following documents are available on www.st.com. Table 2. Referenced documents Reference Title AN2867 Oscillator design guide for ST microcontrollers AN2606 STM32 microcontroller system memory boot mode AN3364 Migration and compatibility guidelines for STM32 microcontroller applications ®(a) This document applies to Arm -based devices.

  • Page 7: Power Supplies

    AN4488 Power supplies Power supplies The operating voltage supply (V ) range is 1.8 V to 3.6 V, which can be reduced down to 1.7 V with some restrictions, as detailed in the product datasheets. An embedded regulator is used to supply the internal 1.2 V digital power. The real-time clock (RTC), backup registers and backup registers can be powered from the voltage when the main V supply is powered off.

  • Page 8: Figure 1. Bypass_Reg Supervisor Reset Connection

    Power supplies AN4488 PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. • In regulator OFF mode, the following features are no more supported: – PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin.

  • Page 9: Power Supply Schemes

    AN4488 Power supplies Power supply schemes The circuit is powered by a stabilized power supply, V Caution: The V voltage range is 1.8 V to 3.6 V (down to 1.7 V with some restrictions, see relative Datasheet for details). • The V pins must be connected to V with external decoupling capacitors: one...

  • Page 10: Figure 2. Power Supply Scheme (Excluding Stm32F469Xx/F479Xx)

    Power supplies AN4488 Figure 2. (excluding STM32F469xx/F479xx) Power supply scheme 1. Optional. If a separate, external reference voltage is connected on V , the two capacitors (100 nF and REF+ 1 µF) must be connected. 2. V is not available on all packages. In that case, a single 4.7 µF (ESR < 1Ω) is connected to V CAP2 CAP1 3.

  • Page 11: Figure 3. Power Supply Scheme For Stm32F469Xx/F479Xx

    AN4488 Power supplies Figure 3. Power supply scheme for STM32F469xx/F479xx 1. Optional. If a separate, external reference voltage is connected on V , the two capacitors (100 nF and REF+ 1 µF) must be connected. 2. V is either connected to V or to V (depending on package).

  • Page 12: Analog Supply

    Power supplies AN4488 Analog Supply To improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB. • The ADC voltage supply input is available on V pin. • An isolated supply ground connection is provided on the V pin.

  • Page 13: Reset And Power Supply Supervisor

    AN4488 Reset and power supply supervisor Reset and power supply supervisor System reset A system reset sets all registers to their reset values except for the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure A system reset is generated when one of the following events occurs: A low level on the NRST pin (external reset)

  • Page 14: Figure 5. Nrst Circuitry Example

    Reset and power supply supervisor AN4488 internal circuitry (no additional component needed, thanks to fully embedded reset controller). • When the internal reset is OFF, the following integrated features are no longer supported: – The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.

  • Page 15: Power Supply Supervisor

    AN4488 Reset and power supply supervisor Figure 6. NRST circuitry timings example (not to scale, only for STM32F410xx, STM32F411xx, STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx, STM32F469xx and STM32F479xx) Selection of NRST voltage supervisor Voltage supervisor should have the following characteristics • Reset output active-low open-drain (output driving low when voltage is below trip point).

  • Page 16: Figure 7. Pdr_On Simple Circuitry Example

    Reset and power supply supervisor AN4488 Note: Please contact your local STMicroelectronics representative or visit www.st.com in case you want to use circuitry different from the one described hereafter. Restrictions: • PDR_ON = 0 is mostly intended for V supply between 1.7 V and 1.9V (i.e. 1.8V +/- 5% supply).

  • Page 17: Power On Reset (Por) / Power Down Reset (Pdr)

    AN4488 Reset and power supply supervisor Figure 8. PDR_ON timings example (not to scale, (not needed for STM32F410xx, STM32F411xx, STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx, STM32F469xx and STM32F479xx) Selection of PDR_ON voltage supervisor Voltage supervisor should have the following characteristics • Reset output active-high push-pull (output driving high when voltage is below trip point) •...

  • Page 18: Programmable Voltage Detector (Pvd)

    Reset and power supply supervisor AN4488 power on/power down reset threshold, refer to the electrical characteristics in the product datasheets. Figure 9. Power-on reset/power-down reset waveform 1. t is approximately 2.6 ms. V rising edge is 1.74 V (typ.) and V falling edge is RSTTEMPO POR/PDR...

  • Page 19: Figure 10. Pvd Thresholds

    AN4488 Reset and power supply supervisor Figure 10. PVD thresholds AN4488 Rev 7 19/50...

  • Page 20: Package

    Package AN4488 Package Package Selection Package should be selected by taking into account the constrains that are strongly dependent upon the application. The list below summarizes the more frequent ones: – Amount of interfaces required. Some interfaces might not be available on some packages. Some interfaces combinations could not be possible on some packages.
  • Page 21 AN4488 Package Table 3. Package summary (continued) Size (mm) Sales numbers STM32F437xx/439xx STM32F446XX STM32F469xx STM32F479xx 1. body size, excluding pins AN4488 Rev 7 21/50...

  • Page 22: Pinout Compatibility

    Package AN4488 Pinout Compatibility 4.2.1 I/O speed • When using the GPIO as I/O, design considerations have to be taken into account to ensure that the operation is as intended. • When the load capacitance becomes larger, the rise/fall time of the I/O pin increases. This capacitance includes the effects of the board traces.
  • Page 23 AN4488 Package (1)(2) Table 4. I/O AC characteristics (continued) OSPEEDR y[1:0] bit Symbol Parameter Conditions Unit value = 40 pF, V ≥ 2.7 V = 10 pF, V ≥ 2.7 V Maximum frequency = 40 pF, V ≥ 1.7 V max(IO)out = 10 pF, V ≥...

  • Page 24: Alternate Function

    CH2N _RTS HS_DM SPI2_ RTC_ TIM1_ TIM8_ TIM12_C OTG_H EVENT PB15 MOSI/ REFIN CH3N CH3N S_DP ‘OUT I2S2_SD In order to easily explore Peripheral Alternate Functions mapping to pins, it is recommended to use the STM32CubeMX tool available on www.st.com.

  • Page 25: Handling Unused Pins

    AN4488 Package Figure 11. STM32CubeMX example screen-shot 4.3.1 Handling unused pins All microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase EMC performance, unused clocks, counters or I/Os, should not be left free, e.g. I/Os should be set to “0”...

  • Page 26: Table 6. Boot Modes

    Package AN4488 Table 6. Boot modes BOOT mode selection pins Boot mode Aliasing BOOT1 BOOT0 Main Flash memory Main Flash memory is selected as boot space System memory System memory is selected as boot space Embedded SRAM Embedded SRAM is selected as boot space The values on the BOOT pins are latched on the 4 rising edge of SYSCLK after a reset.

  • Page 27: Boot Pin Connection

    1. Resistor values are given only as a typical example. Embedded boot loader mode The embedded boot loader is located in the System memory and is programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces.
  • Page 28 Package AN4488 Table 7. STM32F4xxxx bootloader communication peripherals (continued) STM32F405/415 STM32F412xx/ Bootloader STM32F401xB/C STM32F407/417 STM32F411xC/ STM32F469xx/ STM32F410xx STM32F413xx/ peripherals STM32F401xD/E STM32F427/437 STM32F411xE STM32F479xx STM32F423xx STM32F429/439 PA15/PC10/ PA15/PC10/ PA15/PC10/ SPI3 PC11/PC12 PC11/PC12 PC11/PC12 PE11/PE12/ SPI4 PE13/PE14 For additional information, refer to AN2606 (Table 28/50 AN4488 Rev 7...

  • Page 29: Debug Management

    AN4488 Debug management Debug management The Host/Target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool. Figure 13 shows the connection of the host to the evaluation board.

  • Page 30: Internal Pull-Up And Pull-Down Resistors On Jtag Pins

    Debug management AN4488 Table 8. Debug port pin assignment JTAG debug port SW debug port SWJ-DP pin name assignmen Type Description Type Debug assignment JTAG test mode Serial wire data JTMS/SWDIO PA13 selection input/output JTCK/SWCLK JTAG test clock Serial wire clock PA14 JTDI JTAG test data input...

  • Page 31: Figure 14. Jtag Connector Implementation

    AN4488 Debug management Figure 14. JTAG connector implementation AN4488 Rev 7 31/50...

  • Page 32: Clocks

    Typical value is in the range of 5 to 6 R (resonator series resistance). Refer to the dedicated Application Note (AN2867 - Oscillator design guide for ST microcontrollers) and electrical characteristics sections in the datasheet of your product for more details.

  • Page 33: Lse Osc Clock

    A 0 Ω resistor would work but would not be The value of R optimal. To fine tube R value, refer to AN2867 - Oscillator design guide for ST microcontrollers (Table and electrical characteristics sections in the datasheet of your product for more details.

  • Page 34: Reference Design

    Reference design Figure 19. Reference schematic <[ W \ X : S: &$  7 < = U < 7  O >AU7 7 < =: S$ $ AR S++T =<U 7 < =/ S$ $  D 7  S++ & 7 <: B/...

  • Page 35: Figure 20. Bill Of Material

    Figure 20. Bill of Material Comment Description Designator Footprint Quantity TD-0341 [RESET/Black] SE PUSHBUTTON PB10 CR1220 holder Battery BAT_2SM_CR1220 C1, C2, C3, C4, C5, C6, C7, C8, C9, C13, C14, C15, C16, C17, C18, C19, C20, C21, 100nF Capacitor C22, C23, C25, C30 0402C 4.7uF Polarized Capacitor (Radial) C10, C11...

  • Page 36: Recommended Pcb Routing Guidelines For Stm32F4Xxxx Devices

    Recommended PCB routing guidelines for STM32F4xxxx devices AN4488 Recommended PCB routing guidelines for STM32F4xxxx devices PCB stack-up In order to reduce the reflections on high speed signals, it is necessary to match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes.

  • Page 37: Crystal Oscillator

    AN4488 Recommended PCB routing guidelines for STM32F4xxxx devices Figure 22. Six layer PCB stack-up example Crystal oscillator Use the application note: Oscillator design guide for STM8S, STM8A and STM32 microcontrollers (AN2867), for further guidance on how to layout and route crystal oscillator circuits.

  • Page 38: High Speed Signal Layout

    Recommended PCB routing guidelines for STM32F4xxxx devices AN4488 Figure 23. Typical layout for V pair High speed signal layout 8.4.1 SDMMC bus interface Interface connectivity The SD/SDIO MMC card host interface (SDMMC) provides an interface between the APB2 peripheral bus and Multi Media Cards (MMCs), SD memory cards and SDIO cards. The SDMMC interface is a serial data bus interface, that consists of a clock (CK), command signal (CMD) and 8 data lines (D [0:7]).

  • Page 39: Flexible Memory Controller (Fmc) Interface

    AN4488 Recommended PCB routing guidelines for STM32F4xxxx devices 8.4.2 Flexible memory controller (FMC) interface Interface connectivity The FMC controller and in particular SDRAM memory controller which has many signals, most of them have a similar functionality and work together. The controller I/O signals could be split in four groups as follow: •...

  • Page 40: Embedded Trace Macrocell (Etm)

    Recommended PCB routing guidelines for STM32F4xxxx devices AN4488 FLASH memories. The QUAD SPI interface is a serial data bus interface, that consists of a clock (SCLK), a chip select signal (nCS) and 4 data lines (IO[0:3]). Interface signal layout guidelines •...

  • Page 41: Package Layout Recommendation

    AN4488 Recommended PCB routing guidelines for STM32F4xxxx devices Package layout recommendation 8.5.1 BGA 216 0.8 mm pitch design example Table 9. BGA 216 0.8 mm pitch package information Package information (mm) Design parameters (mm) Ball pitch : 0.8 Via size : hole size ∅= 0.2, pad size: 0.45, plane clearance: 0.65 Ball size : 0.4 Trace width : 0.10/0.125 Number of rows/columns : 15x15...

  • Page 42: Wlcsp143 0.4 Mm Pitch Design Example

    Recommended PCB routing guidelines for STM32F4xxxx devices AN4488 Figure 25. Via fan-out Figure 26. FMC signal fan-out routing example 8.5.2 WLCSP143 0.4 mm pitch design example Table 10. Wafer level chip scale package information Package information (mm) Design parameters (mm) Microvia size : hole size ∅= 0.1, via land: 0.2 Bump pitch : 0.4 Bump size : 0.25...
  • Page 43 AN4488 Recommended PCB routing guidelines for STM32F4xxxx devices A better way to route this package and the fan-out signals is to use a through microvia technology. Microvia will route out internal bumps to a buried layers inside the PCB. To achieve this, the WLCSP package pads have to be connected to this internal layer through microvia.

  • Page 44: Figure 27. 143-Bumps Wlcsp, 0.40 Mm Pitch Routing Example

    Recommended PCB routing guidelines for STM32F4xxxx devices AN4488 Figure 27. 143-bumps WLCSP, 0.40 mm pitch routing example 44/50 AN4488 Rev 7...

  • Page 45: Faq

    In order to identify the STM32F4 refer to section “Part numbering” in your product datasheet. To get the MCU’s ID you can use ST-LINK Utility, once connected, the tool identify the target, and shows the ID, sub family, revision and flash size of the device as shown below.

  • Page 46: Where To Find Ibis Models

    Verify the GND coupling. • Monitor OSC_OUT with oscillator to verify if it is working properly. OSC_OUT • Refer to the AN2867: Oscillator design guide for ST microcontrollers. • Check if RESET pin is correctly driven. RESET pin • NRST connection includes a 100nF capacitor to ground.

  • Page 47: Conclusion

    AN4488 Conclusion Conclusion This application note should be used as a starting reference for a new design with STM32F4xxxx device. AN4488 Rev 7 47/50...

  • Page 48: Revision History

    Revision history AN4488 Revision history Table 12. Document revision history Date Revision Changes 20-Jun-2014 Initial release. Added STM32F411xC/xE in Table 1 Added footnote in Table 3 Updated Table 5 Table 11 28-Oct-2014 Updated Figure Figure 7 Figure 8 Updated Section 3.2.1 Added Section 2.3.5 for STM32F411xC/xE...

  • Page 49: Table 1. Applicable Products

    STM32F4xxxx devices – Section 9: FAQ 07-Oct-2016 – Figure 19: Reference schematic – Figure 20: Bill of Material – Figure 28: STM32 ST-LINK Utility Updated: – Section 7: Reference design Added: STM32F413/423 line Updated: 5-Dec-2016 – Table 1: Applicable products –...
  • Page 50 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

This manual is also suitable for:

Stm32f401xd seriesStm32f401xc seriesStm32f401xb seriesStm32f401xe seriesStm32f405 seriesStm32f415 series ... Show all

Table of Contents

Save PDF