L
K
J
CPU CIRCUIT DIAGRAM (DME4io-ES/DME8i-ES/DME8o-ES) 002
1
2
3
4
5
SYSTEM RESET
6
Detection voltage: 3.0 V
(検出電圧 3.0 V)
7
8
16
28CC1-2001004394-2 2
I
H
G
CPLD
AND GATE
INVERTER
AND GATE
F
E
D
: Not installed (未実装)
XX
: Ceramic Capacitor
for CPLD
bypass capacitors
CPU CIRCUIT DIAGRAM (DME4io-ES/DME8i-ES/DME8o-ES) 002
C
B
A
DME4io-ES/DME8i-ES/DME8o-ES
REAL TIME CLOCK
AND
(セラミックコンデンサー)