National Instruments NI sbRIO-9627 Specification page 5

RMC SD via FPGA DIO Throughput
Read
Write
Note
RMC SD has slower throughputs as the Xilinx Zynq-7000 requires SD
interfaces through the FPGA to operate at standard speed rather than at high speed.
3.3 V Digital I/O on RMC Connector
Number of DIO channels
Maximum tested current per channel
Note
The performance of the RMC DIO pins is bounded by the FPGA, signal
integrity, the application timing requirements, and the RMC design. A general SPI
application will typically be able to meet these requirements and achieve frequencies
of up to 10 MHz. For more information on using DIO to connect to RMCs, visit
ni.com/info
Input logic levels
Input low voltage, V
Input high voltage, V
Output logic levels
Output high voltage, V
when sourcing 3 mA
Output low voltage, V
when sinking 3 mA
3.3 V Digital I/O on 50-Pin IDC Connector
Number of DIO channels
Maximum tested current per channel
Input logic levels
Input low voltage, V
Input high voltage, V
and enter the Info Code
IL
IH
OH
OL
IL
IH
8.0 MB/s maximum
6.5 MB/s maximum
96
±3 mA
.
RMCDIO
-0.3 V minimum; 0.8 V maximum
2.0 V minimum; 3.45 V maximum
2.4 V minimum; 3.45 V maximum
0.0 V minimum; 0.4 V maximum
4
±3 mA
-0.3 V minimum; 0.8 V maximum
2.0 V minimum; 5.25 V maximum
NI sbRIO-9627 Specifications | © National Instruments | 5