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Samsung MUXONENAND A-DIE KFN4G16Q2A Specification

2gb muxonenand a-die flash memory
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MuxOneNAND2G(KFM2G16Q2A-DEBx)
MuxOneNAND4G(KFN4G16Q2A-DEBx)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
MuxOneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be
claimed as the property of their rightful owners.
KFM2G16Q2A
KFN4G16Q2A
2Gb MuxOneNAND A-die
- 1 -
FLASH MEMORY

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Summary of Contents for Samsung MUXONENAND A-DIE KFN4G16Q2A

  • Page 1 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

  • Page 2: Flash Memory

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Revision History Document Title MuxOneNAND Revision History Revision No. 1. Initial issue. 1. Corrected errata. 2. Chapter 3.3.1 Cold Reset Mode Operation revised. 3. Chapter 6.17 Cold Reset Timing revised. 4. Chapter 5.9 AC Characteristics for Load/Program/Erase Performance revised.
  • Page 3 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Revision No. History Draft Date Remark 1. Corrected errata. Dec. 16, 2008 Final 2. Chapter 2.8.18 Command Register F220h (R/W) revised. 3. Chapter 3.4.3 NAND Array Write Protection states revised. 4. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection State revised. - 3 -...
  • Page 4 Samsung offers a variety of Flash solutions including NAND Flash, MuxOneNAND component and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia. To determine which Samsung Flash product solution is best for your application, refer the product selector chart. Application Requires...

  • Page 5: Ordering Information

    Phones, Camera Phones, and mobile applications that have large, advanced multimedia applications and operating systems, but lack a NAND controller. When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance, small footprint solution. FLASH MEMORY...

  • Page 6: Product Features

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 1.4 Product Features Device Architecture • Design Technology: • Supply Voltage: • Host Interface: • 5KB Internal BufferRAM: • SLC NAND Array: Device Performance • Host Interface Type: • Programmable Burst Read Latency: • Multiple Sector Read/Write: • Multiple Reset Modes: •...

  • Page 7: General Overview

    The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any ques- tions, please contact the SAMSUNG branch office near you.

  • Page 8: Device Description

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.0 DEVICE DESCRIPTION 2.1 Detailed Product Description The MuxOneNAND is an advanced generation, high-performance NAND-based Flash memory. It integrates on-chip a single-level-cell (SLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page buffer for the Flash array, and a one-time-programmable block.
  • Page 9 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.3 Pin Configuration 2.3.1 2Gb Product (KFM2G16Q2A) 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA ADQ1 ADQ2 ADQ3 ADQ7 ADQ14 ADQ6 Core ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 ADQ0 ADQ15 ADQ10 ADQ9 ADQ13 (TOP VIEW, Balls Facing Down) 63ball FBGA MuxOneNAND Chip - 9 - FLASH MEMORY...
  • Page 10 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.3.2 4Gb Product (KFN4G16Q2A) 63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA ADQ1 ADQ2 ADQ3 ADQ7 ADQ14 ADQ6 Core ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 ADQ0 ADQ15 ADQ10 ADQ9 ADQ13 (TOP VIEW, Balls Facing Down) 63ball FBGA MuxOneNAND Chip - 10 - FLASH MEMORY...

  • Page 11: Pin Description

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.4 Pin Description Pin Name Type Host Interface Multiplexed Address/Data bus - Inputs for addresses during read operation, which are for addressing BufferRAM & Register. ADQ15~ADQ0 - Inputs data during program and commands for all operations, outputs data during memory array/ register read cycles.

  • Page 12: Block Diagram

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.5 Block Diagram BufferRAM ADQ15~ADQ0 BootRAM DataRAM0 DataRAM1 (Address/Command/Configuration 2.6 Memory Array Organization The MuxOneNAND architecture integrates several memory areas on a single chip. 2.6.1 Internal (NAND Array) Memory Organization The on-chip internal memory is a single-level-cell (SLC) NAND array used for data storage and code. The internal memory is divided into a main area and a spare area.
  • Page 13 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Internal Memory Array Information Area Main Spare Internal Memory Array Organization 512B Sector0 512B Sector1 Block Page 128KB Sector Main Area 512B Page Main Area 512B Sector2 512B Sector3 16B Sector0 16B Sector1 16B Sector2 16B Sector3 Block Main Area 2KB Page0 2KB Page63...
  • Page 14 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.6.2 External (BufferRAM) Memory Organization The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering. The BootRAM is a 1KB buffer that receives Boot Code from the internal memory and makes it available to the host at start up. There are two independent 2KB bi-directional data buffers, DataRAM0 and DataRAM1.
  • Page 15 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) External Memory Array Organization BootRAM DataRAM0 DataRAM1 Main area data Spare area data (16B) (512B) BootRAM 0 Sector: (512 + 16) Byte BootRAM 1 DataRAM 0_0 DataRAM 0_1 DataRAM 0_2 DataRAM 0_3 DataRAM 1_0 DataRAM 1_1 DataRAM 1_2 DataRAM 1_3 - 15 - FLASH MEMORY...
  • Page 16 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7 Memory Map The following tables are the memory maps for the MuxOneNAND. 2.7.1 Internal (NAND Array) Memory Organization The following tables show the Internal Memory address map in word order. Page and Sector Block Block Address Address Block0 0000h 0000h~00FFh...
  • Page 17 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block64 0040h 0000h~00FFh Block65 0041h 0000h~00FFh Block66 0042h 0000h~00FFh Block67 0043h 0000h~00FFh Block68 0044h 0000h~00FFh Block69 0045h 0000h~00FFh Block70 0046h 0000h~00FFh Block71 0047h 0000h~00FFh Block72 0048h 0000h~00FFh Block73 0049h 0000h~00FFh Block74 004Ah 0000h~00FFh Block75...
  • Page 18 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block128 0080h 0000h~00FFh Block129 0081h 0000h~00FFh Block130 0082h 0000h~00FFh Block131 0083h 0000h~00FFh Block132 0084h 0000h~00FFh Block133 0085h 0000h~00FFh Block134 0086h 0000h~00FFh Block135 0087h 0000h~00FFh Block136 0088h 0000h~00FFh Block137 0089h 0000h~00FFh Block138 008Ah 0000h~00FFh Block139...
  • Page 19 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block192 00C0h 0000h~00FFh Block193 00C1h 0000h~00FFh Block194 00C2h 0000h~00FFh Block195 00C3h 0000h~00FFh Block196 00C4h 0000h~00FFh Block197 00C5h 0000h~00FFh Block198 00C6h 0000h~00FFh Block199 00C7h 0000h~00FFh Block200 00C8h 0000h~00FFh Block201 00C9h 0000h~00FFh Block202 00CAh 0000h~00FFh Block203...
  • Page 20 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block256 0100h 0000h~00FFh Block257 0101h 0000h~00FFh Block258 0102h 0000h~00FFh Block259 0103h 0000h~00FFh Block260 0104h 0000h~00FFh Block261 0105h 0000h~00FFh Block262 0106h 0000h~00FFh Block263 0107h 0000h~00FFh Block264 0108h 0000h~00FFh Block265 0109h 0000h~00FFh Block266 010Ah 0000h~00FFh Block267...
  • Page 21 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block320 0140h 0000h~00FFh Block321 0141h 0000h~00FFh Block322 0142h 0000h~00FFh Block323 0143h 0000h~00FFh Block324 0144h 0000h~00FFh Block325 0145h 0000h~00FFh Block326 0146h 0000h~00FFh Block327 0147h 0000h~00FFh Block328 0148h 0000h~00FFh Block329 0149h 0000h~00FFh Block330 014Ah 0000h~00FFh Block331...
  • Page 22 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block384 0180h 0000h~00FFh Block385 0181h 0000h~00FFh Block386 0182h 0000h~00FFh Block387 0183h 0000h~00FFh Block388 0184h 0000h~00FFh Block389 0185h 0000h~00FFh Block390 0186h 0000h~00FFh Block391 0187h 0000h~00FFh Block392 0188h 0000h~00FFh Block393 0189h 0000h~00FFh Block394 018Ah 0000h~00FFh Block395...
  • Page 23 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block448 01C0h 0000h~00FFh Block449 01C1h 0000h~00FFh Block450 01C2h 0000h~00FFh Block451 01C3h 0000h~00FFh Block452 01C4h 0000h~00FFh Block453 01C5h 0000h~00FFh Block454 01C6h 0000h~00FFh Block455 01C7h 0000h~00FFh Block456 01C8h 0000h~00FFh Block457 01C9h 0000h~00FFh Block458 01CAh 0000h~00FFh Block459...
  • Page 24 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block512 0200h 0000h~00FFh Block513 0201h 0000h~00FFh Block514 0202h 0000h~00FFh Block515 0203h 0000h~00FFh Block516 0204h 0000h~00FFh Block517 0205h 0000h~00FFh Block518 0206h 0000h~00FFh Block519 0207h 0000h~00FFh Block520 0208h 0000h~00FFh Block521 0209h 0000h~00FFh Block522 020Ah 0000h~00FFh Block523...
  • Page 25 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block576 0240h 0000h~00FFh Block577 0241h 0000h~00FFh Block578 0242h 0000h~00FFh Block579 0243h 0000h~00FFh Block580 0244h 0000h~00FFh Block581 0245h 0000h~00FFh Block582 0246h 0000h~00FFh Block583 0247h 0000h~00FFh Block584 0248h 0000h~00FFh Block585 0249h 0000h~00FFh Block586 024Ah 0000h~00FFh Block587...
  • Page 26 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block640 0280h 0000h~00FFh Block641 0281h 0000h~00FFh Block642 0282h 0000h~00FFh Block643 0283h 0000h~00FFh Block644 0284h 0000h~00FFh Block645 0285h 0000h~00FFh Block646 0286h 0000h~00FFh Block647 0287h 0000h~00FFh Block648 0288h 0000h~00FFh Block649 0289h 0000h~00FFh Block650 028Ah 0000h~00FFh Block651...
  • Page 27 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block704 02C0h 0000h~00FFh Block705 02C1h 0000h~00FFh Block706 02C2h 0000h~00FFh Block707 02C3h 0000h~00FFh Block708 02C4h 0000h~00FFh Block709 02C5h 0000h~00FFh Block710 02C6h 0000h~00FFh Block711 02C7h 0000h~00FFh Block712 02C8h 0000h~00FFh Block713 02C9h 0000h~00FFh Block714 02CAh 0000h~00FFh Block715...
  • Page 28 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block768 0300h 0000h~00FFh Block769 0301h 0000h~00FFh Block770 0302h 0000h~00FFh Block771 0303h 0000h~00FFh Block772 0304h 0000h~00FFh Block773 0305h 0000h~00FFh Block774 0306h 0000h~00FFh Block775 0307h 0000h~00FFh Block776 0308h 0000h~00FFh Block777 0309h 0000h~00FFh Block778 030Ah 0000h~00FFh Block779...
  • Page 29 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block832 0340h 0000h~00FFh Block833 0341h 0000h~00FFh Block834 0342h 0000h~00FFh Block835 0343h 0000h~00FFh Block836 0344h 0000h~00FFh Block837 0345h 0000h~00FFh Block838 0346h 0000h~00FFh Block839 0347h 0000h~00FFh Block840 0348h 0000h~00FFh Block841 0349h 0000h~00FFh Block842 034Ah 0000h~00FFh Block843...
  • Page 30 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block896 0380h 0000h~00FFh Block897 0381h 0000h~00FFh Block898 0382h 0000h~00FFh Block899 0383h 0000h~00FFh Block900 0384h 0000h~00FFh Block901 0385h 0000h~00FFh Block902 0386h 0000h~00FFh Block903 0387h 0000h~00FFh Block904 0388h 0000h~00FFh Block905 0389h 0000h~00FFh Block906 038Ah 0000h~00FFh Block907...
  • Page 31 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block960 03C0h 0000h~00FFh Block961 03C1h 0000h~00FFh Block962 03C2h 0000h~00FFh Block963 03C3h 0000h~00FFh Block964 03C4h 0000h~00FFh Block965 03C5h 0000h~00FFh Block966 03C6h 0000h~00FFh Block967 03C7h 0000h~00FFh Block968 03C8h 0000h~00FFh Block969 03C9h 0000h~00FFh Block970 03CAh 0000h~00FFh Block971...
  • Page 32 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1024 0400h 0000h~00FFh Block1025 0401h 0000h~00FFh Block1026 0402h 0000h~00FFh Block1027 0403h 0000h~00FFh Block1028 0404h 0000h~00FFh Block1029 0405h 0000h~00FFh Block1030 0406h 0000h~00FFh Block1031 0407h 0000h~00FFh Block1032 0408h 0000h~00FFh Block1033 0409h 0000h~00FFh Block1034 040Ah 0000h~00FFh Block1035...
  • Page 33 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1088 0440h 0000h~00FFh Block1089 0441h 0000h~00FFh Block1090 0442h 0000h~00FFh Block1091 0443h 0000h~00FFh Block1092 0444h 0000h~00FFh Block1093 0445h 0000h~00FFh Block1094 0446h 0000h~00FFh Block1095 0447h 0000h~00FFh Block1096 0448h 0000h~00FFh Block1097 0449h 0000h~00FFh Block1098 044Ah 0000h~00FFh Block1099...
  • Page 34 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1152 0480h 0000h~00FFh Block1153 0481h 0000h~00FFh Block1154 0482h 0000h~00FFh Block1155 0483h 0000h~00FFh Block1156 0484h 0000h~00FFh Block1157 0485h 0000h~00FFh Block1158 0486h 0000h~00FFh Block1159 0487h 0000h~00FFh Block1160 0488h 0000h~00FFh Block1161 0489h 0000h~00FFh Block1162 048Ah 0000h~00FFh Block1163...
  • Page 35 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1216 04C0h 0000h~00FFh Block1217 04C1h 0000h~00FFh Block1218 04C2h 0000h~00FFh Block1219 04C3h 0000h~00FFh Block1220 04C4h 0000h~00FFh Block1221 04C5h 0000h~00FFh Block1222 04C6h 0000h~00FFh Block1223 04C7h 0000h~00FFh Block1224 04C8h 0000h~00FFh Block1225 04C9h 0000h~00FFh Block1226 04CAh 0000h~00FFh Block1227...
  • Page 36 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1280 0500h 0000h~00FFh Block1281 0501h 0000h~00FFh Block1282 0502h 0000h~00FFh Block1283 0503h 0000h~00FFh Block1284 0504h 0000h~00FFh Block1285 0505h 0000h~00FFh Block1286 0506h 0000h~00FFh Block1287 0507h 0000h~00FFh Block1288 0508h 0000h~00FFh Block1289 0509h 0000h~00FFh Block1290 050Ah 0000h~00FFh Block1291...
  • Page 37 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1344 0540h 0000h~00FFh Block1345 0541h 0000h~00FFh Block1346 0542h 0000h~00FFh Block1347 0543h 0000h~00FFh Block1348 0544h 0000h~00FFh Block1349 0545h 0000h~00FFh Block1350 0546h 0000h~00FFh Block1351 0547h 0000h~00FFh Block1352 0548h 0000h~00FFh Block1353 0549h 0000h~00FFh Block1354 054Ah 0000h~00FFh Block1355...
  • Page 38 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1408 0580h 0000h~00FFh Block1409 0581h 0000h~00FFh Block1410 0582h 0000h~00FFh Block1411 0583h 0000h~00FFh Block1412 0584h 0000h~00FFh Block1413 0585h 0000h~00FFh Block1414 0586h 0000h~00FFh Block1415 0587h 0000h~00FFh Block1416 0588h 0000h~00FFh Block1417 0589h 0000h~00FFh Block1418 058Ah 0000h~00FFh Block1419...
  • Page 39 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1472 05C0h 0000h~00FFh Block1473 05C1h 0000h~00FFh Block1474 05C2h 0000h~00FFh Block1475 05C3h 0000h~00FFh Block1476 05C4h 0000h~00FFh Block1477 05C5h 0000h~00FFh Block1478 05C6h 0000h~00FFh Block1479 05C7h 0000h~00FFh Block1480 05C8h 0000h~00FFh Block1481 05C9h 0000h~00FFh Block1482 05CAh 0000h~00FFh Block1483...
  • Page 40 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1536 0600h 0000h~00FFh Block1537 0601h 0000h~00FFh Block1538 0602h 0000h~00FFh Block1539 0603h 0000h~00FFh Block1540 0604h 0000h~00FFh Block1541 0605h 0000h~00FFh Block1542 0606h 0000h~00FFh Block1543 0607h 0000h~00FFh Block1544 0608h 0000h~00FFh Block1545 0609h 0000h~00FFh Block1546 060Ah 0000h~00FFh Block1547...
  • Page 41 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1600 0640h 0000h~00FFh Block1601 0641h 0000h~00FFh Block1602 0642h 0000h~00FFh Block1603 0643h 0000h~00FFh Block1604 0644h 0000h~00FFh Block1605 0645h 0000h~00FFh Block1606 0646h 0000h~00FFh Block1607 0647h 0000h~00FFh Block1608 0648h 0000h~00FFh Block1609 0649h 0000h~00FFh Block1610 064Ah 0000h~00FFh Block1611...
  • Page 42 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1664 0680h 0000h~00FFh Block1665 0681h 0000h~00FFh Block1666 0682h 0000h~00FFh Block1667 0683h 0000h~00FFh Block1668 0684h 0000h~00FFh Block1669 0685h 0000h~00FFh Block1670 0686h 0000h~00FFh Block1671 0687h 0000h~00FFh Block1672 0688h 0000h~00FFh Block1673 0689h 0000h~00FFh Block1674 068Ah 0000h~00FFh Block1675...
  • Page 43 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1728 06C0h 0000h~00FFh Block1729 06C1h 0000h~00FFh Block1730 06C2h 0000h~00FFh Block1731 06C3h 0000h~00FFh Block1732 06C4h 0000h~00FFh Block1733 06C5h 0000h~00FFh Block1734 06C6h 0000h~00FFh Block1735 06C7h 0000h~00FFh Block1736 06C8h 0000h~00FFh Block1737 06C9h 0000h~00FFh Block1738 06CAh 0000h~00FFh Block1739...
  • Page 44 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1792 0700h 0000h~00FFh Block1793 0701h 0000h~00FFh Block1794 0702h 0000h~00FFh Block1795 0703h 0000h~00FFh Block1796 0704h 0000h~00FFh Block1797 0705h 0000h~00FFh Block1798 0706h 0000h~00FFh Block1799 0707h 0000h~00FFh Block1800 0708h 0000h~00FFh Block1801 0709h 0000h~00FFh Block1802 070Ah 0000h~00FFh Block1803...
  • Page 45 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1856 0740h 0000h~00FFh Block1857 0741h 0000h~00FFh Block1858 0742h 0000h~00FFh Block1859 0743h 0000h~00FFh Block1860 0744h 0000h~00FFh Block1861 0745h 0000h~00FFh Block1862 0746h 0000h~00FFh Block1863 0747h 0000h~00FFh Block1864 0748h 0000h~00FFh Block1865 0749h 0000h~00FFh Block1866 074Ah 0000h~00FFh Block1867...
  • Page 46 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1920 0780h 0000h~00FFh Block1921 0781h 0000h~00FFh Block1922 0782h 0000h~00FFh Block1923 0783h 0000h~00FFh Block1924 0784h 0000h~00FFh Block1925 0785h 0000h~00FFh Block1926 0786h 0000h~00FFh Block1927 0787h 0000h~00FFh Block1928 0788h 0000h~00FFh Block1929 0789h 0000h~00FFh Block1930 078Ah 0000h~00FFh Block1931...
  • Page 47 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Page and Sector Block Block Address Address Block1984 07C0h 0000h~00FFh Block1985 07C1h 0000h~00FFh Block1986 07C2h 0000h~00FFh Block1987 07C3h 0000h~00FFh Block1988 07C4h 0000h~00FFh Block1989 07C85h 0000h~00FFh Block1990 07C6h 0000h~00FFh Block1991 07C7h 0000h~00FFh Block1992 07C8h 0000h~00FFh Block1993 07C9h 0000h~00FFh Block1994 07CAh 0000h~00FFh Block1995...
  • Page 48 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.2 lnternal Memory Spare Area Assignment The figure below shows the assignment of the spare area in the Internal Memory NAND Array. Main area Main area 256W Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3 Spare Area Assignment in the Internal Memory NAND Array Information Word Byte Note...
  • Page 49 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.3 External Memory (BufferRAM) Address Map The following table shows the External Memory address map in Word and Byte Order. Note that the data output is unknown while host reads a register bit of reserved area. Address Address Division (word order) (byte order)
  • Page 50 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.4 External Memory Map Detail Information The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas. • BootRAM(Main area) -0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB 0000h~00FFh(512B) BootM 0 (sector 0 of page 0) •...
  • Page 51 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.7.5 External Memory Spare Area Assignment Word Byte Buf. Address Address 8000h 10000h 8001h 10002h 8002h 10004h 8003h 10006h BootS 0 8004h 10008h 8005h 1000Ah 8006h 1000Ch 8007h 1000Eh 8008h 10010h 8009h 10012h 800Ah 10014h 800Bh 10016h BootS 1 800Ch 10018h 800Dh...
  • Page 52 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Word Byte Buf. Address Address 8020h 10040h 8021h 10042h 8022h 10044h 8023h 10046h DataS 0_2 8024h 10048h 8025h 1004Ah 8026h 1004Ch 8027h 1004Eh 8028h 10050h 8029h 10052h 802Ah 10054h 802Bh 10056h DataS 0_3 802Ch 10058h 802Dh 1005Ah 802Eh 1005Ch 802Fh 1005Eh...
  • Page 53 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Word Byte Buf. Address Address 8048h 10090h 8049h 10092h 804Ah 10094h 804Bh 10096h DataS 1_3 804Ch 10098h 804Dh 1009Ah 804Eh 1009Ch 804Fh 1009Eh NOTE : - BI: Bad block Information >Host can use complete spare area except BI and ECC code area. For example, Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation.
  • Page 54 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8 Registers Section 2.8 of this specification provides information about the MuxOneNAND registers. 2.8.1 Register Address Map This map describes the register addresses, register name, register description, and host accessibility. Address Address (word order) (byte order) F000h 1E000h F001h 1E002h F002h...
  • Page 55 FF07h 1FE0Eh FF08h 1FE10h FF09h~FFFFh 1FE12h~1FFFEh 2.8.2 Manufacturer ID Register F000h (R) This Read register describes the manufacturer's identification. Samsung Electronics Company manufacturer's ID is 00ECh. F000h, default = 00ECh Host Name Access Reserved Reserved for user Write Protection Current memory Write Protection status...
  • Page 56 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.3 Device ID Register F001h (R) This Read register describes the device. F001h, see table for default. Device Identification Device Identification DeviceID [1:0] Vcc 00 = 1.8V, 01/10/11 = reserved DeviceID [2] Muxed/Demuxed 0 = Muxed, 1 = Demuxed DeviceID [3] Single/DDP 0 = Single, 1 = DDP DeviceID [7:4] Density...
  • Page 57 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.4 Version ID Register F002h This Register is reserved for internal use. 2.8.5 Data Buffer Size Register F003h (R) F003h, default = 0800h DataBufSize Data Buffer Size Information Register Information Description Total data buffer size in Words equal to 2 buffers of 1024 Words each DataBufSize (2 x 1024 = 2 ) in the memory interface...
  • Page 58 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.6 Boot Buffer Size Register F004h (R) This Read register describes the size of the Boot Buffer. F004h, default = 0200h Register Information BootBufSize 2.8.7 Number of Buffers Register F005h (R) This Read register describes the number of each Buffer. F005h, default = 0201h DataBufAmount Number of Buffers Information...
  • Page 59 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.9 Start Address1 Register F100h (R/W) This Read/Write register describes the NAND Flash block address which will be loaded, programmed, or erased. F100h, default = 0000h Reserved(0000) NOTE : 1) Bit 0 should be fixed ‘low’ at 2X Program and 2X Cache Program. Device 4Gb DDP Start Address1 Information...
  • Page 60 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.11 Start Address3 Register F102h (R/W) This Read/Write register describes the NAND Flash destination block address which will be copy back programmed. Also, this register indi- cates the block address for the first page to be read in Cache Read Operation. F102h, default = 0000h Reserved(00000) Device...
  • Page 61 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.13 Start Address5 Register F104h (R/W) This Read/Write register describes the number of page in Synchronous Burst Block Read. F104h, default = 0000h Reserved(0000000000) Flash Page Count (FPC) Information 000000 (Default) 000011 000100 111111 NOTE : Synchronous Burst Block Read are NOT able to be perforformed with 1 or 2pages. 2.8.14 Start Address6 Register F105h This register is reserved for future use.
  • Page 62 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.17 Start Buffer Register F200h (R/W) This Read/Write register describes the BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA). The BufferRAM Sector Count (BSC) field specifies the number of sectors to be loaded, programmed, or copy back programmed. At 00 value (the default value), the number of sector is "4".
  • Page 63 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.18 Command Register F220h (R/W) Command can be issued by two following methods, and user may select one way or the other to issue appropriate command; 1. Write command into Command Register when INT is at ready state. INT will automatically turn to busy state as command is issued. Once the desired operation is completed, INT will go back ready state.
  • Page 64 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.18.1 Two Methods to Clear Interrupt Register in Command Input To clear Interrupt Register in command input, user may select one from either following methods. First method is to turn INT low by manually writing 0000h to INT bit of Interrupt Register. Second method is input command while INT is high, and the device will automatically turn INT to low.
  • Page 65 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.19 System Configuration 1 Register F221h (R, R/W) This Read/Write register describes the system configuration. F221h, default = 40C0h BRWL Read Mode (RM) Read Mode Information[15] Item Burst Read Write Latency (BRWL) BRWL 000~010 100 (default) * Default value of BRWL and HF value is BRWL=4, HF=0. For host frequency over 66MHz, BRWL should be 6 or 7 while HF is 1.
  • Page 66 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Burst Length (BL) Hosts must follow burst length set by BL when reading data in synchronous burst read. 110~111 NOTE : 1) For normal synchronous burst read, setting BL=000 (continuous) will read 1K words, depending on the number of clocks. In using Synchronous Burst Block Read, setting BL=000 (continuous) will read the amount of data in a block set by number of page register.
  • Page 67 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) I/O Buffer Enable (IOBE) IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid after IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register. I/O Buffer Enable Information[5] Item IOBE...
  • Page 68 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Write Mode (WM) Asynchronous Write(default) Synchronous Write Write Mode Information[1] Item MRS(Mode register Setting) Description Other Case NOTE : 1) Operation not guaranteed for cases not defined in above table. Boot Buffer Write Protect Status(BWPS) Boot Buffer Write Protect Status Information[0] Item BWPS Write Mode...
  • Page 69 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.20 System Configuration 2 Register F222h This register is reserved for future use. 2.8.21 Controller Status Register F240h (R) This Read register shows the overall internal status of the MuxOneNAND and the controller. F240h, default = 0000h OnGo Lock Load Prog Erase Error OnGo...
  • Page 70 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Program This bit shows the Program Operation status. In 2X Cache Program Operation, ‘Prog’ bit shows the overall status of 2X Cache Program process. Program Information[12] Item Prog Program Operation status Erase This bit shows the Erase Operation status. Erase Information[11] Item Erase...
  • Page 71 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Reset / Busy (RSTB) This bit shows the Reset Operation status. RSTB Information[7] Item RSTB OTP Lock Status (OTP This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against accidental re- programming of data stored in the OTP block.
  • Page 72 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Plane1 Current This bit shows the current program status of Plane1 at Final 2X Cache Program, 2X Program, and 2X Interleave Cache Program. During 2X Cache Program prior to ‘2X Program’ command, which will be Final 2X Cache Program, this bit will be invalid (fixed to 0). Plane1 Current Information[3] Plane1 Current Plane2 Previous...
  • Page 73 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Controller Status Register Output Modes [15] [14] [13] Mode OnGo Lock Load Load / Cache Read Ongoing Program Ongoing Erase Ongoing Reset Ongoing Multi-Block Erase Ongoing Erase Verify Read Ongoing Load / Cache Read OK Program OK Erase OK Erase Verify Read Load Fail Program Fail...
  • Page 74 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Controller Status Register Output Modes (Continued) [15] [14] [13] Mode OnGo Lock Load Program Fail on 2X Program (Plane1) Program Fail on 2X Program (Plane2) Program Fail on 2X Program (Plane1 & Plane2) Previous Program Fail Dur- ing 2X Cache Program (Plane1) Previous Program Fail Dur- ing 2X Cache Program...
  • Page 75 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.22 Interrupt Status Register F241h (R/W) This Read/Write register shows status of the MuxOneNAND interrupts. In DDP, INT register will not be written if DBS, DFS is not set. F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset Reserved(0000000) Interrupt (INT) This is the master interrupt bit.
  • Page 76 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Write Interrupt (WI) This is the Write interrupt bit. WI Interrupt [6] Status Conditions At the completion of an Program Operation sets itself to ‘1’ (0080h, 001Ah, 001Bh, 007Dh, 007Fh) ’0’ is written to this bit, Cold/Warm/Hot reset is being performed, or com- clears to ‘0’...
  • Page 77 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.23 Start Block Address Register F24Ch (R/W) This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock Block' command, 'Unlock Block' command, or ‘Lock-Tight' Command. F24Ch, default = 0000h Reserved(000000) Device SBA Information[10:0]...
  • Page 78 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.26 ECC Status Register FF00h (R) This Read register shows the Error Correction Status. The MuxOneNAND can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported. ECC can be performed on the NAND Flash main and spare memory areas. The ECC status register can also show the number of errors in a sector as a result of an ECC check in during a load operation.
  • Page 79 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.27 ECC Result of 1 Selected Sector, Main Area Data This Read register shows the Error Correction result for the 1st selected sector of the main area data. ECCposWord0 is the error position address in the Main Area data of 256 words. ECCposIO0 is the error position address which selects 1 of 16 DQs. ECCposWord0 and ECCposIO0 are also updated at boot loading.
  • Page 80 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2.8.31 ECC Result of 3 Selected Sector, Main Area Data This Read register shows the Error Correction result for the 3rd selected sector of the main area data. ECCposWord2 is the error position address in the Main Area data of 256 words. ECCposIO2 is the error position address which selects 1 of 16 DQs. ECCposWord2 and ECCposIO2 are also updated at boot loading.
  • Page 81 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) ECC Log Sector ECClogSector0~ECClogSector3 indicates the error position in the 2nd word and LSB of 3rd word in the spare area. Refer to note 2 in chapter 2.7.2 ECClogSector Information [5:4] ECClogSector 10, 11 FLASH MEMORY Error Position 2nd word 3rd word Reserved...
  • Page 82 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.0 DEVICE OPERATION This section of the datasheet discusses the operation of the MuxOneNAND device. It is followed by AC/DC Characteristics and Timing Diagrams which may be consulted for further information. The MuxOneNAND supports a limited command-based interface in addition to a register-based interface for performing operations on the device.
  • Page 83 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.1.1 Reset MuxOneNAND Command The Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device. 3.1.2 Load MuxOneNAND Command Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing 00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0.
  • Page 84 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.2 Device Bus Operation The device bus operations are shown in the table below. Operation Standby Warm Reset Asynchronous Write Asynchronous Read Start Initial Burst Read Burst Read Terminate Burst Read Cycle Terminate Burst Read Cycle via RP Terminate Current Burst Read Cycle and Start New Burst Read Cycle...
  • Page 85 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.3 Reset Mode Operation The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Array Reset. Section 3.3 discusses the operation of these reset modes. The Register Reset Table shows the which registers are affected by the various types or Reset operations. Internal Register Reset Table Internal Registers F000h...
  • Page 86 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.3.1 Cold Reset Mode Operation See Timing Diagram 6.17 At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal. This trig- gers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from the beginning of memory into the BootRAM.
  • Page 87 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4 Write Protection Operation The MuxOneNAND can be write-protected to prevent re-programming or erasure of data. The areas of write-protection are the BootRAM, and the NAND Flash Array. 3.4.1 BootRAM Write Protection Operation At system power-up, voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal which trig- gers bootcode loading.
  • Page 88 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4.3.1 Unlocked NAND Array Write Protection State An Unlocked block can be programmed or erased. The status of an unlocked block can be changed to locked or locked-tight using the appro- priate software command. (locked-tight state can be achieved via lock-tight command which follows lock command) Only one block can be released from lock state to unlock state with Unlock command and addresses.
  • Page 89 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.4.3.3 Locked-tight NAND Array Write Protection State A block that is in a locked-tight state can only be changed to locked state after a Cold or Warm Reset. Unlock and Lock command sequences will not affect its state. This is an added level of write protection security. If any blocks are changed to locked-tight state, the all block unlock command will fail.
  • Page 90 Read Write Protection Register Add: F24Eh DQ[2:0]=US,LS,LTS Lock/Unlock/Lock-Tight * Samsung strongly recommends to follow the above flow chart NOTE : 1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1 Start...
  • Page 91 Read Write Protection Register Add: F24Eh DQ[2:0]=US,LS,LTS * Samsung strongly recommends to follow the above flow chart * * If any blocks are changed to locked-tight state, the all block unlock command will fail. In order to use all block unlock command again, a cold reset is needed.
  • Page 92 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.5 Data Protection During Power Down Operation See Timing Diagram 6.21 The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin which provides hardware protection is recommended to be kept at VIL before Vcc drops to 1.5V. 3.6 Load Operation See Timing Diagrams 6.11 The Load operation is initiated by setting up the start address from which the data is to be loaded.
  • Page 93 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7 Read Operation See Timing Diagrams 6.1, 6.2, 6.5, and 6.6 The device has two read modes; Asynchronous Read and Synchronous Burst Read. The initial state machine automatically sets the device into the Asynchronous Read Mode (RM=0) to prevent the spurious altering of memory content upon device power up or after a Hardware reset.
  • Page 94 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7.2.1 Continuous Linear Burst Read Operation See Timing Diagram 6.2 First Clock Cycle The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the system by pulsing high.
  • Page 95 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.7.2.3 Programmable Burst Read Latency Operation See Timing Diagrams 6.1 and 6.2 Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks. The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with the (n+1)th rising edge.
  • Page 96 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.8 Cache Read Operation (RM=X, WM=X) A Normal Load Operation(0000h) consists of sequential operation of ‘sensing from NAND Flash Array to Page Buffer’ and ‘transferring from Page Buffer to DataRAM’. Cache Read is a method of improving the data read throughput performance of the device by allowing new data to be transferred from the NAND Flash Array memory into a Page Buffer while the previous data that was requested is transferred from the Page Buffer to the DataRAM.
  • Page 97 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Cache Read Flow Chart Start Select DataRAM for DDP Add: F101h DQ=DBS Write ‘BSA , BSC ’ of Flash Add: F200h DQ=BSA, BSC Write ‘FCBA’ of Flash Add: F102h DQ=FCBA Write ‘FCPA, FCSA ’ of Flash Add: F103h DQ=FCPA, FCSA Write ’DFS*, FBA’...
  • Page 98 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Cache Read Diagram ≈ ≈ ≈ ≈ - 98 - FLASH MEMORY...
  • Page 99 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9 Synchronous Burst Block Read Operation(RM=1, WM=X) See Timing Diagram 6.3 and 6.4. MuxOneNAND is internally composed of two DataRAMs and NAND Flash Array. And for host to read data from NAND Cell Array, load operation which moves data from NAND Cell Array to DataRAM is required. After this load operation, host may use various read mode, such as synchronous burst read or asynchronous read, to read data from MuxOneNAND.
  • Page 100 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.1 Burst Address Sequence During Synchronous Burst Block Read Mode In a Synchronous Burst Block Read, data is output with respect to a clock input. MuxOneNAND is capable of a continuous linear burst operation within one block size and a fixed-length linear burst operation of a preset length.
  • Page 101 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Synchronous Burst Block Read Boundary Read Sequence for Single Plane Device :note that only main area data is read. Page 0 Page 63 Main Area Spare Area - 101 - FLASH MEMORY Not supported...
  • Page 102 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.3 4-, 8-, 16-, 32-, 1K- Word Linear Burst Read Operation During Synchronous Burst Block Read Mode Same as normal linear burst read, synchronous burst block read enables a fixed number of words to be read from consecutive address. The device supports a burst read from consecutive addresses of 4-, 8-, 16-, 32- and 1K-words with no wrap.
  • Page 103 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.9.5 Handshaking Operation During Synchronous Burst Block Read Mode The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see Section 2.8.19, "System Configuration1 Register").
  • Page 104 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.10 Synchronous Write(RM=1, WM=1) See Timing Diagram 6.8, 6.9 and 6.10. Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE goes low, the address to access is latched on the next rising edge of clk that ADV is low. During this first clock rising edge, WE indicates whether the operation is going to be a read (WE = high) or write (WE = low).
  • Page 105 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.11 Program Operation See Timing Diagram 6.12 The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array. The device has two 2KB data buffers, each 1 Page (2KB + 64B) in size. Each page has 4 sectors of 512B each main area and 16B spare area. The device can be programmed in units of 1~4 sectors.
  • Page 106 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Program Operation Flow Diagram Start Select DataRAM for DDP Add: F101h DQ=DBS* Write Data into DataRAM ADD: DP DQ=Data-in Data Input Completed? Write ’DFS*, FBA’ of Flash Add: F100h DQ=DFS*’, FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ’BSA, BSC’...
  • Page 107 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.11.1 2X Program Operation See Timing Diagram 6.13 The 2X Program is an extension of Program Operation. Since the device is equipped with two DataRAMs, and two-plane NAND Flash mem- ory array, these two component enables simultaneous program of 4KB. Plane1 has only even blocks such as block0, block2, block4 while Plane2 has only odd blocks such as block1, block3, block5.
  • Page 108 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Program Operation Flow Diagram Start Select DataRAM for DDP Add: F101h DQ=DBS* Write Data into DataRAM ADD: DP DQ=Data-in Data Input Completed? Write ‘DFS*, FBA’ of Flash Add: F100h DQ=DFS*, FBA Write ‘FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ‘BSA, BSC’...
  • Page 109 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.11.2 2X Cache Program Operation See Timing Diagram 6.14 The 2X Cache Program Operation is invented to accomplish continuous 2X Program Operation efficiently by hiding transferring time from Dat- aRAM to page buffer.. 1. 4KB Data write from host to DataRAMs. 2.
  • Page 110 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 2X Cache Program Operation Flow Diagram Start Select DataRAM for DDP Add: F101h DQ=DBS Write Data into DataRAM0,1 Add: DataRAM DQ=Data(4KB) Write ‘DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA Write ‘FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ‘BSA’, ‘BSC’...
  • Page 111 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.11.3 2X Interleave Cache Program Operation See Timing Diagram 6.15 The 2X Interleave Cache Program is available only on DDP. Host can write data on a chip while programming another chip with this operation. 2X Interleave Cache Program is executed as following: 1.
  • Page 112 6) Once ‘2X PGM command’ is issued onto a chip, the same command(2X PGM) must be issued onto another chip. If not, Samsung can not gurantee the following operation. 7) If error bit is set at this step, DQ[1]~[4] shoulde be checked in order to find where the error occurred.
  • Page 113 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.12 Copy-Back Program Operation The Copy-Back program is configured to quickly rewrite data stored in one page without utilizing memory other than OneNAND. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of block is updated and the rest of the block also need to be copied to the newly assigned free block.
  • Page 114 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) The Copy-Back steps shown in the flow chart are: • Data is read from the NAND Array using Flash Block Address (FBA), Flash Page Address (FPA) and Flash Sector Address (FSA). FBA, FPA, and FSA identify the source address to read data from NAND Flash array. •...
  • Page 115 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.12.1 Copy-Back Program Operation with Random Data Input The Copy-Back Program Operation with Random Data Input in MuxOneNAND consists of 2 phase, Load data into DataRAM, Modify data and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the host, then pro- grammed into the destination page.
  • Page 116 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13 Erase Operation There are multiple methods for erasing data in the device including Block Erase and Multi-Block Erase. 3.13.1 Block Erase Operation See Timing Diagram 6.16 The Block Erase Operation is done on a block basis. To erase a block is to write all 1's into the desired memory block by executing the Internal Erase Routine.
  • Page 117 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) In order to perform the Internal Erase Routine, the following command sequence is necessary. • The Host selects Flash Core of DDP chip. • The Host sets the block address of the memory location. • The Erase Command initiates the Internal Erase Routine. During the execution of the Routine, the host is not required to provide further controls or timings.
  • Page 118 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13.3 Multi-Block Erase Verify Read Operation After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase Verify Command combined with address of each block. If a failed address is identified, it must be managed by firmware. Multi Block Erase/ Multi Block Erase Verify Read Flow Chart Start Select DataRAM for DDP...
  • Page 119 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.13.4 Erase Suspend / Erase Resume Operation The Erase Suspend/Erase Resume Commands interrupt and restart a Block Erase or Multi-Block Erase operation so that user may perform another urgent operation on the block that is not being designated by Erase/Multi-Block Erase Operation. Erase Suspend During a Block Erase Operation When Erase Suspend command is written during a Block Erase or Multi-Block Erase operation, the device requires a maximum of 500us to suspend erase operation.
  • Page 120 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Erase Resume When the Erase Resume command is executed, the Block Erase will restart. The Erase Resume operation does not actually resume the erase, but starts it again from the beginning. When an Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state. For Multi Block Erase, Erase suspend/Resume can be operated after final Erase command (0094h) is issued.
  • Page 121 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Area Structure One Block: 64pages 128KB+4KB 1st Block OTP Area Structure One Block: 64pages 128KB+4KB Page:2KB+64B Sector(main area):512B Sector(spare area):16B Page:2KB+64B Sector(main area):512B Sector(spare area):16B - 121 - FLASH MEMORY Manufacturer Area : 14pages page 50 to page 63 User Area : 50pages page 0 to page 49...
  • Page 122 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.1 OTP Block Load Operation An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer, thus making the OTP contents available to the Host. The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of a Flash Block Address (FBA) command.
  • Page 123 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.2 OTP Block Program Operation An OTP Block Program Operation accesses the OTP area and programs content from the DataRAM on-chip buffer to the designated page(s) of the OTP. A memory location in the OTP area can be programmed only one time (no erase operation permitted). The OTP area is programmed using the same sequence as normal program operation after being accessed by the command (see section 3.8 for more information).
  • Page 124 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Program Operation Flow Chart Start Select DataRAM for DDP Add: F101h DQ=DBS* Write ‘DFS*, FBA’ of Flash Add: F100h DQ=DFS*, FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ‘OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT...
  • Page 125 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.3 OTP Block Lock Operation Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any changes from being made. Unlike the main area of the NAND Flash Array memory, once the OTP block is locked, it cannot be unlocked, for locking bit for both blocks lies in the same word of OTP area.
  • Page 126 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP Block Lock Operation Flow Chart Select DataRAM for DDP Add: F101h DQ=DBS* Write ‘DFS’, ‘FBA’ of Flash Add: F100h DQ=DFS, FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT Write Data into DataRAM...
  • Page 127 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.4 1st Block OTP Lock Operation 1st Block could be used as OTP, for secured booting operation. 1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP, 1st Block OTP cannot be erased or programmed.
  • Page 128 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 1st Block OTP Lock Operation Flow Chart Select DataRAM for DDP Add: F101h DQ=DBS* Write ‘DFS’, ‘FBA’ of Flash Add: F100h DQ=DFS, FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT...
  • Page 129 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.14.5 OTP and 1st Block OTP Lock Operation OTP and 1st Block can be locked simultaneously, for locking bit lies in the same word of OTP area. 1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP, 1st Block OTP cannot be erased or programmed.
  • Page 130 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) OTP and 1st Block OTP Lock Operation Flow Chart Start Select DataRAM for DDP Add: F101h DQ=DBS* Write ‘DFS’, ’FBA’ of Flash Add: F100h DQ=DFS, FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition...
  • Page 131 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.15 Dual Operations The device has independent dual data buffers on-chip (except during the Boot Load period) that enables higher performance read and pro- gram operation. 3.15.1 Read-While-Load Operation This operation accelerates the read performance of the device by enabling data to be read out by the host from one DataRAM buffer while the other DataRAM buffer is being loaded with data from the NAND Flash Array memory.
  • Page 132 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Read While Load Diagram - 132 -...
  • Page 133 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Write While Program Diagram - 133 -...
  • Page 134 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.16 DQ6 Toggle Bit The MuxOneNAND device has DQ6 Toggle bit. Toggle bit is another option to detect whether an internal load operation is in progress or com- pleted. Once the BufferRAM(BootRAM, DataRAM0, DataRAM1) is at a busy state during internal load operation, DQ6 will toggle. Toggling DQ6 will stop after the device completes its internal load operation.
  • Page 135 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 3.17 ECC Operation The MuxOneNAND device has on-chip ECC with the capability of detecting 2 bit errors and correcting 1-bit errors in the NAND Flash Array memory main and spare areas. As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation, the device initiates a background operation which generates an Error Correction Code (ECC) of 24bits for each sector main area data and 10bits for 2nd and 3rd word data of each sector spare area.
  • Page 136 An invalid block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFFFh data at the 1st word of sector0.
  • Page 137 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Invalid Block Table Creation Flow Chart Increment Block Address Create (or update) Invalid Block(s) Table 3.18.2 Invalid Block Replacement Operation Within its life time, additional invalid blocks may develop with NAND Flash Array memory. Refer to the device's qualification report for the actual data.
  • Page 138 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Referring to the diagram for further illustration, when an error happens in the nth page of block 'A' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'B' via data buffer0. Then copy the nth page data of block 'A' in the data buffer1 to the nth page of block 'B' or any free block.

  • Page 139: Absolute Maximum Ratings

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 4.0 DC CHARACTERISTICS 4.1 Absolute Maximum Ratings Parameter Voltage on any pin relative to V Temperature Under Bias Storage Temperature Short Circuit Output Current Recommended Operating Temperature NOTE : 1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V@1.8V device). Maximum DC voltage may overshoot to Vcc+2.0V for periods <20ns.
  • Page 140 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 4.3 DC Characteristics Parameter Symbol Input Leakage Current Output Leakage Current Active Asynchronous Read Current (Note 2) Active Burst Read Current (Note 2) Active Burst Write Current (Note 2) Active Asynchronous Write Current (Note 2) Active Load Current (Note 3) Active Program Current (Note 3) Active Erase Current (Note 3) Multi Block Erase Current (Note 3)
  • Page 141 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.0 AC CHARACTERISTICS 5.1 AC Test Conditions Parameter Input Pulse Levels Input Rise and Fall Times other inputs Input and Output Timing Levels Output Load Input & Output Test Point Input Pulse and Test Point 5.2 Device Capacitance CAPACITANCE = 25 °C, V = 1.8V, f = 1.0MHz)
  • Page 142 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.4 AC Characteristics for Synchronous Burst Read See Timing Diagrams 6.1, 6.2, 6.3, 6.4 and 6.24 Parameter Clock Clock Cycle Initial Access Time Burst Access Time Valid Clock to Output Delay AVD Setup Time to CLK AVD Hold Time from CLK AVD High to OE Low Address Setup Time to CLK Address Hold Time from CLK...
  • Page 143 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.5 AC Characteristics for Asynchronous Read See Timing Diagrams 6.5, 6.6, 6.22 and 6.23. Parameter Access Time from CE Low Asynchronous Access Time from AVD Low Asynchronous Access Time from address valid Read Cycle Time AVD Low Time Address Setup to rising edge of AVD Address Hold from rising edge of AVD Output Enable to Output Valid...
  • Page 144 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.7 AC Characteristics for Asynchronous Write See Timing Diagrams 6.7 Parameter WE Cycle Time AVD low pulse width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time WE Pulse Width WE Pulse Width High WE Disable to AVD Enable CE Low to RDY Valid...
  • Page 145 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 5.9 AC Characteristics for Load/Program/Erase Performance See Timing Diagrams 6.11, 6.12, and 6.16 Parameter Spare Load time(Note 1, Note2) Sector Load time(Note 1) Page Load time(Note 1) Spare Program time(Note 1, Note3) Sector Program time(Note 1) Page Pogram time(Note 1) OTP Access Time(Note 1) Lock/Unlock/Lock-tight (Note 1) All Block Unlock Time...

  • Page 146: Timing Diagrams

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.0 TIMING DIAGRAMS 6.1 8-Word Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5.4 BRWL = 4 RDYO AVDS AVDO AVDH A/DQ0: A/DQ15 Hi-Z 6.2 Continuous Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5.4 BRWL = 4 RDYO AVDS...
  • Page 147 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.3 Synchronous Burst Block Read Operation Timing See AC Characteristics table 5.4 and 5.7. - 147 -...
  • Page 148 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.4 Synchronous Burst Block Read Timing See AC Characteristics table 5.4 and 5.11. Case 1 : BL=1K word synchronous burst block read - 148 -...
  • Page 149 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) Case 2 : BL=8 word synchronous burst block read ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ - 149 -...
  • Page 150 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.5 Asynchronous Read (VA Transition Before AVD Low) See AC Characteristics Table 5.5 A/DQ0: A/DQ15 AAVDS Hi-Z NOTE : VA=Valid Read Address, RD=Read Data. See timing diagram 6.22, 6.23 for tASO 6.6 Asynchronous Read (VA Transition After AVD Low) See AC Characteristics Table 5.5 A/DQ0: A/DQ15...
  • Page 151 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.7 Asynchronous Write See AC Characteristics Table 5.7 AAVDS AAVDH AVDP Hi-Z NOTE : VA=Valid Read Address, WD=Write Data. Valid WD Valid WD - 151 - FLASH MEMORY Hi-Z...
  • Page 152 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.8 8-Word Linear Burst Write Mode See AC Characteristics Table 5.8 BRWL = 4 RDYO AVDS AVDH A/DQ0: A/DQ15 Hi-Z 6.9 Burst Write Operation followed by Burst Read See AC Characteristics Table 5.8 BRWL = 4 RDYO AVDS AVDH A/DQ0: A/DQ15...
  • Page 153 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.10 Start Initial Burst Write Operation See AC Characteristics Table 5.8 BRWL = 4 RDYO AVDS AVDH A/DQ0: Hi-Z CEHP CLKH CLKL RDYS RDYA - 153 - FLASH MEMORY BRWL = 4...
  • Page 154 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.11 Load Operation Timing See AC Characteristics Tables 5.5, 5.7 and 5.9. Load Command Sequence (last two cycles) AAVDS AVDP AAVDH ADQ0~15 Hi-Z NOTE : 1) AA = Address of address register CA = Address of command register LCD = Load Command LMA = Address of memory to be loaded BA = Address of BufferRAM to load the data...
  • Page 155 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.12 Program Operation Timing See AC Characteristics Tables 5.5, 5.7 and 5.9. Program Command Sequence (last two cycles) AVDP AAVDS AAVDH A/DQ0: A/DQ15 Hi-Z NOTE : 1) AA = Address of address register CA = Address of command register PCD = Program Command PMA = Address of memory to be programmed BA = Address of BufferRAM to write the data...
  • Page 156 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.13 2X Program Operation Timing Address Setting ..ADQ0~ 1st data input ADQ15 4KB data into 2 DataRAMs Ongoing Status 2X program Command A1 : Address of DataRAM to be written. INT: Indicator for DataRAM’s Status (Ready=High, Busy=Low) Ongoing Status : Indicated by OnGo bit in Controller Status Register [15] (F240h) 4KB data input : Asynch Write / Synch Write available.
  • Page 157 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.14 2X Cache Program Operation Timing - 157 -...
  • Page 158 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.15 2X Interleave Cache Program Operation Timing - 158 -...
  • Page 159 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.16 Block Erase Operation Timing See AC Characteristics Tables 5.5, 5.7 and 5.9. Erase Command Sequence AAVDS AVDP AAVDH A/DQ0: A/DQ15 Hi-Z NOTE : 1) AA = Address of address register CA = Address of command register ECD = Erase Command EMA = Address of memory to be erased SA = Address of status register AA* = Address of Start Address1 Register(for Flash Block Address)
  • Page 160 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.17 Cold Reset Timing POR triggering level System Power MuxOneNAND Sleep Operation INT bit IOBE bit INTpol bit NOTE : 1) Bootcode copy operation starts 400us later than POR activation. The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data. 2) 1K bytes Bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of NAND Flash array to BootRAM.
  • Page 161 MuxOneNAND2G(KFM2G16Q2A-DEBx) FLASH MEMORY MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.18 Warm Reset Timing See AC Characteristics Tables 5.6. CE, OE Ready1 High-Z High-Z Ready2 Operation Idle Reset Ongoing BootRAM Access INT Bit Polling Idle Status NOTE : 1) The status which can accept any register based operation(Load, Program, Erase command, etc.). 2) The status where reset is ongoing.
  • Page 162 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.19 Hot Reset Timing See AC Characteristics Tables 5.6. BP(Note 3) ADQi or F220h High-Z MuxOneNAND Operation or Idle Operation NOTE : 1) Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept unchanged after Warm/Hot reset operations.
  • Page 163 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.20 NAND Flash Core Reset Timing ADQi F220h High-Z MuxOneNAND Operation or Idle Operation 6.21 Data Protection Timing During Power Down The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin provides hardware protection and is recommended to be kept at V before Vcc drops to 1.5V typ.
  • Page 164 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.22 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low) See AC Characteristics Table 5.5 AVDO A/DQ0: A/DQ15 AAVDS AAVDH AVDP NOTE : 1) VA=Valid Read Address, RD=Read Data. 2) Before IOBE is set to 1, RDY and INT pin are High-Z state. 3) Refer to chapter 5.5 for tASO description and value.
  • Page 165 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 6.24 INT auto mode See AC Characteristics Tables 5.10. INT pin INT bit Write command into INT will automatically Command Register turn to Busy State . . . NOTE : INT pin polarity is based on ‘IOBE=1 and INT pol=1 (default)’ setting INT will automatically turn back to ready state when designated operation is completed.
  • Page 166 From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system are included in this section. Contact your Samsung Representative to determine if additional notes are available. 7.1 Methods of Determining Interrupt Status There are two methods of determining Interrupt Status on the MuxOneNAND.
  • Page 167 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.1 The INT Pin to a Host General Purpose I/O INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation. COMMAND This can be configured to operate either synchronously or asynchronously as shown in the diagrams below. Synchronous Mode Using the INT Pin When operating synchronously, INT is tied directly to a Host GPIO.
  • Page 168 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.2 Polling the Interrupt Register Status Bit An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT pin. When using interrupt register instead of INT pin, INT pin is recommended to float to avoid power consumption at IOBE=0(disable). This can be configured in either a synchronous mode or an asynchronous mode.
  • Page 169 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.1.3 Determining Rp Value (DDP, QDP only) For general operation, INT operates as normal output pin, so that tF is equivalent to tR (below 10ns). But since INT operates as open drain with 50K ohm for Reset (Hot/Warm/NAND Flash Core) operations and ‘2X program operation(007Dh)’ case at DDP option, the pull-up resis- tor value is related to tr(INT).
  • Page 170 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Vcc or Vccq ~50k ohm NOTE : 1) Refer to chapter 2.8.10 Start Address Register F101h DDP Block Diagram KFN4G16Q2A @ Vcc = 1.8V, Ta = 25°C , C 1.76 Ibusy 0.1059 tf[us] 2.976 tr[ns] INT pol = ‘Low’ Ready = 30pF 1.989...

  • Page 171: Boot Sequence

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 7.2 Boot Sequence One of the best features MuxOneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader despite the fact that its core architecture is based on NAND Flash. Thus, MuxOneNAND does not make any additional booting device necessary for a system, which imposes extra cost or area overhead on the overall system.
  • Page 172 MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) Block 2047 Reservoir Reservoir File System File System Block 162 Block 162 Os Image Os Image Block 2 Block 2 NBL3 Block 1 Block 1 NBL1 NBL2 Block 0 Block 0 Reservoir File System Os Image NAND Flash Array NOTE : Step 2 and Step 3 can be copied into DRAM through two DataRAMs using dual buffering Partition 6...

  • Page 173: Package Dimensions

    MuxOneNAND2G(KFM2G16Q2A-DEBx) MuxOneNAND4G(KFN4G16Q2A-DEBx) 8.0 PACKAGE DIMENSIONS 10.00 ±0.10 TOP VIEW 10.00 ±0.10 TOP VIEW 10.00 0.10 MAX 0.80x9=7.20 (Datum A) 5 4 3 (Datum B) 3.60 0.32 ±0.05 ±0.10 BOTTOM VIEW 63- ∅ 0.45 ±0.05 ∅ 0.20 2G product (KFM2G16Q2A) 10.00 0.10 MAX 0.80x9=7.20 (Datum A)

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