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Samsung FLEX-MUXONENAND KFKAGH6Q4M Specifications

4gb flex-muxonenand m-die flash memory
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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
.
4Gb Flex-MuxOneNAND M-die
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Flex-MuxOneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be
claimed as the property of their rightful owners.
* Samsung Electronics reserves the right to change products or specification without notice.
KFM4GH6Q4M
KFN8GH6Q4M
KFKAGH6Q4M
- 1 -
FLASH MEMORY

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Summary of Contents for Samsung FLEX-MUXONENAND KFKAGH6Q4M

  • Page 1 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

  • Page 2: Revision History

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Revision History Document Title Flex-MuxOneNAND Revision History Revision No. History 1. Initial issue. 1. Corrected errata. 2. Chapter 1.3 Product Features revised. 3. Chapter 2.8.16 Start Address8 Register F107 revised. 4. Chapter 2.8.18 Command Register F220h revised. 5.

  • Page 3: Flash Memory

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Revision History Revision No. History 1. Corrected errata. 2. Chapter 2.1 Detailed Product Description revised. 3. Chapter 2.2 Definitions revised. 4. Chapter 2.8.3 Device ID Register F001h(R) revised. 5. Chapter 2.8.8 Technology Register F006h(R) revised. 6. Chapter 2.8.10 Start Address2 Register F101h(R/W) revised. 7.

  • Page 4: Ordering Information

    Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 1.0 INTRODUCTION This specification contains information about the Samsung Electronics Company Flex-MuxOneNAND tion 1.0 includes a general overview, revision history, and product ordering information. Section 2.0 describes the Flex-MuxOneNAND device. Section 3.0 provides information about device operation. Electrical specifications and timing waveforms are in Sections 4.0 through 6.0.

  • Page 5: General Overview

    NOR. The NOR Flash host interface makes Flex-MuxOneNAND an ideal solution for mobile applications that have large, advanced multimedia applications and operating systems and need high performance. When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance, small footprint solution.

  • Page 6: Product Features

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 1.3 Product Features Device Architecture • Design Technology: • Supply Voltage: • Host Interface: • 5KB Internal BufferRAM: • NAND Array: Device Performance • Host Interface Type: • Programmable Burst Read Latency: • Multiple Reset Modes: • Low Power Dissipation: •...

  • Page 7: Device Description

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.0 DEVICE DESCRIPTION 2.1 Detailed Product Description The Flex-MuxOneNAND is an advanced generation, high-performance MLC NAND-based Flash memory(Which can be programmed as both SLC and MLC). It integrates on-chip a convertible(SLC and MLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page buffer for the Flash array, and a one-time-programmable block.
  • Page 8 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.3 Pin Configuration 2.3.1 4Gb (KFM4GH6Q4M) / 8Gb (KFN8GH6Q4M) 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA(4Gb) 63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA (8Gb) ADQ1 ADQ2 ADQ3 ADQ7 ADQ14 ADQ6...
  • Page 9 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.3.2 16Gb Product (KFKAGH6Q4M) (TBD) 63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch FBGA ADQ1 ADQ2 ADQ3 ADQ7 ADQ14 ADQ6 Core ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 ADQ0 ADQ15 ADQ10 ADQ9 ADQ13 INT2 INT1 (TOP VIEW, Balls Facing Down) 63ball FBGA OneNAND Chip - 9 - FLASH MEMORY...

  • Page 10: Pin Description

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.4 Pin Description Pin Name Type Host Interface Multiplexed Address/Data bus - Inputs for addresses during read operation, which are for addressing BufferRAM & Register. ADQ15~ADQ0 - Inputs data during program and commands for all operations, outputs data during memory array/ register read cycles.

  • Page 11: Block Diagram

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.5 Block Diagram ADQ15~ADQ0 CE / CE1 INT/INT1 INT2 2.6 Memory Array Organization The Flex-MuxOneNAND architecture integrates several memory areas on a single chip. 2.6.1 Internal (NAND Array) Memory Organization The on-chip internal memory is a convertible(SLC and MLC) NAND array used for data storage and code. The internal memory is divided into a main area and a spare area.
  • Page 12 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Internal Memory Array Information Area Main(SLC) Main(MLC) Spare(SLC) Spare(MLC) Internal Memory Array Organization Sector0 Sector1 Sector2 Sector3 Sector4 Sector5 Sector6 Sector7 Sector0 Sector1 Sector2 Sector3 Sector4 Sector5 Sector6 Sector7 4KB Page63 Block Page 256KB 512KB 128B 16KB Sector Main Area 512B...
  • Page 13 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.6.2 External (BufferRAM) Memory Organization The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering. The BootRAM is a buffer that receives Boot Code from the internal memory and makes it available to the host at start up. There are 4KB bi-directional data buffers(2KB x2), DataRAM0 and DataRAM1.
  • Page 14 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.7 Memory Map The following tables are the memory maps for the Flex-MuxOneNAND. 2.7.1 Internal (NAND Array) Memory Organization The following tables show the Internal Memory address map in word order. Block Address Page Address Block [F100h] [F107h] Block0 0000h...
  • Page 15 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block64 0040h Block65 0041h Block66 0042h Block67 0043h Block68 0044h Block69 0045h Block70 0046h Block71 0047h Block72 0048h Block73 0049h Block74 004Ah Block75 004Bh Block76 004Ch Block77 004Dh Block78 004Eh SLC: 0000h~00FCh, Block79...
  • Page 16 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block128 0080h Block129 0081h Block130 0082h Block131 0083h Block132 0084h Block133 0085h Block134 0086h Block135 0087h Block136 0088h Block137 0089h Block138 008Ah Block139 008Bh Block140 008Ch Block141 008Dh Block142 008Eh SLC: 0000h~00FCh, Block143...
  • Page 17 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block192 00C0h Block193 00C1h Block194 00C2h Block195 00C3h Block196 00C4h Block197 00C5h Block198 00C6h Block199 00C7h Block200 00C8h Block201 00C9h Block202 00CAh Block203 00CBh Block204 00CCh Block205 00CDh Block206 00CEh SLC: 0000h~00FCh, Block207...
  • Page 18 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block256 0100h Block257 0101h Block258 0102h Block259 0103h Block260 0104h Block261 0105h Block262 0106h Block263 0107h Block264 0108h Block265 0109h Block266 010Ah Block267 010Bh Block268 010Ch Block269 010Dh Block270 010Eh SLC: 0000h~00FCh, Block271...
  • Page 19 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block320 0140h Block321 0141h Block322 0142h Block323 0143h Block324 0144h Block325 0145h Block326 0146h Block327 0147h Block328 0148h Block329 0149h Block330 014Ah Block331 014Bh Block332 014Ch Block333 014Dh Block334 014Eh SLC: 0000h~00FCh, Block335...
  • Page 20 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block384 0180h Block385 0181h Block386 0182h Block387 0183h Block388 0184h Block389 0185h Block390 0186h Block391 0187h Block392 0188h Block393 0189h Block394 018Ah Block395 018Bh Block396 018Ch Block397 018Dh Block398 018Eh SLC: 0000h~00FCh, Block399...
  • Page 21 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block448 01C0h Block449 01C1h Block450 01C2h Block451 01C3h Block452 01C4h Block453 01C5h Block454 01C6h Block455 01C7h Block456 01C8h Block457 01C9h Block458 01CAh Block459 01CBh Block460 01CCh Block461 01CDh Block462 01CEh SLC: 0000h~00FCh, Block463...
  • Page 22 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block512 0200h Block513 0201h Block514 0202h Block515 0203h Block516 0204h Block517 0205h Block518 0206h Block519 0207h Block520 0208h Block521 0209h Block522 020Ah Block523 020Bh Block524 020Ch Block525 020Dh Block526 020Eh SLC: 0000h~00FCh, Block527...
  • Page 23 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block576 0240h Block577 0241h Block578 0242h Block579 0243h Block580 0244h Block581 0245h Block582 0246h Block583 0247h Block584 0248h Block585 0249h Block586 024Ah Block587 024Bh Block588 024Ch Block589 024Dh Block590 024Eh SLC: 0000h~00FCh, Block591...
  • Page 24 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block640 0280h Block641 0281h Block642 0282h Block643 0283h Block644 0284h Block645 0285h Block646 0286h Block647 0287h Block648 0288h Block649 0289h Block650 028Ah Block651 028Bh Block652 028Ch Block653 028Dh Block654 028Eh SLC: 0000h~00FCh, Block655...
  • Page 25 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block704 02C0h Block705 02C1h Block706 02C2h Block707 02C3h Block708 02C4h Block709 02C5h Block710 02C6h Block711 02C7h Block712 02C8h Block713 02C9h Block714 02CAh Block715 02CBh Block716 02CCh Block717 02CDh Block718 02CEh SLC: 0000h~00FCh, Block719...
  • Page 26 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block768 0300h Block769 0301h Block770 0302h Block771 0303h Block772 0304h Block773 0305h Block774 0306h Block775 0307h Block776 0308h Block777 0309h Block778 030Ah Block779 030Bh Block780 030Ch Block781 030Dh Block782 030Eh SLC: 0000h~00FCh, Block783...
  • Page 27 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block832 0340h Block833 0341h Block834 0342h Block835 0343h Block836 0344h Block837 0345h Block838 0346h Block839 0347h Block840 0348h Block841 0349h Block842 034Ah Block843 034Bh Block844 034Ch Block845 034Dh Block846 034Eh SLC: 0000h~00FCh, Block847...
  • Page 28 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block896 0380h Block897 0381h Block898 0382h Block899 0383h Block900 0384h Block901 0385h Block902 0386h Block903 0387h Block904 0388h Block905 0389h Block906 038Ah Block907 038Bh Block908 038Ch Block909 038Dh Block910 038Eh SLC: 0000h~00FCh, Block911...
  • Page 29 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block Address Page Address Block [F100h] [F107h] Block960 03C0h Block961 03C1h Block962 03C2h Block963 03C3h Block964 03C4h Block965 03C5h Block966 03C6h Block967 03C7h Block968 03C8h Block969 03C9h Block970 03CAh Block971 03CBh Block972 03CCh Block973 03CDh Block974 03CEh SLC: 0000h~00FCh, Block975...
  • Page 30 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.7.2 Internal Memory Spare Area Assignment The figure below shows the assignment of the spare area in the Internal Memory NAND Array. Main Main Main Main area area area area 256W 256W 256W 256W 256W Note1 Note1 Note2 Note2 Note2 Note2 Note3 Note3 Note3 Note3 Note3 Note3 Spare Area Assignment in the Internal Memory NAND Array Information Word Byte...
  • Page 31 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.7.3 External Memory (BufferRAM) Address Map The following table shows the External Memory address map in Word and Byte Order. Note that the data output is unknown while host reads a register bit of reserved area and dual buffering is not applicable. Address Address Division...
  • Page 32 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.7.4 External Memory Map Detail Information The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas. • BootRAM(Main area) -0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB 0000h~00FFh(512B) BootM 0 (sector 0 of page 0/block 0) •...
  • Page 33 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.7.5 External Memory Spare Area Assignment Word Byte Buf. Address Address BootS 0 8000h 10000h 8001h 10002h 8002h 10004h 8003h 10006h 8004h 10008h 8005h 1000Ah 8006h 1000Ch 8007h 1000Eh BootS 1 8008h 10010h 8009h 10012h 800Ah 10014h 800Bh 10016h 800Ch...
  • Page 34 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Word Byte Buf. Address Address DataS 0_2 8020h 10040h 8021h 10042h 8022h 10044h 8023h 10046h 8024h 10048h 8025h 1004Ah 8026h 1004Ch 8027h 1004Eh DataS 0_3 8028h 10050h 8029h 10052h 802Ah 10054h 802Bh 10056h 802Ch 10058h 802Dh 1005Ah 802Eh 1005Ch 802Fh...
  • Page 35 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Word Byte Buf. Address Address DataS 1_3 8048h 10090h 8049h 10092h 804Ah 10094h 804Bh 10096h 804Ch 10098h 804Dh 1009Ah 804Eh 1009Ch 804Fh 1009Eh NOTE : In case of ‘with ECC’ mode, Flex-MuxOneNAND automatically generates ECC code for both main and spare data of memory during program operation, but does not update ECC code to spare bufferRAM during load operation.
  • Page 36 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8 Registers Section 2.8 of this specification provides information about the Flex-MuxOneNAND4G registers. 2.8.1 Register Address Map This map describes the register addresses, register name, register description, and host accessibility. Address Address (word order) (byte order) F000h 1E000h F001h 1E002h...
  • Page 37 Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.2 Manufacturer ID Register F000h (R) This Read register describes the manufacturer's identification. Samsung Electronics Company manufacturer's ID is 00ECh. F000h, default = 00ECh 2.8.3 Device ID Register F001h (R) This Read register describes the device. F001h, see table for default.
  • Page 38 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.4 Version ID Register F002h This register is reserved for future use. 2.8.5 Data Buffer Size Register F003h (R) This Read register describes the size of the Data Buffer. F003h, default = 0800h DataBufSize - 38 - FLASH MEMORY...
  • Page 39 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.6 Boot Buffer Size Register F004h (R) This Read register describes the size of the Boot Buffer. F004h, default = 0200h Register Information BootBufSize 2.8.7 Amount of Buffers Register F005h (R) This Read register describes the number of each Buffer. F005h, default = 0201h DataBufAmount Number of Buffers Information...
  • Page 40 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.9 Start Address1 Register F100h (R/W) This Read/Write register describes the NAND Flash block address which will be loaded, programmed, or erased. F100h, default = 0000h Reserved(00000) Device 8Gb DDP NOTE : For QDP, See Section 7.4 Start Address1 Information Register Information 2.8.10 Start Address2 Register F101h (R/W)
  • Page 41 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.16 Start Address8 Register F107h (R/W) This Read/Write register describes the NAND Flash start page address in a block for a page load, program operation and the NAND Flash start sector address in a page for a load, or program operation. F107h, default = 0000h Reserved (0000000) Start Address8 Information...
  • Page 42 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Sector allocation according to BSC(CASE1 : FSA=00) BSC = 000 Sector0 Sector1 Sector0 Sector0 BSC = 001 BSC = 001 Sector0 Sector0 Sector1 Sector1 BSC = 010 BSC = 010 Sector0 Sector0 Sector1 Sector1 BSC = 011 BSC = 011 Sector0 Sector1...
  • Page 43 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.18 Command Register F220h (R/W) Command can be issued by two following methods, and user may select one way or the other to issue appropriate command; 1. Write command into Command Register when INT is at ready state. INT will automatically turn to busy state as command is issued. Once the desired operation is completed, INT will go back ready state.
  • Page 44 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.18.1 Two Methods to Clear Interrupt Register in Command Input To clear Interrupt Register in command input, user may select one from either following methods. First method is to turn INT to low by manually writing 0000h to INT bit of Interrupt Register. Second method is to input command while INT is high, and the device will automatically turn INT to low.
  • Page 45 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.19 System Configuration 1 Register F221h (R, R/W) This Read/Write register describes the system configuration. F221h, default =40C0h BRWL Read Mode (RM) Read Mode Information[15] Item Burst Read Write Latency (BRWL) BRWL 000~010 100 (default) * Default value of BRWL and HF value is BRWL=4, HF=0. For host frequency over 66MHz, BRWL should be 6 or 7 while HF is 1.
  • Page 46 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Burst Length (BL) Host must follow burst length set by BL when reading data in synchronous burst read. 101~111 NOTE : 1) In case of BootRAM : Main=512word, Spare=16word In case of DataRAM : Main=1Kword, Spare=32word Burst Length (BL) Information[11:9] Item Error Correction Code (ECC) Information[8] Item...
  • Page 47 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) I/O Buffer Enable (IOBE) IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid after IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register. I/O Buffer Enable Information[5] Item IOBE...
  • Page 48 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Write Mode (WM) Write Mode Information[1] Item MRS(Mode Register Setting) Description Other Cases NOTE : 1) Operation not guaranteed for cases not defined in above table. Boot Buffer Write Protect Status(BWPS) Boot Buffer Write Protect Status Information[0] Item BWPS Write Mode...
  • Page 49 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.20 System Configuration 2 Register F222h This register is reserved for future use. 2.8.21 Controller Status Register F240h (R) This Read register shows the overall internal status of the Flex-MuxOneNAND and the controller. F240h, default = 0000h OnGo Reserved(0000) Error...
  • Page 50 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) OTP Lock Status (OTP This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against accidental re-programming of data stored in the OTP block. The OTP status bit is automatically updated at power-on.
  • Page 51 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Controller Status Register Output Modes [15] [14] Mode OnGo Operation Ongoing Operation OK Operation Fail Program fail on Cache Program Previous program fail during Cache Program Program fail after Finish Cache Program Reset during Program/Erase/Load Program/Erase to the locked block, Load to the BootRAM OTP Program Fail(Lock) OTP Program Fail...
  • Page 52 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Read Interrupt (RI) This is the Read interrupt bit. RI Interrupt [7] Status Conditions At the completion of a Load, Superload or LSB Page sets itself to ‘1’ Recovery Read Operation. (0000h, 0003h or 0005h) ‘0’ is written to this bit, Cold/Warm/Hot reset is being performed, or clears to ‘0’...
  • Page 53 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Reset Interrupt (RSTI) This is the Reset interrupt bit. RSTI Interrupt [4] Status Conditions At the completion of an Reset Operation sets itself to ‘1’ (00B0h, 00F0h, 00F3h or warm reset is released) ‘0’ is written to this bit, or clears to ‘0’...
  • Page 54 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 2.8.26 ECC Status Register 1 FF00h (R) This Read register shows the Error Correction Status. The Flex-MuxOneNAND can correct up to 4-bit errors. ECC can be performed on the NAND Flash main and spare memory areas. The ECC status register can also show the number of errors in a sector as a result of an ECC check in during a load operation.
  • Page 55 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.0 DEVICE OPERATION This section of the data sheet discusses the operation of the Flex-MuxOneNAND device. It is followed by AC/DC Characteristics and Timing Diagrams which may be consulted for further information. The Flex-MuxOneNAND supports a limited command-based interface in addition to a register-based interface for performing operations on the device.
  • Page 56 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.1.1 Reset Flex-MuxOneNAND Command The Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device. 3.1.2 Load Data Into Buffer Command Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing 00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0 and DataRAM1.
  • Page 57 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.2 Device Bus Operation The device bus operations are shown in the table below. Operation Standby Warm Reset Asynchronous Write Asynchronous Read Start Initial Burst Read Burst Read Terminate Burst Read Cycle Terminate Burst Read Cycle via RP Terminate Current Burst Read Cycle and Start New Burst Read Cycle...
  • Page 58 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.3 Reset Mode Operation The Flex-MuxOneNAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Array Reset. Section 3.3 discusses the operation of these reset modes. The Register Reset Table shows the which registers are affected by the various types of Reset operations. Internal Register Reset Table Internal Registers F000h...
  • Page 59 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.3.1 Cold Reset Mode Operation See Timing Diagram 6.15 At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal. This trig- gers boot code loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from the beginning of memory into the BootRAM.
  • Page 60 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.4 Write Protection Operation The Flex-MuxOneNAND can be write-protected to prevent re-programming or erasure of data. The areas of write-protection are the BootRAM, and the NAND Flash Array. 3.4.1 BootRAM Write Protection Operation At system power-up, voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal which trig- gers boot code loading.
  • Page 61 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.4.3.1 Unlocked NAND Array Write Protection State An Unlocked block can be programmed or erased. The status of an unlocked block can be changed to locked or locked-tight using the appro- priate software command(Locked-tight state can be achieved in 2 steps. First, the block should be locked via the lock command. Then, Lock tight command must be issued.).
  • Page 62 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.4.3.3 Locked-tight NAND Array Write Protection State A block that is in a locked-tight state can only be changed to locked state after a Cold or Warm Reset. Unlock and Lock command sequences will not affect its state. This is an added level of write protection security. A block must first be set to a locked state before it can be changed to locked-tight using the Lock-tight command.
  • Page 63 DQ[10]=Error DQ[10]=0? Lock/Unlock/Lock-Tight completed completed * Samsung strongly recommends to follow the above flow chart NOTE : 1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1 Start Command * DBS, DFS is for DDP...
  • Page 64 Add: F241h DQ[15]=INT Read Controller Status All Block Unlock *Samsung strongly recommends to follow the above flow chart NOTE : 1) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1 2) All Block Unlock command fails if there are lock-tight blocks in flash.
  • Page 65 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.5 Data Protection During Power Down Operation See Timing Diagrams 6.19 The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin which provides hardware protection is recommended to be kept at VIL before Vcc drops to 1.5V. 3.6 Load Operation See Timing Diagrams 6.9 The Load operation is initiated by setting up the start address from which the data is to be loaded.
  • Page 66 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.6.1 Superload Operation See Timing Diagrams 6.10 The Superload operation is used to read multiple pages. During Superload operation, up to 4bit errors are corrected. Once the first data is loaded, an interrupt status returns to ready. The data in DataRAM should be read after next Superload command is issued.
  • Page 67 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.6.2 LSB Page Recovery Read MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has lower page address and MSB page has higher page address in paired pages. If power off occurs during MSB page program, the paired LSB page data can become corrupt. LSB page recovery read is a way to read LSB page though page data are corrupted.
  • Page 68 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.7 Read Operation See Timing Diagrams 6.1,6.2, 6.3 and 6.4. The device has two read modes; Asynchronous Read and Synchronous Burst Read. The initial state machine automatically sets the device into the Asynchronous Read Mode (RM=0) to prevent the spurious altering of memory content upon device power up or after a Hardware reset.
  • Page 69 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.7.2.1 Continuous Linear Burst Read Operation See Timing Diagram 6.2 First Clock Cycle The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the system by pulsing high.
  • Page 70 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.7.2.3 Programmable Burst Read Latency Operation See Timing Diagrams 6.1 and 6.2 Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks. The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with the (n+1)th rising edge.
  • Page 71 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.8 Synchronous Write(RM=1, WM=1) See Timing Diagram 6.6, 6.7 and 6.8 Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE goes low, the address to access is latched on the next rising edge of clk that ADV is low. During this first clock rising edge, WE indicates whether the operation is going to be a read (WE = high) or write (WE = low).
  • Page 72 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.9 Program Operation See Timing Diagrams 6.11 The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array. The device has two 2KB data buffers, 1 Page (4KB + 128B) in size. A page has 8 sectors of 512B each main area and 16B spare area. The device can be programmed in units of 8 sectors at once.
  • Page 73 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Paired Page Address Information In case of MLC partition, when Program, Cache Program, Interleave cache program, Copy-back with random data in operations are abnor- mally aborted(eg. power-down), not only page data under program but also paired page data may be damaged. Paired Page Address Paired Page Address 17h.
  • Page 74 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Pairing of pages in MLC block: Represents a Page number XX in an MLC block Represents Pairing of pages in an MLC block FLASH MEMORY . . . - 74 -...
  • Page 75 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Program Operation Flow Diagram Start Select DataRAM for DDP Add: F101h DQ=DBS* Write Data into DataRAM ADD: DataRAM DQ=Data(4KB) Data Input Completed? Write ‘DFS*, FBA’ of Flash Add: F100h DQ=DFS*, FBA Read Write Protection Status Add: F24Eh DQ=US,LS,LTS Write ‘FPA, FSA’...
  • Page 76 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Program Interleave(@DDP) Flow Chart Start Select DataRAM for DDP Add: F101h DQ=DBS* Write Data into DataRAM Add: DataRAM, DQ=Data(4KB) Write ‘DFS*, FBA’ of Flash Add: F100h DQ=DFS*, FBA Read Write Protection Status Add: F24Eh DQ=US,LS,LTS Write ‘FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ‘BSA, BSC’...
  • Page 77 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.9.1 Cache Program Operation See Timing Diagram 6.12 The Cache Program is to enhance the performance of Program Operation. Employing Cache Program operation, transfer time from Host to DataRAM can be shadowed, therefore write performance will increase. In Cache Program, since 4KB data is to be programmed into NAND Flash Array in another advanced way.
  • Page 78 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Cache Program Operation Flow Diagram Start Select DataRAM for DDP Add: F101h DQ=DBS Write Data into DataRAM0,1 Add: DataRAM DQ=Data(4KB) Write ‘DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA Read Write Protection Status Add: F24Eh DQ=US,LS,LTS Write ‘FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ‘BSA , BSC’...
  • Page 79 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.9.2 Interleave Cache Program Operation The Interleave Cache Program is available only on DDP. Host can write data on a chip while programming another chip with this operation. Interleave Cache Program is executing as following: 1. 4KB Data are written from host to DataRAMs in Chip1. 2.
  • Page 80 5) Host is strongly recommended to see the INT register(F241h) of each chip. 6) Once ‘PGM command’ is issued onto a chip, the same command(PGM) must be issued onto another chip. If not, Samsung cannot gurantee the following oper- ation.
  • Page 81 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.10 Copy-Back Program Operation with Random Data Input The Copy-Back Program Operation with Random Data Input in Flex-MuxOneNAND consists of 3 phases, Load data into DataRAM, Modify data and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the host, then programmed into the destination page.
  • Page 82 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.11 Erase Operation 3.11.1 Block Erase Operation See Timing Diagram 6.14 The device can be erased one block at a time. To erase a block is to write all 1's into the desired memory block by executing the Internal Erase Routine.
  • Page 83 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Erase Interleave (@DDP) Flow Chart Start Write ‘DFS*, FBA’ of Flash Add: F100h DQ=DFS*, FBA Select DataRAM for DDP Add: F101h DQ=DBS* Write ‘Erase’ Command Add: F220h DQ=0094h Select DataRAM for DDP Add: F101h DQ=DBS* Check for INT register high Add: F241h DQ[15]=INT INT=1(Ready) Write ‘DFS*, FBA’...
  • Page 84 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.11.2 Erase Suspend / Erase Resume Operation The Erase Suspend/Erase Resume Commands interrupt and restart a Block Erase operation so that user may perform another urgent opera- tion on the block that is not being designated by Erase Operation. Erase Suspend During a Block Erase Operation When Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 500us to suspend erase opera- tion.
  • Page 85 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.12 Partition Information (PI) Block (SLC Only) One Block of the SLC NAND Flash Array memory is reserved for Partition Information (PI) Block. The block can be read, programmed and erased using the same operations as any other NAND Flash Array memory block. Only Load, Erase and Program can be performed.
  • Page 86 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.12.1 PI Block Boundary Information setting It is 1st word of sector0 of page0 of main area of PI Block. The Lock bits for PI Block and Boundary address of SLC and MLC are stored. After shipment, it is initially programmed as data FC00h(Lock bit[15:14]: 11b(binary), Boundary address[9:0]: 000h). To change PI Block contents (i.e, lock bits and boundary address), Erase/Program sequence should be followed as below.
  • Page 87 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.12.1.1 PI Block Access mode entry The PI area is a separate part of the NAND Flash Array memory. It is accessed by issuing PI Access command(66h) instead of writing a Flash Block Address(FBA) in the StartAddress1 register. After being accessed through the PI Access Command, the contents of PI memory area can be programmed, erased or loaded using the same operations as a normal program, erase or load operation to the NAND Flash Array memory.
  • Page 88 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.12.1.2 PI Block Erase The PI Block Erase Operation erases the entire PI block including Partition Information. PI Block Access mode entry must be done before issuing Erase operation for PI Block. Erasing the PI Area • Issue the PI Access Command(Refer to Chapter 3.12.1.1). •...
  • Page 89 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.12.1.3 PI Block Program Operation The PI Block Program Operation accesses the PI area and programs content from the DataRAM on-chip buffer to the designated page(s) of the PI. A memory location in the PI area can be program. The PI area is programmed using the same sequence as normal program operation after being accessed by the PI Block Access mode entry command (see section 3.8 for more information).
  • Page 90 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.12.1.4 PI Update Once new partition information is programmed into the PI block, an internal register that is invisible to users must be updated for the changes in PI to be applied. This internal register which stores partition information(i.e. the last address of SLC area and lock bits) will be automatically updated through cold reset.
  • Page 91 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.12.2 PI Block Load Operation PI Block Load Operation accesses the PI area and transfers identified content from the PI to the DataRAM on-chip buffer, thus making the PI contents available to the Host. The PI area is a separate part of the NAND Flash Array memory. It is accessed by issuing PI Access command(66h). After being accessed with the PI Access Command, the contents of PI memory area are loaded using the same operations as a normal load operation to the NAND Flash Array memory (see section 3.6 for more information).
  • Page 92 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.13 OTP Operation (SLC only) One Block of the NAND Flash Array memory is reserved as a One-Time Programmable Block memory area. Also, 1st Block of NAND Flash Array can be used as OTP. OTP area and 1st block OTP area must be utilized as a SLC block. The OTP block can be read, programmed and locked using the same operations as any other NAND Flash Array memory block.
  • Page 93 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) OTP Block Area Structure Sector(main area):512B One Block: 64pages 256KB+8KB 1st Block OTP Area Structure Sector(main area):512B One Block: 64pages 256KB+8KB FLASH MEMORY Page:4KB+128B Sector(spare area):16B Page:4KB+128B Sector(spare area):16B - 93 - Manufacturer Area : 14pages page 50 to page 63 User Area : 50pages page 0 to page 49...
  • Page 94 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.13.1 OTP Block Load Operation An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer, thus making the OTP contents available to the Host. The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of a Flash Block Address (FBA) value in Start Address1 Register.
  • Page 95 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.13.2 OTP Block Program Operation An OTP Block Program Operation accesses the OTP area and programs content from the DataRAM on-chip buffer to the designated page(s) of the OTP. A memory location in the OTP area can be programmed only one time (no erase operation permitted). The OTP area is programmed using the same sequence as normal program operation after being accessed by the command (see section 3.9 for more information).
  • Page 96 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) OTP Block Program Operation Flow Chart Start Write ‘DFS*, FBA’ of Flash Add: F100h DQ=DFS*, FBA Select DataRAM for DDP Add: F101h DQ=DBS* Write 0 to interrupt register Add: F241h DQ=0000h Write ‘OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT...
  • Page 97 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.13.3 OTP Block Lock Operation Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any changes from being made. Unlike the main area of the NAND Flash Array memory, once the OTP block is locked, it cannot be unlocked, for locking bit for both blocks lies in the same word of OTP area.
  • Page 98 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) OTP Block Lock Operation Flow Chart Start Write ‘DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA Select DataRAM for DDP Add: F101h DQ=0000h(DBS*) Write 0 to interrupt register Add: F241h DQ=0000h Write ‘OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT...
  • Page 99 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.13.4 1st Block OTP Lock Operation 1st Block can be used as OTP, for secured booting operation. 1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP, 1st Block OTP cannot be erased or programmed.
  • Page 100 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 1st Block OTP Lock Operation Flow Chart Start Write ‘DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA Select DataRAM for DDP Add: F101h DQ=0000h(DBS*) Write 0 to interrupt register Add: F241h DQ=0000h Write ‘OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT...
  • Page 101 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.13.5 OTP and 1st Block OTP Lock Operation OTP and 1st Block can be locked simultaneously, for locking bit lies in the same word of OTP area. 1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP, 1st Block OTP cannot be erased or programmed.
  • Page 102 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) OTP and 1st Block OTP Lock Operation Flow Chart Start Write ‘DFS, FBA’ of Flash Add: F100h DQ=DFS, FBA Select DataRAM for DDP Add: F101h DQ=0000h(DBS*) Write 0 to interrupt register Add: F241h DQ=0000h Write ‘OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition...
  • Page 103 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.14 DQ6 Toggle Bit The Flex-MuxOneNAND device has DQ6 Toggle bit. Toggle bit is another option to detect whether an internal load operation is in progress or completed. Once the BufferRAM(BootRAM, DataRAM0, DataRAM1) is at a busy state during internal load operation, DQ6 will toggle. Toggling DQ6 will stop after the device completes its internal load operation.
  • Page 104 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 3.15 ECC Operation The Flex-MuxOneNAND device has on-chip ECC with the capability of correcting up to 4-bit errors in the NAND Flash Array memory main and spare areas (512+16)B. As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation, the device initiates a background operation which generates an Error Correction Code (ECC).
  • Page 105 An invalid block(s) status is defined by the 1st word in the spare area. Samsung makes sure that the first page in the block either SLC partition or MLC partition of every invalid block has non-FFFFh data at the 1st word of sector0 of pages 0 or 1 in the spare area.
  • Page 106 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Invalid Block Table Creation Flow Chart Increment Block Address Create (or update) Invalid Block(s) Table 3.16.2 Invalid Block Replacement Operation Within its life time, additional invalid blocks may develop with NAND Flash Array memory. Refer to the device's qualification report for the actual data.
  • Page 107 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Referring to the diagram for further illustration, when an error happens in the nth page of block 'A' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'B' via DataRAM. Then re-program the nth page to the nth page of block 'B' or any free block.

  • Page 108: Absolute Maximum Ratings

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 4.0 DC CHARACTERISTICS 4.1 Absolute Maximum Ratings Parameter Voltage on any pin relative to V Temperature Under Bias Storage Temperature Short Circuit Output Current Recommended Operating Temperature NOTE : 1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V@1.8V device). Maximum DC voltage may overshoot to Vcc+2.0V for periods <20ns.
  • Page 109 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 4.3 DC Characteristics Parameter Symbol Input Leakage Current Output Leakage Current Active Asynchronous Read Current (Note 2) Active Burst Read Current (Note 2) CC2R Active Burst Write Current (Note 2) CC2W Active Asynchronous Write Current (Note 2) Active Load Current (Note 3) Active Program Current (Note 3) Active Erase Current (Note 3)
  • Page 110 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 5.0 AC CHARACTERISTICS 5.1 AC Test Conditions Parameter Input Pulse Levels Input Rise and Fall Times other inputs Input and Output Timing Levels Output Load Input & Output Test Point Input Pulse and Test Point 5.2 Device Capacitance CAPACITANCE = 25 °C, V = 1.8V, f = 1.0MHz)
  • Page 111 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 5.4 AC Characteristics for Synchronous Burst Read See Timing Diagrams 6.1 and 6.2 Parameter Clock Clock Cycle Initial Access Time Burst Access Time Valid Clock to Output Delay AVD Setup Time to CLK AVD Hold Time from CLK AVD High to OE Low Address Setup Time to CLK Address Hold Time from CLK...
  • Page 112 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 5.5 AC Characteristics for Asynchronous Read See Timing Diagrams 6.3 and 6.4. Parameter Access Time from CE Low Asynchronous Access Time from AVD Low Asynchronous Access Time from address valid Read Cycle Time AVD Low Time Address Setup to rising edge of AVD Address Hold from rising edge of AVD Output Enable to Output Valid CE Setup to AVD falling edge...

  • Page 113: Table Of Contents

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 5.7 AC Characteristics for Asynchronous Write See Timing Diagrams 6.5 Parameter WE Cycle Time AVD low pulse width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time WE Pulse Width WE Pulse Width High WE Disable to AVD Enable CE Low to RDY Valid...
  • Page 114 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 5.9 AC Characteristics for Load/Program/Erase Performance See Timing Diagrams 6.9, 6.10, 6.11, 6.12, 6.13 and 6.14 Parameter Sector Load time(Note 1) Page Load time(Note 1) Page Program time(Note 1) OTP Access Time(Note 1) Lock/Unlock/Lock-tight(Note 1) All Block Unlock Time(Note 1) Erase Suspend Time(Note 1) Erase Resume Time(Note 1) Number of Partial Program Cycles in the page (Including main and...

  • Page 115: Cer

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.0 TIMING DIAGRAMS 6.1 8-Word Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5.4 BRWL = 4 RDYO AVDS AVDO AVDH A/DQ0: A/DQ15 Hi-Z 6.2 Continuous Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5.4 BRWL = 4 RDYO AVDS...
  • Page 116 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.3 Asynchronous Read (VA Transition Before AVD Low) See AC Characteristics Table 5.5 A/DQ0: A/DQ15 Hi-Z NOTE : VA=Valid Read Address, RD=Read Data. See timing diagram 6.20, 6.21 for tASO 6.4 Asynchronous Read (VA Transition After AVD Low) See AC Characteristics Table 5.5 A/DQ0: A/DQ15...
  • Page 117 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.5 Asynchronous Write See AC Characteristics Table 5.7 AAVDS AVDP ADQ15-ADQ0 Hi-Z NOTE : VA=Valid Read Address, WD=Write Data. AAVDH Valid WD - 117 - FLASH MEMORY Valid WD Hi-Z...

  • Page 118: Wds

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.6 8-Word Linear Burst Write Mode See AC Characteristics Table 5.8 BRWL = 4 RDYO AVDS AVDH A/DQ0: A/DQ15 Hi-Z 6.7 Burst Write Operation followed by Burst Read See AC Characteristics Table 5.8 BRWL = 4 RDYO AVDS AVDH A/DQ0:...
  • Page 119 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.8 Start Initial Burst Write Operation See AC Characteristics Table 5.8 BRWL = 4 RDYO AVDS AVDH A/DQ0: A/DQ15 Hi-Z CEHP CLKH CLKL RDYS RDYA - 119 - FLASH MEMORY BRWL = 4...

  • Page 120: Avdp

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.9 Load Operation Timing See AC Characteristics Table 5.7 and Table 5.9 Load Command Sequence (last two cycles) AAVDS AVDP AAVDH ADQ0~15 Hi-Z NOTE : 1) AA = Address of address register CA = Address of command register LCD = Load Command LMA = Address of memory to be loaded BA = Address of BufferRAM to load the data...
  • Page 121 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.10 Superload Operation Timing See AC Characteristics Table 5.7 and Table 5.9 Superload Operation Timing Diagram ≈ ≈ ≈ ≈ - 121 - FLASH MEMORY...
  • Page 122 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.11 Program Operation Timing See AC Characteristics Table 5.7 and Table 5.9 Program Command Sequence (last two cycles) AVDP AAVDS AAVDH A/DQ0: A/DQ15 Hi-Z NOTE : 1) AA = Address of address register CA = Address of command register PCD = Program Command PMA = Address of memory to be programmed BA = Address of BufferRAM to write the data...
  • Page 123 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) FLASH MEMORY 6.12 Cache Program Operation Timing See AC Characteristics Table 5.7 and Table 5.9 - 123 -...
  • Page 124 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) FLASH MEMORY 6.13 Interleave Cache Program Operation Timing See AC Characteristics Table 5.7 and Table 5.9 - 124 -...
  • Page 125 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.14 Block Erase Operation Timing See AC Characteristics Table 5.7 and Table 5.9 Erase Command Sequence AAVDS AVDP AAVDH A/DQ0: A/DQ15 Hi-Z NOTE : 1) AA = Address of address register CA = Address of command register ECD = Erase Command EMA = Address of memory to be erased SA = Address of status register...
  • Page 126 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.15 Cold Reset Timing POR triggering level System Power OneNAND Sleep Operation INT bit IOBE bit INTpol bit NOTE : 1) Bootcode copy operation starts 400us later than POR activation. The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data. 2) 1KB Bootcode copy and internal update operation take 250us(estimated) from sector0 and 1/page0/block0 of NAND Flash array to BootRAM.
  • Page 127 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.16 Warm Reset Timing See AC Characteristics Table 5.6 CE, OE Ready1 High-Z Operation Idle Reset Ongoing Status NOTE : 1) The status which can accept any register based operation(Load, Program, Erase command, etc). 2) The status where reset is ongoing. 3) The status allows only BootRAM(BL1) read operation for Boot Sequence.(Refer to 7.2.2 Boot Sequence) 4) To read BL2 of Boot Sequence, Host should wait INT until becomes ready.
  • Page 128 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.17 Hot Reset Timing See AC Characteristics Table 5.6 BP(Note 3) ADQi or F220h High-Z Flex-MuxOneNAND Operation or Idle Operation NOTE : 1) Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept unchanged after Warm/Hot reset operations.
  • Page 129 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.18 NAND Flash Core Reset Timing See AC Characteristics Table 5.6 ADQi F220h High-Z Flex-MuxOneNAND Operation or Idle Operation 6.19 Data Protection Timing During Power Down The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin provides hardware protection and is recommended to be kept at V before Vcc drops to 1.5V Flex-MuxOneNAND...
  • Page 130 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.20 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low) See AC Characteristics Table 5.5 AVDO A/DQ0: A/DQ15 AAVDS AAVDH AVDP Note : NOTE : 1) VA=Valid Read Address, RD=Read Data. 2) Before IOBE is set to 1, RDY and INT pin are High-Z state. 3) Refer to chapter 5.5 for tASO description and value.
  • Page 131 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 6.22 INT auto mode See AC Characteristics Table 5.10. INT pin INT bit Write command into Command Register . . . NOTE : 1) INT pin polarity is based on ‘IOBE=1 and INT pol=1 (default)’ setting INT will automatically INT will automatically turn back to ready state turn to Busy State when designated operation is completed.
  • Page 132 From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system are included in this section. Contact your Samsung Representative to determine if additional notes are available. 7.1 Methods of Determining Interrupt Status There are two methods of determining Interrupt Status on the Flex-MuxOneNAND.

  • Page 133: Clk Clk

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 7.1.1 The INT Pin to a Host General Purpose I/O INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation. COMMAND This can be configured to operate either synchronously or asynchronously as shown in the diagrams below. Synchronous Mode Using the INT Pin When operating synchronously, INT is tied directly to a Host GPIO.
  • Page 134 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 7.1.2 Polling the Interrupt Register Status Bit An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT pin. When using interrupt register instead of INT pin, INT must be unconnected This can be configured in either a synchronous mode or an asynchronous mode.
  • Page 135 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 7.1.3 Determining Rp Value (DDP, QDP Only) For general operation, INT operates as normal output pin, so that tF is equivalent to tR (below 10ns). But since INT operates as open drain with 50K ohm for Reset (Cold/Hot/Warm/NAND Flash Core) operations and ‘Cache program operation’ case at DDP option, the pull-up resis- tor value is related to tr(INT).
  • Page 136 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Vcc or Vccq ~50k ohm KFN8GH6Q4M @ Vcc = 1.8V, Ta = 25°C , C 1.76 Ibusy 0.111 tf[us] 7.53 tr[ns] INT pol = ‘Low’ Ready = 30pF 3.012 2.655 0.18 2.218 0.09 0.06 0.959 1.669 0.045 0.036 6.73 6.71...

  • Page 137: Boot Sequence

    Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 7.2 Boot Sequence One of the best features Flex-MuxOneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader despite the fact that its core architecture is based on NAND Flash. Thus, Flex-MuxOneNAND does not make any additional booting device necessary for a system, which imposes extra cost or area overhead on the overall system.
  • Page 138 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) Block 1023 Reservoir Reservoir Partition 6 Partition 6 File System File System Partition 5 Partition 5 Block 162 Block 162 Os Image Os Image Partition 4 Partition 4 Block 2 Block 2 NBL3 Partition 3 Partition 3 Block 1 Block 1 NBL2...
  • Page 139 : {0 ~ K} Blocks NOTE : 1) K is the boundary address(the end of SLC). Samsung will decide the value of K before final specification open (K=TBD). 2) For the partitionning method, samsung will support application note and guidance code.
  • Page 140 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 7.4 DDP and QDP Description DDP(Dual Die Package): 8Gb DDP Flex-OneNAND contains two chips of 4Gb which are multiplexed such that they provide a single address range interface, with dou- ble the storage capacity. Since the address range is single, the BootRAM, the bufferRAM and the register set are multiplexed. BootRAM: The bootRAM of chip1 is selected always, and the contents of the block 0 of chip1 are copied to it at startup.
  • Page 141 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 8.0 PACKAGE DIMENSIONS (TBD) 10.00 ±0.10 TOP VIEW 10.00 ±0.10 TOP VIEW 10.00 0.10 MAX 0.80x9=7.20 (Datum A) 5 4 3 (Datum B) 3.60 0.32 ±0.05 ±0.10 BOTTOM VIEW 63- ∅ 0.45 ±0.05 ∅ 0.20 4G product (KFM4GH6Q4M) 10.00 0.10 MAX 0.80x9=7.20...
  • Page 142 Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx) Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx) Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx) 10.00 ±0.10 TOP VIEW 0.10 MAX (Datum A) (Datum B) 3.60 0.32 ±0.05 ±0.10 BOTTOM VIEW 63- ∅ 0.45 ±0.05 ∅ 0.20 16G product (KFKAGH6Q4M) - 142 - FLASH MEMORY #A1 INDEX 10.00 ±0.10 0.80x9=7.20 5 4 3...

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