Hitachi Compute Rack CR 210H User Manual page 47

Lock step
A memory lock step is a function for synchronizing two channels with each other
and handling two memory boards as a single memory board logically. Normal
access of 64-bit data/8-bit ECC is expanded to 128-bit data/16-bit ECC for
operation. This allows enhancement of multi-bit error detection and correcting
functions by Single Device Data Correction (SDDC).
Typically, the memory controller supports x4 SDDC (able to correct a 4-bit DRAM
device failure) and also using the lock step function allows support of x8 SDDC
(able to correct an 8-bit DRAM device failure) as well as detection of two 4-bit
DRAM device failures.
These are the following conditions for using the lock step function:
Memory boards should be of the same configuration for channels 0 and 1 as

well as channels 2 and 3 of each processor.
All memory boards should have the same capacity and same model.

When two processors are installed, the same memory configuration should be

applied to processor 1 and processor 2.
SDDC is also referred to as advanced ECC, which assigns the data of each DRAM
chip to individual ECC controllers so that a single DRAM chip does not affect one
or more bits of data to be processed on an ECC basis.
If the entire one DRAM chip fails, an error occurs on multiple bits. Each ECC
controller can handle such an error as a 1-bit error for error correction.
The x4 SDDC functions image is as follows.
Figure 3-18: The function of x4 SDDC
System Unit Functions
Hitachi Compute Rack 210H User's Guide
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