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DIC6 shares the data bus of micom with other devices(DVD1, EPROM, SRAM). CH2 shows the measurement of a
signal line of data bus. The inclining and rising part in CH2 indicates high impedence state after data bus floating.
The data bus is pulled up by 4.7K resistance.
It shows access in fast page mode as waveform when DIC1 accesses external memory(4Mbit DRAM) at DVD
refresh.
WR
OE
RAS
CAS
ADRS
DATA
It shows the external memory refresh of DIC1 and uses Cas Before Ras Refresh.
RAS
CAS
It shows refresh per approx. 31 usec as measurement of refresh waverform outputted by DIC1 in large timing.
RAS
CAS
Samsung Electronics
Fig. 2-40
Fig. 2-41
Fig. 2-42
Fig. 2-43
¥ CH1 : ALE (MIC4-11, Address latch enable
signal)
¥ CH2 : HAD0-7 (MIC402 to 9, Main micom
address and data multiplexed bus)
1
¥ CH3 : HA0-7 (MIC4-19 to 12, Main micom
addreess 0-7)
2
3
¥ WE : Write enable(DIC2-7)
¥ OE : OUTPUT ENABLE (DIC2-22)
¥ RAS : RAW ADDRESS STROBE (DIC2-8)
¥ CAS : COLUMN ADDRESS STROBE (DIC2-23)
¥ ADRS : ADDRESS
¥ DATA : DATA
¥ DIC2 (4MDRAM) REFRESH TIME
Refresh time(PERIOD) of DIC2(4MDRAM)
Reference Information
2-23
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