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It shows PLL clock swung on the right and left on the basis of input RF signal, PLL clock and trigger at DVD
playback. The eye of RF signal is open in PLL lock state.
It shows RF signal and RLLD signal waveform at DVD refresh and RLLD waveform is regular as 1.65V. If a
serious error occurs in disk, RLLD signal is outputted as correction signal and enters PLL control system after
summing with phase difference signal.
RLLD signal is ouputted at disk halt or occurrence of serious error.
Samsung Electronics
Fig. 2-34
Fig. 2-35
Fig. 2-36
¥ CH1 : RFIN(DIC1-50, RF Input signal)
(Vp_p is approx. 2.5V)
¥ CH4 : PLCK (DIC1-26, PLL clock)
1
4
¥ CH1 : RFIN(DIC1-50, RF Input signal)
¥ CH2 : RLLD (DIC1-38, RLLD signal at disk
refresh)
1
2
¥ CH1 : RFIN(DIC1-50, RF Input signal)
¥ CH2 : RLLD (DIC1-38, RLLD at disk halt or
occurrence of serious error)
1
2
Reference Information
2-21
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