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Because RF signal, external VCO input voltage and VCO control voltage swings terribly at disk halt, PLL ouput
clock changes largely.(PLL not unlock state)
The input voltage of VCO becomes a regular voltage level(approx. 3.59V in Figure) at DVD playback and VCO
outpus PLL clock depending on this control voltage. The input voltage of VCO swings a little and appears as
frequency variation of VCO as much as change amount. As the control voltage of VCO is higher, PLL clock
frequency becomes high.
When the inputted RF signal is error-correction processed in DIC1 and inputted into DIC6, it is processed to release the digital
copy protection. The digital copy protection released data makes the acknowlegde signal of CH2 LOW and outputs
data(CH4)
when MPEG decoder(Video, Audio signal process chip) falls the request signal to 0(LOW) and demands data. The data
acknowledge signal of CH2 and data of CH4 are synchronized with BSTCLK(CH3) and outputted. BSTCLK of CH3 is made by
2-22
Fig. 2-37
Fig. 2-38
Fig. 2-39
¥ CH1 : RFIN(DIC1-50, RF Input signal at disk
halt)
¥ CH2 : VCO control signal (DD1-3, Variable
capacitance diode)
1
2
¥ CH1 : RFIN(DIC1-50, RF Input signal at disk
playback)
¥ CH2 : VCO control signal (DD1-3, Variable
capacitance diode)
1
2
division of 27MHz into 16.
1
¥ CH1 : PVSREQ (DIC6-13, Data request signal
from DVD1)
¥ CH2 : PVSACK (DIC6-14, Output data
2
acknowledge signal)
¥ CH3 : BSTCLK (DIC6-17, Output clock)
¥ CH4 : PVSIN (DIC6-5 to 11, Output data)
3
4
Samsung Electronics
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