Xilinx Zynq-7000 User Manual page 236

Debug Signals
Table 1-74: DDR2/DDR3 Debug Signals
Signal Name
dbg_init_calib_complete
dbg_wrlvl_start
dbg_wrlvl_done
dbg_wrlvl_err
dbg_pi_phaselock_start
dbg_pi_phaselocked_done
dbg_pi_phaselock_err
dbg_pi_dqsfound_start
dbg_pi_dqsfound_done
dbg_pi_dqsfound_err
dbg_rdlvl_start[1]
dbg_rdlvl_start[0]
dbg_rdlvl_done[1]
dbg_rdlvl_done[0]
dbg_rdlvl_err[1]
dbg_rdlvl_err[0]
dbg_oclkdelay_calib_start
dbg_oclkdelay_calib_done
dbg_wrcal_start
dbg_wrcal_done
dbg_wrcal_err
dbg_phy_init_5_0
dbg_rddata_valid_r
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Description
ILA Signals (Status)
Signifies memory initialization and calibration have completed
successfully.
Signifies the start of the Write Leveling stage of calibration.
Signifies successful completion of the Write Leveling stage of
calibration.
Signifies the Write Leveling stage of calibration exhibited errors and
did not complete.
Signifies the start of the PHASELOCK stage of calibration.
Signifies successful completion of the PHASELOCK stage of
calibration.
Signifies the PHASELOCK stage of calibration exhibited errors and did
not complete.
Signifies the start of the DQSFOUND stage of calibration.
Signifies successful completion of the DQSFOUND stage of
calibration.
Signifies the DQSFOUND stage of calibration exhibited errors and did
not complete.
Signifies the start of the MPR stage of calibration.
Signifies the start of Read Leveling Stage 1 calibration.
Signifies the successful completion of the MPR Stage of calibration.
Signifies the successful completion of Read Leveling Stage 1
calibration.
Signifies Read Leveling Stage 1 calibration exhibited errors and did not
complete
Signifies the MPR stage of calibration exhibited errors and did not
complete.
Signifies the start of the OCLKDELAY stage of calibration.
Signifies successful completion of the OCLKDELAY stage of calibration.
Signifies the start of the Write Calibration stage of calibration.
Signifies successful completion of the write calibration stage of
calibration.
Signifies write calibration exhibited errors and did not complete.
State variable for the PHY Init state machine. States can be decoded in
the ddr_phy_init module.
Asserts when the read data (dbg_rddata_r) is valid.
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