Xilinx Zynq-7000 User Manual page 193

Bank and Pin Selection Guides for DDR3 Designs
The MIG tool generates pin assignments for a memory interface based on physical layer
rules.
Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and
certain rules must be followed to use the DDR3 SDRAM physical layer. Xilinx 7 series FPGAs
have dedicated logic for each DQS byte group. Four DQS byte groups are available in each
50-pin bank. Each byte group consists of a clock-capable I/O pair for the DQS and 10
associated I/Os.
Several times in this document byte groups are referenced for address and control as well,
this refers to the 12 associated groups. In a typical DDR3 data bus configuration, eight of
these 10 I/Os are used for the DQs, one is used for the data mask (DM), and one is left over
for other signals in the memory interface.
The MIG tool should be used to generate a pinout for a 7 series DDR3 interface. The MIG
tool follows these rules:
• The system clock input must be in the same column as the memory interface. The
system clock input is recommended to be in the address/control bank, when possible.
RECOMMENDED:
(SLRs), it is not recommended due to the additional clock jitter in this topology.
• CK must be connected to a p-n pair in one of the control byte groups. Any p-n pair in
the group is acceptable, including SRCC, MRCC, and DQS pins.
• If multiple CK outputs are used, such as for dual rank, all CK outputs must come from
the same byte lane.
• DQS signals for a byte group must be connected to a designated DQS pair in the bank
due to the dedicated strobe connections for DDR2 and DDR3 SDRAM. For more
information, see 7 Series FPGAs Clocking Resources User Guide (UG472)
• DQ and DM (if used) signals must be connected to the byte group pins associated with
the corresponding DQS.
• VRN and VRP are used for the digitally controlled impedance (DCI) reference for banks
that support DCI.
• The non-byte groups pins (that is, VRN/VRP pins in HP banks and top/bottom most
pins in HR banks) can be used for an address/control pin, if the following conditions are
met:
For HP banks, DCI cascade is used or the bank does not need the VRN/VRP pins, as
°
in the case of only outputs.
The adjacent byte group (T0/T3) is used as an address/control byte group.
°
Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
UG586 November 30, 2016
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Although the MIG allows system clock selection to be in different super logic regions
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[Ref 10].
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