Xilinx 7 Series User Manual
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Xilinx 7 Series User Manual

Fpgas clocking resources
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7 Series FPGAs
Clocking Resources
User Guide
UG472 (v1.5) July 13, 2012
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  • Page 1 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012 www.BDTIC.com/XILINX...
  • Page 2 Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Revision History

    VHDL and Verilog Templates and the Clocking Wizard. Added Appendix A, Multi-Region Clocking. 05/31/11 Added section on 7 Series FPGAs Clocking Differences from Previous FPGA Generations. Updated Figure 2-2. Clarified discussion in Clock-Capable Inputs section including removing Table 1-1: Migration of devices in the same package with different top/bottom alignments.
  • Page 4 In introductory paragraph of High-Performance Clocks, removed description of HPCs (Cont’d) connecting to OSERDES and buffers. Replaced cross reference to UG429, 7 Series FPGAs Migration Methodology Guide, with UG872, Large FPGA Methodology Guide. Updated Stacked Silicon Interconnect Clocking. Replaced SRL with SLR in Figure 2-28.

  • Page 5: Table Of Contents

    Clocking Differences in 7 Series FPGAs ........
  • Page 6 ..............101 www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 7 BUFR Alignment ............106 Appendix B: Clocking Resources and Connectivity Variations per Clock Region www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 8 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 9: Preface: About This Guide

    FPGAs optimized for the best price-performance. This guide serves as a technical reference describing the 7 series FPGAs clocking resources. This 7 series FPGAs clocking resources user guide, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/7.
  • Page 10 Preface: About This Guide www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 11: Chapter 1: Clocking Overview

    Chapter 1 Clocking Overview This chapter provides an overview of the 7 series FPGAs clocking, a comparison between 7 series FPGAs clocking and previous FPGA generations, and a summary of clocking connectivity within the 7 series FPGAs. For detailed information on usage of 7 series...
  • Page 12 CMTs within the same clock region and, with limitations, vertically adjacent clock regions Each 7 series device has 32 global clock lines that can clock and provide control signals to all sequential resources in the whole device. Global clock buffers (BUFGCTRL, simplified as BUFG throughout this user guide) drive the global clock lines and must be used to access global clock lines.

  • Page 13: Cmt Overview

    Clocking Architecture Overview CMT Overview Each 7 series FPGA has up to 24 CMTs, each consisting of one MMCM and one PLL. The MMCMs and PLLs serve as frequency synthesizers for a wide range of frequencies, serve as a jitter filters for either external or internal clocks, and deskew clocks. The PLL contains a subset of the MMCM functions.
  • Page 14 GT Column UG472_c1_30_020712 Figure 1-1: 7 Series FPGA High-Level Clock Architecture View A clock region always contains 50 CLBs per column, ten 36K block RAMs per column (unless five 36K blocks are replaced by a PCI block), 20 DSP slices per column, and 12 BUFHs.
  • Page 15 Figure 1-2: Basic View of Clock Region Figure 1-3 shows a more detailed view of clocking in a single clock region on the right edge of the device. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 16 BUFG and regional BUFH/ CMT/CC pin connectivity as well as the number of resources available in a region (a right side region is shown here). www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 17 Figure 1-5 shows a more detailed diagram of the I/O clocking resources and connectivity. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 18 FPGA has a minimum of one complete I/O column on the left edge of the device. A GT can be any one of the serial transceivers supported by the 7 series FPGAs (GTP, GTX, or GTH). Devices with GTs either have a mixed column of GTs and I/Os to the right edge of the...

  • Page 19: Series Fpgas Clocking Differences From Previous Fpga Generations

    7 Series FPGAs Clocking Differences from Previous FPGA Generations The 7 series FPGAs clocking has a similar structure to Virtex-6 FPGAs and supports many of the same features. However, there are some architectural differences and modifications to the various clocking elements and their functionality. When compared with Spartan-6 FPGAs, there are some significant changes in both architecture and functionality.

  • Page 20: Key Differences From Spartan-6 Fpgas

    ILOGIC and OLOGIC. • The Spartan-6 FPGA BUFIO2 dedicated input routing from GCLKs to the CMT and global clock buffers are no longer supported. To migrate to the 7 series FPGAs, use the dedicated input routing from the CCIO pins. •...

  • Page 21: Summary Of Clock Connectivity

    DCM_CLKGEN are no longer available and their functionality is now supported in the MMCMs and PLLs. • Global clock (GCLK) inputs are no longer supported in the 7 series FPGAs. Four clock-capable input pins are now available in every bank that support much of the Spartan-6 FPGA GCLK pin capabilities.
  • Page 22 • MMCM.CLKOUT0– • OLOGIC.clk BUFIO MMCM.CLKOUT3 • OLOGIC.clkb • CLKFBOUT • OLOGIC.oclk • BUFMRs in the same clock region • OLOGIC.oclkb and clock regions below and above www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 23 Clocks:) • Interconnect (not recommended) GT Transceiver Clocks: • Any BUFG RXUSRCLK Within the same clock region, GTs are driven by: RXUSRCLK2 • BUFH TXUSRCLK TXUSRCLK2 www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 24 • MMCM/PLL.CLKOUT0-3 • MRCC/SRCC IDELAYCNTRL.CLK • BUFG • BUFH CCLK pin Configuration logic Configuration logic EMCCLK pin Configuration logic TCK pin JTAG configuration logic and Boundary Scan www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 25: Clocking Differences In 7 Series Fpgas

    For a comprehensive graphical representation of the GT, CMT, and I/O locations and alignments, see the Die Level Bank Numbering Overview section in UG475, 7 Series FPGA Packaging and Pinout Specification. Table 1-2: Clocking Connectivity Differences by 7 Series FPGAs...
  • Page 26 Chapter 1: Clocking Overview www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 27: Chapter 2: Clock Routing Resources

    High-Performance Clocks Clock Buffer Selection Considerations 7 series FPGAs have a rich set of clocking resources. The various buffer types, clock input pins, and clocking connectivity satisfy many different application requirements. Selecting the proper clocking resources can improve routeability, performance, and general FPGA resource utilization.
  • Page 28 In this case, particular attention must be paid to the timing and skew because this is not the primary purpose of the BUFR. For more information on clocking SelectIO resources, consult UG471, 7 Series FPGAs SelectIO Resources User Guide. The horizontal clock buffer BUFH (BUFHCE) is strictly a regional resource and cannot span clock regions above or below.

  • Page 29: Clock-Capable Inputs

    CMTs in the same clock region and adjacent clock regions. • Global clocks lines (BUFG) in the same top/bottom half of the device. Refer to 7 Series FPGA Packaging and Pinout Specification for BUFG and I/O bank alignments. MRCCs can access multiple clock regions and the global clock tree. MRCCs function the same as SRCCs and can additionally drive multi-clock region buffers (BUFMR) to access up to three clock regions.

  • Page 30: Clock-Capable Input Pin Placement Rules

    There are limited dedicated resources to drive CMTs in the adjacent clock regions. Some Xilinx IP uses these resources, thus making them unavailable for additional design uses and resulting in unroutable designs. If the dedicated routes to the adjacent clock regions are not available, setting CLOCK_DEDICATED_ROUTE to FALSE allows the local interconnect logic to be used, although it results in longer, uncompensated delays.
  • Page 31 • A specific clock-capable pin pair connects to a specific BUFR and BUFIO. Therefore it is not recommended to manually LOC the BUFR/BUFIO. • There are four clock-capable inputs and four BUFIOs per clock region. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 32 25, for details on devices that have exceptions to these placement rules and UG475, 7 Series FPGA Packaging and Pinout Specification, for CMT, BUFG, and I/O bank alignments. 2. Ensure that the clock-capable input pinout does not require more resources than available, i.e., more than the 16 BUFGs per “half”...

  • Page 33: Global Clocking Resources

    There can also be situations when migrating to a smaller device in the same package where all BUFGs in the larger device’s south side are already utilized and no more BUFGs are available. See UG475: 7 Series FPGAs Packaging and Pinout Specification for BUFG and I/O bank alignments.

  • Page 34: Clock Regions

    32 global clock buffers. The dimensions of a clock region are fixed to 50 CLBs tall (50 IOBs) and spanning the left or right side of the die. In 7 series devices, the clock backbone splits the device into a left or right side. The backbone is not located in the center of the die.

  • Page 35: Global Clock Buffer Primitives

    Global Clocking Resources All global clock buffers can drive all clock regions in 7 series devices. However, only 12 different clocks can be driven in a single clock region. A clock region (50 CLBs) is a branch of the clock tree consisting of 25 CLB rows up and 25 CLB rows down. A clock region spans halfway across the device.
  • Page 36 I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 37 Virtex architectures. The timing diagram in Figure 2-4 illustrates various clock switching conditions using the BUFGCTRL primitives. Exact timing numbers are best found using the speed specification. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 38 Chapter 2: Clock Routing Resources X-Ref Target - Figure 2-4 BCCCK_CE IGNORE0 IGNORE1 BCCKO_O BCCKO_O BCCKO_O Begin I0 Begin I1 at I0 UG472_c1_04_033030 Figure 2-4: BUFGCTRL Timing Diagram www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 39 Figure 2-5 illustrates the relationship of BUFG and BUFGCTRL. The LOC constraint is available for manually placing the BUFG location. See the Constraints Guide for more information. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 40 BUFGCE and BUFGCE_1 locations. See the Constraints Guide for more information. X-Ref Target - Figure 2-7 BUFGCE as BUFGCTRL IGNORE1 BUFGCE IGNORE0 UG472_c1_07_061310 Figure 2-7: BUFGCE as BUFGCTRL www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 41 BUFGMUX and BUFGCTRL. The LOC constraint is available for manually placing the BUFGMUX and BUFGCTRL locations. See the Constraints Guide for more information. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 42 BUFGMUX_1. The LOC constraint is available for manually placing the BUFGMUX and BUFGMUX_1 locations. See the Constraints Guide for more information. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 43 This primitive is based on BUFGCTRL with some pins connected to logic High or Low. Figure 2-13 illustrates the relationship of BUFGMUX_CTRL and BUFGCTRL. X-Ref Target - Figure 2-13 IGNORE1 BUFGMUX_CTRL IGNORE0 ug472_c1_13_061310 Figure 2-13: BUFGMUX_CTRL as BUFGCTRL www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 44: Additional Use Models

    BUFGCTRL never detected a clock edge. This case uses the asynchronous MUX. Figure 2-15 illustrates an asynchronous MUX with BUFGCTRL design example. Figure 2-16 shows the asynchronous MUX timing diagram. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 45 The current clock is from I0. • S is activated High. • The Clock output immediately switches to I1. • When Ignore signals are asserted High, glitch protection is disabled. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 46 , before time event 3, CE is asserted Low. To avoid any output clock BCCCK_CE glitches, the clock output is switched Low and kept at Low until after a High to Low transition of I1 is completed. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 47: Regional Clocking Resources

    BUFIO or BUFMR. I/O Clock Buffer—BUFIO The I/O clock buffer (BUFIO) is a clock buffer available in 7 series devices. The BUFIO drives a dedicated clock net within the I/O bank, independent of the global clocking resources.

  • Page 48: Bufio Primitive

    2-20, a BUFIO is used to drive the I/O logic using the clock-capable I/O. This implementation is ideal in source-synchronous applications where a forwarded clock is used to capture incoming data. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 49 X-Ref Target - Figure 2-20 BUFIO BUFR Not all available BUFIOs and To FPGA BUFR BUFRs are shown. Logic BUFIO ug472_c1_20_030311 Figure 2-20: BUFIO Driving I/O Logic www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 50: Regional Clock Buffer-Bufr

    Chapter 2: Clock Routing Resources Regional Clock Buffer—BUFR The regional clock buffer (BUFR) is another clock buffer available in 7 series devices. BUFRs drive clock signals to a dedicated clock net within a clock region, independent from the global clock tree. Each BUFR can drive the four regional clock nets in the region it is located.

  • Page 51: Bufr Attributes And Modes

    • At time event 2, CLR is asserted. After T from time event 2, O stops BRDO_CLRO toggling. • At time event 3, CLR is deasserted. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 52: Bufr Use Models

    Figure 2-23: BUFR Driving Various Logic Resources Regional Clock Nets In addition to global clock trees and nets, 7 series devices contain regional clock trees and nets. The regional clock trees are also designed for low-skew and low-power operation. Unused branches are disconnected. The regional clock trees also manage the load/fanout when all the logic resources are used.

  • Page 53: Multi-Region Clock Buffer-Bufmr/Bufmrce

    Table 2-9: BUFMR and BUFMRCE Port List and Definitions Port Type Width Definition Output Clock output port Input Output clock enable port Input Clock input port www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 54 BUFMRCE is to provide a synchronous, phase-aligned clock to the BUFMR and BUFIO. For more details on the use of BUFMR in driving BUFRs and BUFIOs, see Appendix A, Multi-Region Clocking. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 55: Horizontal Clock Buffer-Bufh, Bufhce

    CE_TYPE Set to SYNC for CE to be synchronous from input to SYNC (default), output O, or set to ASYNC for asynchronous input to ASYNC output. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 56: High-Performance Clocks

    The Xilinx Power Estimator (XPE) or the Xilinx Power Analyzer (XPower) tools are used to estimate power savings. The difference is calculated by setting the frequency on the corresponding clock net to 0 MHz or providing the appropriate stimulus data to the tool.

  • Page 57: Stacked Silicon Interconnect Clocking

    SLR. Attention must be paid to minimize skew when placing clocking networks by placing related BUFG clocking structures into the same SLR, which might require duplication of external clocks. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 58 16 BUFGs HROW SLR Clock Backbone 12 BUFHCEs Bidirectional 3-Stateable Super Logic Region Interposer Connection Interposer UG472_c1_28_020712 Figure 2-28: SSI Technology Example for Virtex-7 XT Devices www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 59: Placement Of Clocking Structures

    Although each SLR has 32 BUFGs available in an SSI device, there are only 32 total global clock buffers available to the user. A single global clock buffer can drive any clocking point www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 60 Interposer Clock Backbone tracks BUFG31 (X0Y31) SLR Clock Backbone BUFG2 (X0Y2) SLR0 BUFG1 (X0Y1) BUFG0 (X0Y0) Interposer UG472_c2_18_011712 Figure 2-30: BUFG Connectivity across Interposer Clock Backbone www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 61: Chapter 3: Clock Management Tile

    (MMCM) and a phase-locked loop (PLL). The PLL contains a subset of the MMCM functions. At the core of the 7 series FPGAs CMT is the architecture similar to the Virtex-5 and Virtex-6 FPGAs with enhanced functions and capabilities. The CMT backbone can be used to chain CMT clocking functions;...

  • Page 62: Mmcms And Plls

    The PLL in the 7 series FPGAs, a subset of the MMCM functionality, is based on the MMCM and not necessarily based on previous PLL designs. The additional features supported by the MMCM are: •...
  • Page 63 CLKOUT0 CLKIN2 Fractional Divide CLKOUT0B CLKOUT1 CLKFB CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3 CLKOUT3B CLKOUT4 CLKOUT5 CLKOUT6 CLKFBOUT (Fractional Divide) CLKFBOUTB ug472_c2_02_020712 Figure 3-2: Detailed MMCM Block Diagram www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 64 General Switch Lock Routing Lock Monitor Circuit 8-phase taps CLKIN1 CLKIN2 CLKOUT0 CLKFB CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT ug472_c2_03_030211 Figure 3-3: Detailed PLL Block Diagram www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 65: General Usage Description

    General Usage Description General Usage Description MMCM and PLL Primitives The two 7 series FPGAs MMCM primitives, MMCME2_BASE and MMCME2_ADV, are shown in Figure 3-4. X-Ref Target - Figure 3-4 CLKIN1 CLKOUT0 CLKIN1 CLKOUT0 CLKOUT0B CLKIN2 CLKOUT0B CLKFBIN CLKOUT1 CLKFBIN...

  • Page 66: Mmcme2_Base And Plle2_Base Primitives

    Chapter 3: Clock Management Tile The two 7 series FPGAs PLL primitives, PLLE2_BASE and PLLE2_ADV, are shown in Figure 3-5. X-Ref Target - Figure 3-5 CLKIN1 CLKOUT0 CLKIN1 CLKOUT0 CLKOUT1 CLKIN2 CLKOUT1 CLKOUT2 CLKFBIN CLKFBIN CLKOUT2 CLKOUT3 CLKOUT3 CLKOUT4 CLKOUT4...

  • Page 67: Mmcme2_Adv And Plle2_Adv Primitive

    Control and Data Input RST, CLKINSEL, DWE, DEN, DADDR, DI Clock Output CLKOUT0 to CLKOUT5, and CLKFBOUT Status and Data Output LOCKED, DO, DRDY Power Control PWRDWN www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 68: Clock Network Deskew

    Chapter 3: Clock Management Tile The 7 series FPGAs MMCM and PLL are mixed-signal blocks designed to support clock network deskew, frequency synthesis, and jitter reduction. These three modes of operation are discussed in more detail within this section. The Voltage Controlled Oscillator (VCO) operating frequency can be determined by using the following relationship: ×...

  • Page 69: Frequency Synthesis Using Fractional Divide In The Mmcm

    Limitations The MMCM and the PLL have some restrictions that must be adhered to. These are summarized in the MMCM and the PLL electrical specifications in the 7 Series FPGA Data Sheets (http://www.xilinx.com/support/documentation/7_series.htm#156339). In general, the major limitations are VCO operation range, input frequency, duty cycle programmability, and phase shift.

  • Page 70: Minimum And Maximum Input Frequency

    CLKOUT output counters depending on the CLKOUT divide value. In 7 series FPGAs there is also an interpolated phase shifting capability in either fixed or dynamic mode. The MMCM phase shifting capabilities are very powerful which can lead to complex scenarios.

  • Page 71: Dynamic Phase Shift Interface In The Mmcm

    PSDONE asserts High. After PSDONE has pulsed High, another increment/decrement can be initiated. There is no maximum phase shift or phase-shift overflow. An entire clock period (360 degrees) can www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 72: Mmcm Counter Cascading

    There can be a very large number of frequencies. When using integer divides, in the worst case, there will be 106 x 64 x 136 = 868,363 possible www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 73: Determine The M And D Values

    D value is used to start the process. The goal is to make D and M values as small as possible while keeping ƒ as high as possible. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 74: Mmcm Ports

    Direct HPC connections to BUFR/BUFIO are only supported on CLKOUT[0:3]. See CLKOUT[0:6] – Output Clocks. CLKOUT[0:3]B Output Inverted CLKOUT[0:3]. See CLKOUT[0:3]B – Inverted Output Clocks. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 75: Pll Ports

    The dynamic reconfiguration address (DADDR) input bus provides a DADDR[6:0] Input reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 76: Mmcm And Pll Port Descriptions

    Must be connected either directly to the CLKFBOUT for internal feedback or IBUFG (through a clock-capable pin for external deskew), BUFG, BUFH, or interconnect (not recommended). For external clock alignment, the feedback path clock buffer type should www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 77 The dynamic reconfiguration enable strobe (DEN) provides the enable control signal to access the dynamic reconfiguration feature and enables all DRP port operations. When the dynamic reconfiguration feature is not used, DEN must be tied Low. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 78 See Static Phase Shift Mode for more information. CLKOUT[0:3]B – Inverted Output Clocks Inverted (180° phase shift) of CLKOUT[0:3]. Not available in the PLL. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 79: Mmcm Attributes

    Type Allowed Values Default Description BANDWIDTH String HIGH OPTIMIZED Specifies the MMCM programming algorithm affecting OPTIMIZED the jitter, phase margin and other characteristics of the MMCM. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 80 If known, then the value provided should be specified in terms of the unit interval (UI) (the maximum peak to peak value) of the expected jitter on the input clock. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 81 (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 82 1. The COMPENSATION attribute values are documented for informational purpose only. The ISE® software tools automatically select the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at the default value. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 83: Pll Attributes

    Real 0.01 to 0.99 0.50 Specifies the Duty Cycle of the DUTY_CYCLE associated CLKOUT clock output in percentage (i.e., 0.50 will generate a 50% duty cycle). www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 84 1. The COMPENSATION attribute values are documented for informational purpose only. The ISE software tools automatically select the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at the default value. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 85: Mmcm Clock Input Signals

    DIVIDE = 3 DUTY_CYCLE = 0.33 PHASE = 0 DIVIDE = 3 DUTY_CYCLE = 0.5 PHASE = 0 UG472_c2_08_061710 Figure 3-8: Output Counter Clock Synthesis Examples www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 86: Detailed Vco And Output Counter Waveforms

    Figure 3-9: Selecting VCO Phases All “O” counters can be equivalent, anything O0 can do, O1 can do. In 7 series devices, the O0 counter has the additional capability to be used in fractional divide mode. The MMCM/PLL outputs are flexible when connecting to the global clock network since they are identical.

  • Page 87: Reference Clock Switching

    The configuration in Figure 3-11 is the most flexible, but it does require two global clock networks. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 88 CLKIN1 CLKFBIN CLKOUT0B CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3B CLKOUT4 CLKOUT5 BUFH CLKOUT6 CLKFBOUT CLKFBOUTB LOCKED MMCM UG472_c2_17_011712 Figure 3-12: Horizontal Clock Network Deskew Using Two BUFHs www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 89: Mmcm With Internal Feedback

    IBUFG To Logic CLKOUT0 CLKIN1 CLKFBIN CLKOUT0B CLKOUT1 CLKOUT1B CLKOUT2 CLKOUT2B CLKOUT3B CLKOUT4 CLKOUT5 CLKOUT6 CLKFBOUT CLKFBOUTB LOCKED MMCM UG472_c2_12_061710 Figure 3-13: MMCM with Internal Feedback www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 90: Zero Delay Buffer

    MMCMs because the backbone connection is not compensated. To cascade MMCMs, route the output of the first MMCM to the CLKIN pin of the second www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 91 CLKOUT5 BUFG CLKOUT6 CLKOUT6 To Logic CLKFBOUT CLKFBOUT CLKFBOUTB CLKFBOUTB MMCM MMCM LOCKED LOCKED ug472_c2_15_042611 Figure 3-16: Cascading Two MMCMs With the Closest Possible Clock Alignment www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 92: Spread-Spectrum Clock Generation

    FIFO to ensure that data is not lost. Increasing the frequency deviation will require a larger FIFO. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 93 Because the average output frequency when using down spread is lower than the input frequency, an asynchronous FIFO must be used for transferring data between the input and output clock domains. Logic within the MMCME2 controls the spread-spectrum www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 94 M = 21, 22 75 MHz < F < 100 MHz D = 2 M = 21, 22 100 MHz < F < 150 MHz D = 3 www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 95 10% of SS_MOD_PERIOD. Because the modulation frequency is a fraction of the VCO frequency, the modulation frequency will scale as the input frequency changes for a given compilation. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 96: Mmcm Application Example

    CLKOUT3 CLKOUT4 CLKOUT5 UG472_c2_16_061710 Figure 3-20: Example Waveform Dynamic Reconfiguration Port For DRP usage, see XAPP888, MMCM and PLL Dynamic Reconfiguration and the associated reference design. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 97: Vhdl And Verilog Templates And The Clocking Wizard

    The VHDL and Verilog code for all clocking resource primitives and ISE language templates are available in the Libraries Guide. The Clocking Wizard helps to correctly set up the 7 series MMCM and PLL resources. Additionally, the Clocking Wizard reports the jitter and supports phase and frequency synthesis.
  • Page 98 Chapter 3: Clock Management Tile www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 99: Appendix A: Multi-Region Clocking

    This appendix details using the BUFIO and BUFR clock buffers to drive clock signals across multiple clock regions. All 7 series FPGAs are divided into areas known as clock regions. A clock region spans from the global clocking column in the center of the device to either the left or right edge of...

  • Page 100: Clocking Across Multiple Regions

    BUFMRs located in each clock region. The BUFMRs drive the dedicated low-skew clocking resources residing within the CMT column, ensuring that the least possible skew is inserted when driving clock signals into multiple regions. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 101: Use Cases

    P-side, look for a P in the pin name (for example: IO_LxxP_Tx_MRCC_xx). The GT inputs to the Virtex®-6 FPGA BUFRs are not available in the 7 series FPGAs architecture. The BUFMR, however, can get its inputs from any one of the GT clocks within the clock region.

  • Page 102: Clock Alignment Across Clock Regions

    X-Ref Target - Figure A-4 I/O Logic BUFIO Clock Region Boundary I/O Logic MRCC BUFMR BUFIO Clock Region Boundary I/O Logic BUFIO ug472_aA_04_030111 Figure A-4: Driving Multiple BUFIOs www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 103: Driving Multiple Bufrs

    When driving multiple buffers in this manner, manually place the buffers with a LOC constraint. The logic driven by the buffers is automatically placed in the appropriate location. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 104 CLKDIV BUFR MRCC BUFMRCE BUFIO BUFR Alignment Circuit Clock Region Boundary ISERDES/OSERDES ÷ CLKDIV BUFR BUFIO ug472_aA_06_051311 Figure A-6: Driving Multiple BUFRs (With Divide) and BUFIO www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

  • Page 105: Driving Multiple Bufrs (With And Without Divide)

    CLKDIV BUFR MRCC BUFMRCE BUFR BUFR Alignment Circuit Clock Region Boundary ISERDES/OSERDES ÷ CLKDIV BUFR BUFR ug472_aA_07_051311 Figure A-7: Driving Multiple BUFRs (With and Without Divide) www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...

  • Page 106: Bufr Alignment

    To turn off clocks during circuit operations, that is after the reset/CLR signal to the BUFRs is deasserted, disable the BUFMRCE using its CE pin. This ensures that the BUFRs continue to be aligned when the clock signal is reinstated. www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 107 Appendix B Clocking Resources and Connectivity Variations per Clock Region The figures in this appendix show the clocking resources and connectivity for the clock region variations. www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 108 SelectIO Logic SelectIO Logic 5x36K MMCM 5x36K DSP48 DSP48 Block RAMs/ Block RAMs/ Slices Slices FIFOs FIFOs UG472_aB_01_020812 Figure B-1: Clock Region in Virtex-7 FPGAs (Right Side) www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 109 Logic Resources 25 CLBs SelectIO Logic SelectIO Logic SelectIO Logic UG472_aB_02_020812 Figure B-2: Clock Region in Kintex-7 FPGAs with I/O Banks and no GT Transceivers (Right Side) www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 110 RX/TXUSRCLKs RX/TXOUTCLKs 25 CLBs IBUFDS O/ODIV2 UG472_aB_03_020812 Figure B-3: Clock Region in Kintex-7 and Artix-7 XC7A100T FPGAs with GT Transceivers and no I/O Banks (Right Side) www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...
  • Page 111 SelectIO Logic IBUFDS O/ODIV2 SelectIO Logic SelectIO Logic UG472_aB_04_020812 Figure B-4: Clock Region in Artix-7 XC7A200T and XC7A350T Devices with GTP Transceivers and I/O Banks (Right Side) www.BDTIC.com/XILINX 7 Series FPGAs Clocking Resources User Guide www.xilinx.com UG472 (v1.5) July 13, 2012...
  • Page 112 Appendix B: Clocking Resources and Connectivity Variations per Clock Region www.BDTIC.com/XILINX www.xilinx.com 7 Series FPGAs Clocking Resources User Guide UG472 (v1.5) July 13, 2012...

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