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» Pin Function
Pin No.
Pin Name
31, 32, 33, 34, 35,
P3.0-P3.7
36, 37, 38
48, 49
P4.2-P4.3(P4.7)
5
XROM
17
ENE
18
STOP
19
OCF
20
EXTIF
21
CVBS
29
HS/SC
30
VS/P4.7
50
RST
52
XTAL2
53
XTAL1
57
R
58
G
59
B
60
BLANK/COR
64
WR
65
RD
72
FL_PGM
80
FL_RST
87
ALE
88
PSEN
95
FL_CE
6, 73
VDD2.5
22, 56
VDDA2.5
8, 40, 75, 92
VDD3.3
7, 39, 74, 91,
VSS
23, 55
VSSA
28, 51, 54, 61, 63,
—
66
I/O
I/O
Port 3 is an 8-bit bi-directional I/O port with internal pull-up resistors, Port 3 pins that
have 1 written to them are pulled high by the internal pull-up resistors and in that state
can be used as inputs,
To use the secondary functions of Port 3, the corresponding output latch must be
programmed to a one (1) for that function to operate. The secondary functions are as
follows:
» Alternate function
P3.0 : ODD/EVEN indicate output
P3.1 : external extra interrupt 0 (INTX0)/UART(TXD)
P3.2 : interrupt 0 input/timer 0 gate control input)INT0)
P3.3 : interrupt 1 input/timer 1 gate control input)INT1)
P3.4 : counter 0 input (T0)
P3.5 : counter 1 input (T1) or In master mode HS or VCS output.
P3.7 : external extra interrupt 0 (INTX1)/UART (RXD)
I/O
Port 4 is a bi-directional I/O port with internal pull-up resistors.
Port 4 pins that have 1 written to them are pulled high by the internal pull-up resistors
and in that state can be used as inputs.
Secondary functions
P4.2: RD, Read line. This signal is same as the to output of the pin RD available in
some packages.
P4.3: WR write line. This signal is same as the output of the pin WE, which is only
available in some package.
I
This pin must be pulled low to access external ROM.
I
Enable Emulation
Only if this pin set to zero externally, STOP and OCF are operational. ENE has an
internal pull-up resistor which switches automatically to non-emulation mode if ENE is
not connected.
I
STOP
Emulation control line; Driving a low level during the input phase freezes the real time
relevant internal peripherals such as timers and interrupt controller.
O
Opcode Fetch
Emulation control line; A high level driven by the controller during output phase
indicates the beginning of a new instruction.
I
I
CVBS input for the acquisition circuit.
I/O
In slave mode Horizontal sync input or sandcastle input for display synchronization .In
master mode HS or VCS output.
I
Vertical sync input/output for display synchronization.
Can also be used as digital input P4.7.
Furthermore this pin can be selected as an ODD/EVEN indicator alternatively to P3.0.
O
A low level on this pin resets the device. An internal pull-up resistor permits power-on
reset using only one external capacitor connected to Vss.
I
Output of the inverting oscillator amplifier.
O
Input of the inverting oscillator amplifier.
O
Red
O
Green
O
Blue
O
Contrast reduction and blanking.
O
Control output; indicates a write access to the internal XRAM; can be used as a write
strobe for writing data into an external data RAM by a MOVX instruction.
This signal is also available as P4.3.
I
Control output; indicates a read access to the internal XRAM; can be used for latching
data from the data bus into an external data RAM by a MOVX instruction.
This signal is also available as P4.2.
I
All the pins prefix by Flax are test pins which must be left open.
O
All the pins prefix by Flax are test pins which must be left open.
O
Address Latch Enable.
I
Program Store Enable
is a control output signal which is usually connected to OE input line of the external
program memory to enable the data output.
—
All the pins prefix by Flax are test pins which must be left open.
—
Supply voltage (2.5V).
—
Supply voltage for analog components (2.5V).
—
Input/output (3.3V).
—
Ground (0V).
—
Ground for analog components.
—
27
Pin Function
PZ-43MR2E
PZ-50MR2E
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