Page 1 USER'S MANUAL ERRATA This document contains the corrections of errors, typos and omissions in the following document. Samsung 8-bit CMOS S3C80A5B Microprocessor User's Manual Document Number: 21.1-S3-C80A5B-082005 Publication: August 2005...
Page 2 S3C80A5B USER’S MANUAL ERRATA ERRATA ( VER 1.1) Samsung 8-bit CMOS S3C80A5B Microprocessor User’s Manual Document Number: 21.1-S3-C80A5B-082005 Publication: August 2005 1. Features (PAGE 1-2) Operating Voltage Range — 2.0 V to 5.5 V at 8 MHz f 2. Table 13-2. D.C. Electrical Characteristics (PAGE13-2) °...
Page 3 USER’S MANUAL ERRATA S3C80A5B 4. Table 13-2. D.C. Electrical Characteristics (PAGE13-3) ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Output low = 2.4 V, I = 12 mA, port –...
Page 4 8 MHz 1.00 MHz 6 MHz 670 kHz 4 MHz 500 kHz 250 kHz 8.32 kHz 400 kHz Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 13-2. Operating Voltage Range of S3C80A5B...
Page 5 S3C80A5B 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.1...
Page 6: Important Notice
Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
Page 7 Chapter 14 Mechanical Data Two order forms are included at the back of this manual to facilitate customer order for S3C80A5B microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
Page 8: Table Of Contents
Table of Contents Part I — Programming Model Chapter 1 Product Overview Overview......................................1-1 S3C80A5B Microcontroller................................1-1 Features......................................1-2 Block Diagram ....................................1-3 Pin Assignments....................................1-4 Pin Descriptions .....................................1-5 Pin Circuits ......................................1-6 Chapter 2 Address Spaces Overview......................................2-1 Program memory (ROM) ................................2-2 Register Architecture..................................2-3 Register Page Pointer (PP)..............................2-5 Register Set 1..................................2-6...
Page 9 Control Registers Overview .............................4-1 Chapter 5 Interrupt Structure Overview ......................................5-1 Interrupt Types..................................5-2 S3C80A5B Interrupt Structure............................5-3 Interrupt Vector Addresses...............................5-5 Enable/Disable Interrupt Instructions (EI, DI)......................5-7 System-Level Interrupt Control Registers........................5-7 Interrupt Processing Control Points..........................5-8 Peripheral Interrupt Control Registers ...........................5-9 System Mode Register (SYM) ............................5-10 Interrupt Mask Register (IMR)............................5-11...
Page 10 Port 0 Interrupt Pending Register (P0PND).........................9-4 Port 1......................................9-6 Port 2......................................9-8 Chapter 10 Basic Timer and Timer 0 Module Overview.....................................10-1 Basic Timer Control Register (BTCON)........................10-1 Basic Timer Function Description..........................10-3 Timer 0 Control Register (T0CON) ..........................10-3 Timer 0 Function Description............................10-5 S3C80A5B MICROCONTROLLER...
Page 11 Timer 1 Match Interrupt..............................11-2 Timer 1 Control Register (T1CON)..........................11-4 Chapter 12 Counter A Overview ......................................12-1 Counter A Control Register (CACON) ...........................12-3 Counter A Pulse Width Calculations ..........................12-4 Chapter 13 Electrical Data Overview .............................13-1 Chapter 14 Mechanical Data Overview .............................14-1 viii S3C80A5B MICROCONTROLLER...
Page 12 Indexed Addressing to Program or Data Memory with Short Offset........3-8 Indexed Addressing to Program or Data Memory ..............3-9 3-10 Direct Addressing for Load Instructions ..................3-10 3-11 Direct Addressing for Call and Jump Instructions ..............3-11 3-12 Indirect Addressing..........................3-12 3-13 Relative Addressing..........................3-13 3-14 Immediate Addressing........................3-14 Register Description Format ......................4-4 S3C80A5B MICROCONTROLLER...
Page 13 Reset Block Diagram .........................8-1 Power-on Reset Circuit........................8-2 Timing Diagram for Power-on Reset Circuit.................8-3 S3C80A5B I/O Port Data Register Format ..................9-2 Port 0 High-Byte Control Register (P0CONH) ................9-3 Port 0 Low-Byte Control Register (P0CONL)................9-4 Port 0 External Interrupt Control Register (P0INT) ..............9-5 Port 0 External Interrupt Pending Register (P0PND)..............9-5...
Page 14 Counter A Registers ...........................12-4 12-4 Counter A Output Flip-Flop Waveforms in Repeat Mode............12-5 13-1 Input Timing for External Interrupts (Port 0) ................13-5 13-2 Operating Voltage Range of S3C80A5B ..................13-6 14-1 24-Pin SOP Package Mechanical Data..................14-1 14-2 24-Pin SDIP Package Mechanical Data..................14-2 S3C80A5B MICROCONTROLLER...
Page 15 List of Tables Table Title Page Number Number Pin Descriptions ..........................1-5 S3C80A5B Register Type Summary.....................2-3 Mapped Registers (Set 1).........................4-2 S3C80A5B Interrupt Vectors ......................5-6 Interrupt Control Register Overview....................5-7 Interrupt Source Control and Data Registers ................5-9 Instruction Group Summary ......................6-2 Flag Notation Conventions........................6-8 Instruction Set Symbols........................6-8...
Page 16 To Divide STOP Mode Releasing and POR...........................8-7 Chapter 10: Basic Timer and Timer 0 Configuring the Basic Timer ..............................10-8 Programming Timer 0................................10-9 Chapter 12: Counter A To Generate 38 kHz, 1/3duty Signal Through P2.1.......................12-6 To Generate a One Pulse Signal Through P2.1......................12-7 S3C80A5B MICROCONTROLLER...
Page 17 P2CON Port 2 Control Register..................4-22 Register Page Pointer..................4-23 Register Pointer 0....................4-24 Register Pointer 1....................4-24 Stack Pointer (Low Byte) ..................4-25 STOPCON Stop Control Register...................4-25 System Mode Register ..................4-26 T0CON Timer 0 Control Register..................4-27 T1CON Timer 1 Control Register..................4-28 S3C80A5B MICROCONTROLLER xvii...
Page 18 Disable Interrupts ....................6-37 Divide (Unsigned)....................6-38 DJNZ Decrement and Jump if Non-Zero ................6-39 Enable Interrupts ....................6-40 ENTER Enter........................6-41 EXIT Exit ........................6-42 IDLE Idle Operation......................6-43 Increment ......................6-44 INCW Increment Word....................6-45 IRET Interrupt Return ....................6-46 Jump........................6-47 Jump Relative......................6-48 Load........................6-49 Load Bit......................6-51 S3C80A5B MICROCONTROLLER...
Page 19 Subtract with Carry ....................6-77 Set Carry Flag.....................6-78 Shift Right Arithmetic...................6-79 SRP/SRP0/SRP1 Set Register Pointer ....................6-80 STOP Stop Operation....................6-81 Subtract ......................6-82 SWAP Swap Nibbles ......................6-83 Test Complement under Mask ................6-84 Test under Mask ....................6-85 Wait for Interrupt....................6-86 Logical Exclusive OR...................6-87 S3C80A5B MICROCONTROLLER...
Page 20: Chapter 1 Product Overview
PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources —...
Page 21: Features
• Program memory (ROM) • One 8-bit timer/counter (Timer 0) with two operating modes; Interval mode and PWM mode. – S3C80A5B: 15,872 byte (0000H–3E00H) • One 16-bit timer/counter with one operating modes; Interval mode • Data memory: 272-byte RAM...
Page 22: Block Diagram
S3C80A5B PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7/INT0-INT4 P1.0-P1.7 Port 0(INTR) Port 1 TEST Internal Bus Main P2.0/T0PWM Port I/O and Interrupt Port 2 P2.1/REM Control 8-bit P2.2 Basic Timer SAM87RI CPU 8-bit Timer/ Counter Carrier Generator (Counter A) 256-Byte 15-Kbyte ROM...
Page 23: Pin Assignments
PRODUCT OVERVIEW S3C80A5B PIN ASSIGNMENTS P2.2/SCLK P2.1/REM/SDAT P2.0/T0PWM/T0CK TEST S3C80A5B P1.7 P0.0/INT0/INTR P1.6 P0.1/INT1/INTR P1.5 nRESET/P0.2/INT2/INTR P1.4 P0.3/INT3/INTR 24-SOP/SDIP P1.3 P0.4/INT4/INTR (TOP VIEW) P1.2 P0.5/INT4/INTR P1.1 P0.6/INT4/INTR P1.0 P0.7/INT4/INTR Figure 1-2. Pin Assignment Diagram (24-Pin SOP/SDIP Package)
Page 24: Pin Descriptions
S3C80A5B PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. Pin Descriptions Circuit 24-Pin Shared Names Type Description Type Number Functions P0.0–P0.7 I/O port with bit-programmable pins. 5–12 INT0 – INT4/INTR Configurable to input or push-pull output mode. Pull-up resistors are assignable by software.
Page 25: Pin Circuits
Figure 1-3. Pin Circuit Type 1 (Port 0) NOTE Interrupt with reset (INTR) is assigned to port 0 of S3C80A5B. It is designed to release stop status with reset. When the falling/rising edge is detected at any pin of Port 0 during stop status, non vectored interrupt INTR signal occurs, after then system reset occurs automatically.
Page 26: Pin Circuit Type 2 (Port 1)
S3C80A5B PRODUCT OVERVIEW Pull-up Resistor Pull-up Enable Data Input/Output Open-drain Output Disable Noise Normal Input filter Figure 1-4. Pin Circuit Type 2 (Port 1) Pull-up Resistor (Typical 21KΩ) Pull-up Enable P2CON.0 Port 2.0 Data Data T0_PWN P2.0/T0PWN Open-drain Output Disable P2.0 Input...
Page 27: Pin Circuit Type 4 (P2.1)
PRODUCT OVERVIEW S3C80A5B Pull-up Resistor (Typical 21KΩ) Pull-up Enable P2CON.1 Port 2.1 Data Data CAOF(CACON.0) Carrier On/Off (P2.5) P2.1/REM/T0CK Open-Drain Output Disable P2.1 Input T0CK Noise filter Figure 1-6. Pin Circuit Type 4 (P2.1) Pull-up Resistor (Typical 21 kΩ) Pull-up...
Page 28: Chapter 2 Address Spaces
CPU and the register file. The S3C80A5B has an internal 15,872 byte programmable ROM. An external memory interface is not implemented. The 256-byte physical RAM space is expanded into an addressable area of 320 bytes by the use of addressing modes.
Page 29: Program Memory (Rom)
S3C80A5B PROGRAM MEMORY (ROM) Program memory stores program code or table data. The S3C80A5B has 15, 872 bytes of internal programmable program memory, and the program memory address range is therefore 0000H-3E00H of ROM . (see Figure 2-1). The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory.
Page 30: Register Architecture
ADDRESS SPACES REGISTER ARCHITECTURE The S3C80A5B register file has 312 registers. The upper 64 bytes register files are addressed as system control register and working register. The lower 192-byte area of the physical register file(00H–BFH) contains freely- addressable, general-purpose registers called prime registers. It can be also used for stack operation.
Page 31: Internal Register File Organization
ADDRESS SPACES S3C80A5B Set 1 Set 2 System and Peripheral Control Registers (Register Addressing General-Purpose Mode) Data Register (Indirect Register or 64-Bytes System Registers Indexed addressing (Register Addressing modes or Mode) stack operations) Working Registers (Working Register Addressing Mode) 256-Bytes...
Page 32: Register Page Pointer (Pp)
8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C80A5B microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to "page 0."...
Page 33: Register Set 1
32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3C80A5B microcontroller, bank 1 is not implemented. A hardware reset operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not necessary.
Page 34: Prime Register Space
S3C80A5B ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All registers...
Page 35: Working Registers
ADDRESS SPACES S3C80A5B WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices."...
Page 36: Using The Register Pointers
S3C80A5B ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
Page 37: Non-Contiguous 16-Byte Working Register Block
ADDRESS SPACES S3C80A5B F7H (R7) 8-Byte Slice F0H (R0) 16-Byte Register File Contiguous Contains 32 1 1 1 1 0 X X X working 8-Byte Slices Register block 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R0) Figure 2-7.
Page 38: Register Addressing
S3C80A5B ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2.
Page 39: Register File Addressing
ADDRESS SPACES S3C80A5B Special-Purpose Registers General-Purpose Register Set 1 Control Registers Set 2 System Registers Register Pointers Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file Prime (other than set 2). After a reset, RP0 points to...
Page 40: Common Working Register Area (C0H-Cfh)
S3C80A5B ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H– CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area.
Page 41: 4-Bit Working Register Addressing
ADDRESS SPACES S3C80A5B PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Example 1: 0C2H,40H ; Invalid addressing mode!
Page 42: Bit Working Register Addressing
S3C80A5B ADDRESS SPACES Selects RP0 or RP1 Address OPCODE 4-bit Address Register Pointer Provides Three Provides Five Low-order Bits High-order Bits Together They Create an 8-bit Register Address Figure 2-11. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0...
Page 43: 8-Bit Working Register Addressing
ADDRESS SPACES S3C80A5B 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B.
Page 44: Bit Working Register Addressing Example
S3C80A5B ADDRESS SPACES 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 8-bit Address Form Instruction 1 1 0 0 1 0 1 1 'LD R11, R2' Specifies Working Register Addressing...
Page 45: System And User Stacks
Register location D9H contain the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset, the SPL value is undetermined. Because only internal memory 256-byte is implemented in S3C80A5B, the SPL must be initialized to an 8-bit value in the range 00H–FFH.
Page 46: Standard Stack Operations Using Push And Pop
S3C80A5B ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SPL ← FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...
Page 47: Chapter 3 Addressing Modes
S3C80A5B ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
Page 48: Register Addressing Mode (R)
ADDRESSING MODES S3C80A5B REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing because it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Page 49: Indirect Register Addressing Mode (Ir)
S3C80A5B ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).
Page 50: Indirect Register Addressing To Program Memory
ADDRESSING MODES S3C80A5B INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Register Pair Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...
Page 51: Indirect Working Register Addressing To Register File
S3C80A5B ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP Points to Start of Program Memory Woking Register 4-bit Block 3 LSBs Working ADDRESS Register Point to the OPCODE...
Page 52: Indirect Working Register Addressing To Program Or Data Memory
R3,@RR14 ; External data memory access @RR4, R8 ; External data memory access NOTE: LDE command is not available, because an external interface is not implemented for the S3C80A5B Figure 3-6. Indirect Working Register Addressing to Program or Data Memory...
Page 53: Indexed Addressing Mode (X)
S3C80A5B ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented).
Page 54: Indexed Addressing To Program Or Data Memory With Short Offset
; Identical operation to LDC example, except that external program memory is accessed. NOTE: LDE command is not available, because an external interface is not implemented for the S3C80A5B. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset...
Page 55: Indexed Addressing To Program Or Data Memory
R4, #1000H[RR2] ; Identical operation to LDC example, except that external program memory is accessed. NOTE: LDE command is not available, because an external interface is not implemented for the S3C80A5B. Figure 3-9. Indexed Addressing to Program or Data Memory...
Page 56: Direct Address Mode (Da)
R5. R5,1234H Identical operation to LDC example, except that external program memory is accessed. NOTE: LDE command is not available, because an external interface is not implemented for the S3C80A5B. Figure 3-10. Direct Addressing for Load Instructions 3-10...
Page 57: Direct Addressing For Call And Jump Instructions
S3C80A5B ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: C,JOB1 ; Where JOB1 is a 16 bit immediate address CALL DISPLAY ; Where DISPLAY is a 16 bit immediate address Figure 3-11.
Page 58: Indirect Address Mode (Ia)
ADDRESSING MODES S3C80A5B INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Page 59: Relative Address Mode (Ra)
S3C80A5B ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.
Page 60: Immediate Mode (Im)
ADDRESSING MODES S3C80A5B IMMEDIATE MODE (IM) In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
Page 61: Overview
CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C80A5B control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.
Page 62: Mapped Registers (Set 1)
CONTROL REGISTERS S3C80A5B Table 4-1. Mapped Registers (Set 1) Register Name Mnemonic Decimal (note) Timer 0 counter T0CNT Timer 0 data register T0DATA Timer 0 control register T0CON Basic timer control register BTCON Clock control register CLKCON System flags register...
Page 63 S3C80A5B CONTROL REGISTERS Table 4-1. Mapped Registers (Continued) Register Name Mnemonic Decimal Timer 1 data register (low byte) T1DATAL Timer 1 control register T1CON STOP Control register STOPCON Locations FCH is not mapped. (note) Basic timer counter BTCNT External memory timing register...
Page 64: Register Description Format
CONTROL REGISTERS S3C80A5B Bit number(s) that is/are appended to Name of individual the register name for bit addressing bit or related bits Register location in the internal Register address Register ID Register name (hexadecimal) register file FLAGS - System Flags Register...
Page 65: Basic Timer Control Register
.3–.2 Basic Timer Input Clock Selection Bits /4096 /1024 /128 Invalid setting; not used for S3C80A5B Basic Timer Counter Clear Bit No effect Clear the basic timer counter value Clock Frequency Divider Clear Bit for Basic Timer and Timer 0...
Page 66: Counter A Control Register
Counter A Interrupt Timing Selection Bits Elapsed time for Low data value Elapsed time for High data value Elapsed time for combined Low and High data values Invalid setting; not used for S3C80A5B. Counter A Interrupt Enable Bit Disable interrupt Enable interrupt...
Page 67: System Clock Control Register
CLKCON.3 and CLKCON.4. These selection bits are required only for systems that have a main clock and a subsystem clock. The S3C80A5B uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
Page 68: External Memory Timing Register
Not used for S3C80A5B. NOTE: The EMT register is not used for S3C80A5B, because an external peripheral interface is not implemented in the S3C80A5B. The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT...
Page 69: System Flags Register
Fast Interrupt Status Flag (FIS) Interrupt return (IRET) in progress (when read) Fast interrupt service routine in progress (when read) Bank Address Selection Flag (BA) Bank 0 is selected (normal setting for S3C80A5B) Invalid selection (bank 1 is not implemented)
Page 70: Imr Interrupt Mask Register
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow Disable (mask) Enable (un-mask) NOTES: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU. Interrupt levels IRQ2, IRQ3 and IRQ5 are not used in the S3C80A5B interrupt structure. 4-10...
Page 71: Iph Instruction Pointer (High Byte)
S3C80A5B CONTROL REGISTERS — Instruction Pointer (High Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
Page 72: Ipr Interrupt Priority Register
IRQ0 > IRQ1 IRQ1 > IRQ0 NOTE: The S3C80A5B interrupt structure uses only five levels: IRQ0, IRQ1, IRQ4, IRQ6–IRQ7. Because IRQ2, IRQ3, IRQ5 are not recognized, the interrupt subgroup B and group C settings (IPR.2,.3 and IPR.5) are not evaluated.
Page 73: Irq Interrupt Request Register
Level 1 (IRQ1) Request Pending Bit; Timer 1 Match or Overflow Not pending Pending Level 0 (IRQ0) Request Pending Bit; Timer 0 Match or Overflow Not pending Pending NOTE: Interrupt level IRQ2, IRQ3 and IRQ5 is not used in the S3C80A5B interrupt structure. 4-13...
Page 74: Port 0 Control Register (High Byte)
CONTROL REGISTERS S3C80A5B P0CONH — Port 0 Control Register (High Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.7/INT4 Mode Selection Bits C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode;...
Page 75: Port 0 Control Register (Low Byte)
S3C80A5B CONTROL REGISTERS P0CONL — Port 0 Control Register (Low Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.3/INT3 Mode Selection Bits C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode;...
Page 76 CONTROL REGISTERS S3C80A5B P0INT — Port 0 External Interrupt Enable Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only P0.7 External Interrupt (INT4) Enable Bit Disable interrupt Enable interrupt P0.6 External Interrupt (INT4) Enable Bit...
Page 77 S3C80A5B CONTROL REGISTERS P0PND — Port 0 External Interrupt Pending Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only (note) P0.7 External Interrupt (INT4) Pending Flag No P0.7 external interrupt pending (when read) P0.7 external interrupt is pending (when read) P0.6 External Interrupt (INT4) Pending Flag...
Page 78: Port 0 Pull-Up Resistor Enable Register
CONTROL REGISTERS S3C80A5B P0PUR — Port 0 Pull-up Resistor Enable Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only P0.7 Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P0.6 Pull-up Resistor Enable Bit...
Page 79: Port 1 Control Register (High Byte)
S3C80A5B CONTROL REGISTERS P1CONH — Port 1 Control Register (High Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.7 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode Invalid setting .5–.4...
Page 80: Port 1 Control Register (Low Byte)
CONTROL REGISTERS S3C80A5B P1CONL — Port 1 Control Register (Low Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.3 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode Invalid setting .5–.4...
Page 81 S3C80A5B CONTROL REGISTERS P1PUR — Port 0 Pull-up Resistor Enable Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only P1.7 Pull-up Resistor Enable Bit Disable pull-up resistor Enable pull-up resistor P1.6 Pull-up Resistor Enable Bit...
Page 82: Port 2 Control Register
CONTROL REGISTERS S3C80A5B P2CON — Port 2 Control Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P2.2 Mode Selection Bits C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode .5–.4...
Page 83: Pp Register
Source: page 0 NOTE: In the S3C80A5B microcontroller, a paged expansion of the internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to '0000B' following a hardware reset. These values should not be changed during normal operation.
Page 84: Rp0 Register Pointer 0
8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H–C7H. .2–.0 Not used for S3C80A5B. — Register Pointer 1 Set 1 Bit Identifier RESET Value –...
Page 85: Spl Stack Pointer (Low Byte)
S3C80A5B CONTROL REGISTERS — Stack Pointer (Low Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (Low Byte) The SP value is undefined following a reset. STOPCON — Stop Control Register...
Page 86: Sym System Mode Register
Enable global interrupt processing NOTES: Because an external interface is not implemented for the S3C80A5B, SYM.7 must always be "0". You can select only one interrupt level at a time for fast interrupt processing. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.
Page 87: Timer 0 Control Register
S3C80A5B CONTROL REGISTERS T0CON — Timer 0 Control Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 Timer 0 Input Clock Selection Bits /4096 /256 External clock input (at the T0CK pin, P2.1) .5–.4...
Page 88: Timer 1 Overflow Interrupt
CONTROL REGISTERS S3C80A5B T1CON — Timer 1 Control Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 Timer 1 Input Clock Selection Bits Internal clock (counter a flip-flop, T-FF) .5–.4 Timer 1 Operating Mode Selection Bits...
Page 89: Overview
128. (The actual number of vectors used for KS88-series devices is always much smaller.) If an interrupt level has more than one vector address, the vector priorities are set in hardware. The S3C80A5B uses ten vectors. One vector address is shared by four interrupt sources.
Page 90: Interrupt Types
IRQn Type 3: IRQn Sn + 1 Sn + 2 Sn + m NOTES: The number of Sn and Vn value is expandable. In the S3C80A5B implementation, interrupt types 1, 2, and 3 is used. Figure 5-1. S3C8-Series Interrupt Types...
Page 91: S3C80A5B Interrupt Structure
— Vectored Interrupt — Non vectored interrupt (Reset interrupt): INTR The S3C80A5B microcontroller supports thirteen interrupt sources. Nine of the interrupt sources have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector address. Five interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.
Page 92: S3C80A5B Interrupt Structure
NOTE: For interrupt levels with two or more vectors, the lowest vector address usually the highest priority. For example, FAH has the higher priority (0) than FCH (1) within level IRQ0. These priorities are fixed in hardware. Figure 5-2. S3C80A5B Interrupt Structure...
Page 93: Interrupt Vector Addresses
INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C80A5B interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH. You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses.
Page 94: S3C80A5B Interrupt Vectors
INTERRUPT STRUCTURE S3C80A5B Table 5-1. S3C80A5B Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Interrupt Priority in Value Value Level Level √ 100H Basic timer overflow RESET – √ Timer 0 (match) IRQ0 √ Timer 0 overflow √ Timer 1 (match) IRQ1 √...
Page 95: Enable/Disable Interrupt Instructions (Ei, Di)
Interrupt priority register Controls the relative processing priorities of the interrupt levels. The five levels of the S3C80A5B are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ4, and group C is IRQ6, and IRQ7.
Page 96: Interrupt Processing Control Points
INTERRUPT STRUCTURE S3C80A5B INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are, therefore: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) —...
Page 97: Peripheral Interrupt Control Registers
S3C80A5B INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers...
Page 98: System Mode Register (Sym)
1 = Enable all interrupts 1 = High (Tri-state) Fast interrupt enable bit: Fast interrupt level 0 = Disable fast interrupt Not used for the S3C80A5B selection bits: 1 = Enable fast interrupt 0 0 0 IRQ0 0 0 1...
Page 99: Interrupt Mask Register (Imr)
S3C80A5B INTERRUPT STRUCTURE INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
Page 100: Interrupt Priority Register (Ipr)
4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. In the S3C80A5B implementation, interrupt levels 2 and 3 are not used. Therefore, IPR.2 and IPR.3 settings are not evaluated, as IRQ4 is the only remaining level in the group.
Page 101: Interrupt Priority Register (Ipr)
S3C80A5B INTERRUPT STRUCTURE Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W Group priority: Group A 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ1 > IRQ0 (note) Group B 0 = IRQ4 Undefined 1 = IRQ4 = B >...
Page 102: Interrupt Request Register (Irq)
INTERRUPT STRUCTURE S3C80A5B INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.
Page 103: Interrupt Pending Function Types
"0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3C80A5B interrupt structure, the timer 0 and timer 1 overflow interrupts (IRQ0 and IRQ1), and the counter A interrupt (IRQ4) belong to this category of interrupts whose pending condition is cleared automatically by hardware.
Page 104: Interrupt Source Polling Sequence
INTERRUPT STRUCTURE S3C80A5B INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.
Page 105: Generating Interrupt Vector Addresses
S3C80A5B INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack.
Page 106 — When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' ("FLAGS prime"). NOTE For the S3C80A5B microcontroller, the service routine for any one of the five interrupt levels: IRQ0, IRQ1, IRQ4 or IRQ6–IRQ7, can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1.
Page 107: Overview
S3C80A5B INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: —...
Page 108: Instruction Group Summary
INSTRUCTION SET S3C80A5B Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst, src Load dst, src Load bit dst, src Load external data memory dst, src Load program memory LDED dst, src Load external data memory and decrement...
Page 109 S3C80A5B INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions dst,src Add with carry dst,src dst,src Compare Decimal adjust Decrement DECW Decrement word dst,src Divide Increment INCW Increment word MULT dst,src Multiply dst,src Subtract with carry...
Page 110 INSTRUCTION SET S3C80A5B Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal...
Page 111 S3C80A5B INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic SWAP Swap nibbles CPU Control Instructions Complement carry flag...
Page 112: Flags Register (Flags)
INSTRUCTION SET S3C80A5B FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic.
Page 113: Flag Descriptions
S3C80A5B INSTRUCTION SET FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Page 114: Instruction Set Notation
INSTRUCTION SET S3C80A5B INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation –...
Page 115: Instruction Notation Conventions
S3C80A5B INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Bit (b) of working register Rn.b (n = 0–15, b = 0–7) Bit 0 (LSB) of working register Rn (n = 0–15)
Page 116: Opcode Quick Reference
INSTRUCTION SET S3C80A5B Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1...
Page 117 S3C80A5B INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – DJNZ NEXT r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER EXIT IDLE ↓ ↓ ↓ ↓ ↓ ↓ ↓...
Page 118: Condition Codes
INSTRUCTION SET S3C80A5B CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal.
Page 119: Instruction Descriptions
S3C80A5B INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...
Page 120: Adc Add With Carry
INSTRUCTION SET S3C80A5B — Add with carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Page 121: Add Add
S3C80A5B INSTRUCTION SET — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
Page 122: And Logical And
INSTRUCTION SET S3C80A5B — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...
Page 123: Band Bit And
S3C80A5B INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source).
Page 124: Bcp Bit Compare
INSTRUCTION SET S3C80A5B — Bit Compare dst,src.b dst(0) ← src(b) Operation: The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.
Page 125: Bitc Bit Complement
S3C80A5B INSTRUCTION SET BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 126: Bitr Bit Reset
INSTRUCTION SET S3C80A5B BITR — Bit Reset BITR dst.b dst(b) ← 0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 127: Bits Bit Set
S3C80A5B INSTRUCTION SET BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...
Page 128: Bor Bit Or
INSTRUCTION SET S3C80A5B — Bit OR dst,src.b dst.b,src dst(0) ← dst(0) OR src(b) Operation: dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected.
Page 129: Btjrf Bit Test, Jump Relative On False
S3C80A5B INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 130: Btjrt Bit Test, Jump Relative On True
INSTRUCTION SET S3C80A5B BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b If src(b) is a "1", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...
Page 131: Bxor Bit Xor
S3C80A5B INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.
Page 132: Call Call Procedure
INSTRUCTION SET S3C80A5B CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
Page 133: Ccf Complement Carry Flag
S3C80A5B INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
Page 134: Clr Clear
INSTRUCTION SET S3C80A5B — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: →...
Page 135: Com Complement
S3C80A5B INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
Page 136: Cp Compare
INSTRUCTION SET S3C80A5B — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Page 137: Cpije Compare, Increment, And Jump On Equal
S3C80A5B INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.
Page 138: Cpijne Compare, Increment, And Jump On Non-Equal
INSTRUCTION SET S3C80A5B CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA If dst – src "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement...
Page 139: Da Decimal Adjust
S3C80A5B INSTRUCTION SET — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed.
Page 140 INSTRUCTION SET S3C80A5B — Decimal Adjust (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1,R0 R1 ←...
Page 141: Dec Decrement
S3C80A5B INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.
Page 142: Decw Decrement Word
INSTRUCTION SET S3C80A5B DECW — Decrement Word DECW dst ← dst – 1 Operation: The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.
Page 143: Di Disable Interrupts
S3C80A5B INSTRUCTION SET — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.
Page 144: Div Divide (Unsigned)
INSTRUCTION SET S3C80A5B — Divide (Unsigned) dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.
Page 145: Djnz Decrement And Jump If Non-Zero
S3C80A5B INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
Page 146: Ei Enable Interrupts
INSTRUCTION SET S3C80A5B — Enable Interrupts SYM (0) ← 1 Operation: An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
Page 147: Enter Enter
S3C80A5B INSTRUCTION SET ENTER — Enter ENTER SP ← SP – 2 Operation: ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.
Page 148: Exit Exit
INSTRUCTION SET S3C80A5B EXIT — Exit EXIT IP ← @SP Operation: SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.
Page 149: Idle Idle Operation
S3C80A5B INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.
Page 150: Inc Increment
INSTRUCTION SET S3C80A5B — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.
Page 151: Incw Increment Word
S3C80A5B INSTRUCTION SET INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.
Page 152: Iret Interrupt Return
INSTRUCTION SET S3C80A5B IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) FLAGS ← @SP PC ↔ IP Operation: SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.
Page 153: Jp Jump
S3C80A5B INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.
Page 154: Jr Jump Relative
INSTRUCTION SET S3C80A5B — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
Page 155: Ld Load
S3C80A5B INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
Page 156 INSTRUCTION SET S3C80A5B — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0 = 10H LD R0,#10H →...
Page 157: Ldb Load Bit
S3C80A5B INSTRUCTION SET — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.
Page 158: Ldc/Lde Load Memory
INSTRUCTION SET S3C80A5B LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.
Page 159 S3C80A5B INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: ;...
Page 160: Ldcd/Lded Load Memory And Decrement
INSTRUCTION SET S3C80A5B LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location.
Page 161: Ldci/Ldei Load Memory And Increment
S3C80A5B INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location.
Page 162: Load Memory With Pre-Decrement
INSTRUCTION SET S3C80A5B LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src rr ← rr – 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented.
Page 163: Load Memory With Pre-Increment
S3C80A5B INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented.
Page 164: Ldw Load Word
INSTRUCTION SET S3C80A5B — Load Word dst,src dst ← src Operation: The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode...
Page 165: Mult Multiply (Unsigned)
S3C80A5B INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
Page 166: Next
INSTRUCTION SET S3C80A5B NEXT — Next NEXT PC ← @ IP Operation: IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.
Page 167: Nop No Operation
S3C80A5B INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.
Page 168: Or Logical Or
INSTRUCTION SET S3C80A5B — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...
Page 169: Pop Pop From Stack
S3C80A5B INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
Page 170: Popud Pop User Stack (Decrementing)
INSTRUCTION SET S3C80A5B POPUD — Pop User Stack (Decrementing) POPUD dst,src dst ← src Operation: IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.
Page 171: Popui Pop User Stack (Incrementing)
S3C80A5B INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.
Page 172: Push Push To Stack
INSTRUCTION SET S3C80A5B PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.
Page 173: Pushud Push User Stack (Decrementing)
S3C80A5B INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.
Page 174: Pushui Push User Stack (Incrementing)
INSTRUCTION SET S3C80A5B PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src IR ← IR + 1 Operation: dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.
Page 175: Rcf Reset Carry Flag
S3C80A5B INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1"...
Page 176: Ret Return
INSTRUCTION SET S3C80A5B — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.
Page 177: Rl Rotate Left
S3C80A5B INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.
Page 178: Rlc Rotate Left Through Carry
INSTRUCTION SET S3C80A5B — Rotate Left Through Carry dst (0) ? ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...
Page 179: Rr Rotate Right
S3C80A5B INSTRUCTION SET — Rotate Right C ←?dst (0) Operation: dst (7) ← dst (0) dst (n? ? ? ? ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
Page 180: Rrc Rotate Right Through Carry
INSTRUCTION SET S3C80A5B — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...
Page 181: Sb0 Select Bank 0
S3C80A5B INSTRUCTION SET — Select Bank 0 Operation: BANK.0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected.
Page 182: Sb1 Select Bank 1
INSTRUCTION SET S3C80A5B — Select Bank 1 Operation: BANK.1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.)
Page 183: Sbc Subtract With Carry
S3C80A5B INSTRUCTION SET — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.
Page 184: Scf Set Carry Flag
INSTRUCTION SET S3C80A5B — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex)
Page 185: Sra Shift Right Arithmetic
S3C80A5B INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.
Page 186: Srp/Srp0/Srp1
INSTRUCTION SET S3C80A5B SRP/SRP0/SRP1 — Set Register Pointer SRP0 SRP1 Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7)
Page 187: Stop Stop Operation
S3C80A5B INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
Page 188: Sub Subtract
INSTRUCTION SET S3C80A5B — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.
Page 189: Swap Swap Nibbles
S3C80A5B INSTRUCTION SET SWAP — Swap Nibbles SWAP dst (0 – 3) ← dst (4 – 7) Operation: The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise.
Page 190: Tcm Test Complement Under Mask
INSTRUCTION SET S3C80A5B — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).
Page 191: Tm Test Under Mask
S3C80A5B INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
Page 192: Wfi Wait For Interrupt
INSTRUCTION SET S3C80A5B — Wait For Interrupt Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt .
Page 193: Xor Logical Exclusive Or
S3C80A5B INSTRUCTION SET — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
Page 194: Overview
CLOCK CIRCUITS OVERVIEW The clock frequency generated for the S3C80A5B by an external crystal, or supplied by an external clock source, can range from 1MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON register settings, is 8 MHz. The X...
Page 195: Clock Status During Power-Down Modes
An external interrupt with an RC-delay noise filter (for S3C80A4A/C80A8A/ C80A5A, INT0-4) is fiexed to release Stop mode and "wake up" the main oscillator. Because the S3C80A5B has no subsystem clock, the 3-bit CLKCON signature code (CLKCON.2-CLKCON.0) is no meaning. Figure 7-3. System Clock Circuit Diagram...
Page 196: System Clock Control Register (Clkcon)
CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release. (This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7. In S3C80A5B, this bit is not valid any more. Actually bit 7, 6, 5, 2, 1, and 0 are no meaning in S3C80A5B.
Page 197: System Reset
Figure 8-1. Rese t Block Diagram LVD RESET The Low Voltage detect circuit is built on the S3C80A5B product for system reset not in stop mode. When the operating status is not stop mode it detects a slope of V...
Page 198: Interrupt With Reset(Intr)
A non vectored interrupt called Interrupt with reset (INTR) is built in S3C80A5B to release stop status with system reset. When a falling/rising edge occurs at Port 0 during stop mode, INTR signal is generated and it makes the system reset pulse. An INTR signal is generated relating to interaction between Port 0 and operating status.
Page 199: System Reset Operation
System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal CPU and peripheral modules. This procedure brings the S3C80A5B into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance.
Page 200: Hardware Reset Values
RESET and POWER-DOWN S3C80A5B HARDWARE RESET VALUES Tables 5-1 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
Page 201 Interrupt priority register NOTES: Although the SYM register is not used for the S3C80A5B , SYM.5 should always be "0". If you accidentally write a 1 to this bit during normal operation, a system malfunction may occur. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are read/write addressable.
Page 202: Power-Down Modes
RESET and POWER-DOWN S3C80A5B POWER-DOWN MODES STOP MODE Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 uA at 5.5 V.
Page 203: To Divide Stop Mode Releasing And Por
RESET S3C80A5B and POWER-DOWN PROGRAMMING TIP — To Divide STOP Mode Releasing and POR. This example shows how to enter the stop mode and how to know it is stop mode releasing or power on RESET. 0100H ; Reset address...
Page 204 RESET and POWER-DOWN S3C80A5B PROGRAMMING TIP — To Divide STOP Mode Releasing and POR. (Continued) CHK_W @R0,R0 R0,#0B0H UGE,CHK_W MAIN: P0,#0FFH EQ,ENT_STOP • • • T,MAIN ENT_STOP STOPCON,#0A5H ; Enter the STOP mode. STOP RESET • • •...
Page 205: Idle Mode
RESET S3C80A5B and POWER-DOWN IDLE MODE Idle mode is invoked by the instruction IDLE (OPCODE 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active: —...
Page 206: Summary Table Of Stop Mode, And Idle Mode
RESET and POWER-DOWN S3C80A5B SUMMARY TABLE OF STOP MODE, AND IDLE MODE Table 8-2. Summary of Each Mode Item/Mode IDLE STOP Approach Condition is higher than V is higher than V STOPCON ≤ A5H IDLE (instruction). STOP instruction Release Source...
Page 207: Overview
The S3C80A5B microcontroller has three bit-programmable I/O ports, P0–P2. Two ports, P0-P1, are 8-bit ports and P2 is a 3-bit port. This gives a total of 19 I/O pins in the S3C80A5B"s 24-pin package. Each port is bit-programmable and can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers.
Page 208: Port Data Registers
I/O PORTS S3C80A5B PORT DATA REGISTERS Table 9-2 gives you an overvi ew of the register locations of all three S3C80A5B port data registers. Data registers for ports 0, and 1 have the general format. NOTE The data register for port 2, P2, contains three bits for P2.0, P2.1 and P2.2, and an additional status bit for carrier signal on/off.
Page 209: Port
S3C80A5B I/O PORTS PORT 0 Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment using P0PUR register settings and all pins have noise filters for external interrupt inputs.
Page 210: Port 0 Interrupt Enable Register (P0Int)
I/O PORTS S3C80A5B Port 0 Control Register, Low Byte (P0CONL) E9H, Set 1, R/W P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0CONL Pin Configureation Settings: Input mode; interrupt on falling edges Input mode; interrupt on rising and falling edges Push-pull output mode Input mode; interrupt on rising edges Figure 9-3.
Page 211: Port 0 External Interrupt Control Register (P0Int)
S3C80A5B I/O PORTS Port 0 Interrup Enable Register (P0INT) F1H, Set 1, R/W P0.6/INT4 P0.4/INT4 P0.2/INT2 P0.0/INT0 P0.7/INT4 P0.5/INT4 P0.3/INT3 P0.1/INT1 Port 0 Interrupt Enable Bits: Disable interrupt Enable interrupt Figure 9-4. Port 0 External Interrupt Control Register (P0INT) Port 0 Interrup Pending Register (P0PND) F2H, Set 1, R/W P0.6/INT4...
Page 212: Port
I/O PORTS S3C80A5B PORT 1 Port 1 is a bit-programmable 8-bit I/O port. Port 1 pins are accessed directly by read/write operations to the port 1 data register, P1 (set 1, E1H). To configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers: P1CONH (set 1, EAH) for the upper nibble pins, P1.7–P1.4, and P1CONL (set 1, EBH) for the lower nibble pins, P1.3–P1.0.
Page 213: Port 1 Low-Byte Control Register (P1Conl)
S3C80A5B I/O PORTS Port 1 Control Register, Low Byte (P1CONL) EBH, Set 1, R/W P1.0 P1.1 P1.2 P1.3 P1CONL Pin Configureation Settings: Input mode Open-drain output mode Push-pull output mode Invalid setting Figure 9-7. Port 1 Low-Byte Control Register (P1CONL)
Page 214: Port
I/O PORTS S3C80A5B PORT 2 Port 2 is a bit-programmable 3-bit I/O port. Port 2 pins are accessed directly by read/write operations to the port 2 data register, P2 (set 1, E2H). You can configure port 2 pins individually to Input mode, open-drain output mode, or push-pull output mode.
Page 215: Port 2 Data Register (P2)
S3C80A5B I/O PORTS Port 2 Data Register (P2) E2H, R/W P2.0/T0_PWM Not used for S3C80A5 P2.1/REM/TOCK Carrier on/off for Remote Controller P2.2 Not used for S3C80A5 Figure 9-9. Port 2 Data Register (P2)
Page 216: Module Overview
BASIC TIMER AND TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The S3C80A5B has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0. Basic Timer (BT) You can use the basic timer (BT) in two different ways: —...
Page 217 BASIC TIMER and TIMER 0 S3C80A5B Basic Timer Control Register (BTCON) D3H, Set 1, R/W Watchdog function enable bits: Divider clear bit for basic 1010B = Disable watchdog timer timer and timer 0: Other value = Enable watchdog timer 0 = No effect...
Page 218: Basic Timer Function Description
S3C80A5B BASIC TIMER AND TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by enabling the watchdog function. A reset clears BTCON to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting),divided by 4096, as the BT clock.
Page 219 BASIC TIMER and TIMER 0 S3C80A5B Timer 0 Control Register (T0CON) D2H, Set 1, R/W Timer 0 match interrupt pending bit: Timer 0 input clock selection bits: 0 = No interrupt pending 00 = f /4096 0 = Clear pending bit (write)
Page 220: Timer 0 Function Description
S3C80A5B BASIC TIMER AND TIMER 0 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors FAH and FCH) The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match interrupt (T0INT). T0OVF is interrupt level IRQ0, vector FAH. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, FCH.
Page 221: Simplified Timer 0 Function Diagram: Pwm Mode
BASIC TIMER and TIMER 0 S3C80A5B Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register.
Page 222: Basic Timer And Timer 0 Block Diagram
S3C80A5B BASIC TIMER AND TIMER 0 Bit 1 RESET or Stop Basic Timer Control Register Bits 3,2 (Write '1010xxxxB' to disable) Data Bus Clear 1/4096 RESET 8-Bit Basic Counter 1/1024 (Read-Only) 1/128 Bit 2 Bit 0 Bits 7,6 Data Bus...
Page 223: Configuring The Basic Timer
BASIC TIMER and TIMER 0 S3C80A5B PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications: 0100H RESET ; Disable all interrupts BTCON,#03H ; Enable the watchdog timer CLKCON,#18H ; Non-divided clock ;...
Page 224: Programming Timer 0
S3C80A5B BASIC TIMER AND TIMER 0 Programming Tip — Programming Timer 0 This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows: —...
Page 225 BASIC TIMER and TIMER 0 S3C80A5B PROGRAMMING TIP — Programming Timer 0 (Continued) T0INT PUSH ; Save RP0 to stack ; RP0 ← 60H SRP0 #60H ; R0 ← R0 + 1 ; R2 ← R2 + R0 R2,R0 ; R3 ← R3 + R2 + Carry R3,R2 ;...
Page 226: Overview
— To generate a timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit timer 1 count value matches the 16-bit value written to the reference data registers. In the S3C80A5B interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1 match. 11-1...
Page 227 TIMER 1 S3C80A5B TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the 16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’.
Page 228: Timer 1 Block Diagram
S3C80A5B TIMER 1 T1CON.2 T1CON.7-.6 IRQ1 CAOF (T-F/F) T1CON.3 Clear 16-Bit Up-Counter (Read-Only) (note) Match 16-Bit Comparator T1CON.1 T1CON.5-.4 T1CON.0 IRQ1 Timer 1 High/Low Buffer Register T1CON.3 Match Signal T1OVF Timer 1 Data High/Low Register Data Bus NOTES: Match signal is occured only in interval mode.
Page 229: Timer 1 Control Register (T1Con)
TIMER 1 S3C80A5B TIMER 1 CONTROL REGISTER (T1CON) The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains control settings for the following T1 functions: — Timer 1 input clock selection — Timer 1 operating mode selection —...
Page 230: Timer 1 Registers
S3C80A5B TIMER 1 Timer 1 Counter High-Byte Register (T1CNTH) F6H, Set 1, R Reset Value : 00H Timer 1 Counter Low-Byte Register (T1CNTL) F7H, Set 1, R Reset Value : 00H Timer 1 Data High-Byte Register (T1DATAH) F8H, Set 1, R/W...
Page 231: Overview
COUNTER A COUNTER A OVERVIEW The S3C80A5B microcontroller has an 8-bit counter called counter A. Counter A, which can be used to generate the carrier frequency, has the following components (see Figure 12-1): — Counter A control register, CACON — 8-bit down counter with auto-reload function —...
Page 232: Counter A Block Diagram
COUNTER A S3C80A5B CACON.6-.7 DIV 1 DIV 2 8-Bit CACON.0 To Other Block Down Counter (CAOF) DIV 4 (P3.1/REM) DIV 8 CACON.3 Repeat Control Interrupt IRQ4 INT.GEN. Control (CAINT) Counter A Data Low Byte Register CACON.2 CACON.4-.5 Counter A Data...
Page 233: Counter A Control Register (Cacon)
S3C80A5B COUNTER A COUNTER A CONTROL REGISTER (CACON) The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON contains control settings for the following functions (see Figure 12-2): — Counter A clock source selection —...
Page 234 COUNTER A S3C80A5B Counter A Data High-Byte Register (CADATAH) F4H, Set 1, R/W Reset Value : FFh Counter A Data Low-Byte Register (CADATAL) F5H, Set 1, R/W Reset Value : FFh Figure 12-3. Counter A Registers COUNTER A PULSE WIDTH CALCULATIONS...
Page 235: Counter A Output Flip-Flop Waveforms In Repeat Mode
S3C80A5B COUNTER A Counter A Clock CAOF = '0' CADATAL = 01-FFH High CADATAH = 001H CAOF = '0' CADATAL = 00H CADATAH = 01-FFH CAOF = '0' CADATAL = 00H CADATAH = 00H CAOF = '1' CADATAL = 00H...
Page 236: To Generate 38 Khz, 1/3Duty Signal Through P2.1
COUNTER A S3C80A5B PROGRAMMING TIP — To Generate 38 kHz, 1/3duty Signal Through P2.1 This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are: 8.795 µs...
Page 237: To Generate A One Pulse Signal Through P2.1
S3C80A5B COUNTER A PROGRAMMING TIP — To Generate a One Pulse Signal Through P2.1 This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40 µs width pulse. The program parameters are: 40 µs...
Page 238: Overview
S3C80A5B ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, S3C80A5B electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode —...
Page 239: Absolute Maximum Ratings
ELECTRICAL DATA 3C80A5B Table 13-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply voltage – – 0.3 to + 6.5 Input voltage – – 0.3 to V + 0.3 Output voltage All output pins – 0.3 to V + 0.3 Output current high One I/O pin active...
Page 240 S3C80A5B ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) ° ° = – 25 C to + 85 C, V = 2.0 V to 5.5 V) Parameter Symbol Conditions Unit Output low = 2.4 V, I = 12 mA, –...
Page 241: Characteristics Of Low Voltage Detect Circuit
Symbol Conditions Unit ∆V Hysteresys voltage of LVD – – (Slew Rate of LVD) Low level detect voltage (S3C80A5B) – 2.20 2.40 Table 13-4. Data Retention Supply Voltage in Stop Mode ° ° = – 25 C to + 85...
Page 242: Input Timing For External Interrupts (Port 0)
S3C80A5B ELECTRICAL DATA INTL INTH 0.8 V 0.2 V NOTE: The unit tCPU means one CPU clock period. Figure 13-1. Input Timing for External Interrupts (Port 0) Table 13-7. Oscillation Characteristics ° ° = – 25 C + 85 Oscillator...
Page 243: Operating Voltage Range Of S3C80A5B
8 MHz 1.00 MHz 6 MHz 670 kHz 4 MHz 500 kHz 250 kHz 8.32 kHz 400 kHz Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16) Figure 13-2. Operating Voltage Range of S3C80A5B...
Page 244: Overview
S3C80A5B MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C80A5B microcontroller is currently available in a 24-pin SOP and SDIP package. 24-SOP-375 + 0.10 0.15 - 0.05 15.74 MAX ± 0.20 15.34 0.10 MAX 1.27 (0.69) + 0.10 0.38 - 0.05 NOTE: Dimensions are in millimeters.
Page 245: Pin Sdip Package Mechanical Data
MECHANICAL DATA S3C80A5B 0-15 24-SDIP-300 23.35 MAX ± 0.20 22.95 ± 0.10 0.46 1.778 ± 0.10 (1.70) 0.89 NOTE: Dimensions are in millimeters. Figure 14-2. 24-Pin SDIP Package Mechanical Data 14-2...
Page 246 __________________________________ (Person placing the order) (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE: Please one more check whether the selected device is S3C80A5B.
Page 247 _______________________________________ (Person Placing the Risk Order) (SEC Sales Representative) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE:...
Page 248 Remocon Other Please describe in detail its application (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE: Please one more check whether the selected device is S3C80A5B.
Page 249 __________________________________ (Person placing the order) (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) NOTE: Please one more check whether the selected device is S3C80A5B...
Page 250 Once you choose a read protection, you cannot read again the programming code from the EPROM. OTP Writing will be executed in our manufacturing site. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program.

Samsung S3C80A5B User Manual

Chapter 1 Product Overview

Chapter 2 Address Spaces

Chapter 3 Addressing Modes

Chapter 11 Timer 1 Overflow Interrupt

Chapter 12 Counter a

Chapter 4 Control Registers

Chapter 5 Interrupt Structure

Chapter 13 Electrical Data

Chapter 8 System Reset

Chapter 9

Chapter 10 Basic Timer and Timer 0

Chapter 7 Clock Circuit

Chapter 6 Instruction Set

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Summary of Contents for Samsung S3C80A5B