Target Register Addresses: Target[Q] - Delta Tau Power PMAC User Manual

Power PMAC User's Manual
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3 (11 ): (Reserved for future use)
2
Bits 4 and 5 of Ctrl determine the boundary mode for the dimension with index n = 1 (which uses
the motor specified by Source[1]). This 2-bit component has the possible values as for dimension
n = 0.
Bits 6 and 7 of Ctrl determine the boundary mode for the dimension with index n = 2 (which uses
the motor specified by Source[2]). This 2-bit component has the possible values as for dimension
n = 0.
Examples
rd
For a 3D table with 3 -order interpolation in all dimensions, and maintain-last-correction
boundary mode in all dimensions, Ctrl should be set to 01010111 binary, which is $57
hexadecimal, or 87 decimal. The value can be entered in decimal or hexadecimal form. It will be
reported in decimal form.
rd
For a 1D table with 3 -order interpolation and rollover boundary mode, Ctrl should be set to
xxxx0001 binary, where x represents a "don't-care" bit. Generally the don't-care bits are set to 0,
so the value is $01 hexadecimal, or 1 decimal.
st
For a 2D table with 1 -order interpolation in both dimensions, and mirror boundary mode, Ctrl
should be set to xx101000 binary. where x represents a "don't-care" bit. Generally the don't-care
bits are set to 0, so the value is $28 hexadecimal, or 40 decimal.

Target Register Addresses: Target[q]

CompTable[m].Target[q] contains the address to which the correction computed by the table
will be written. The target index q can take a value from 0 to 7, so a single table can have up to 8
target registers. If the Target[q] element has a value of 0 (the default), no value will be written
for that index.
If all the Target[q] elements for a table have a value of 0, the table will have no effect, even if
enabled (although processor time will still be devoted to the computation of corrections.) Setting
these elements to 0 can be a simple way of temporarily disabling an individual table. However, in
doing this, the last computed correction(s) will be left in the target register(s); it may be desirable
to then set the register value to 0 by writing directly to the register.
The target registers can be actual or command position-compensation, torque-compensation, or
backlash-compensation registers for motors. The "target" motor or motors do not need to be the
same motor(s) as the "source" motors, permitting "cross-axis" compensation for uses such as
straightness correction. Other registers are not permitted as targets for compensation tables.
Note that Turbo PMAC has separate classes of tables for position compensation, backlash
compensation, and torque compensation. In Power PMAC, every table can provide each of these
types of compensation, depending on which target register is specified.
Setting Up Compensation Tables 340