Texas Instruments Tiva TM4C123GH6PM User Manual

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Tiva™ TM4C123GH6PM

ROM USER'S GUIDE

ROM-TM4C123GH6PM-UG-750

Texas Instruments Incorporated

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Page 2: Copyright
Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semicon- ductor products and disclaimers thereto appears at the end of this document.
Page 3: Table Of Contents
Table of Contents Table of Contents Copyright ........... . . Revision Information .
Page 4 Table of Contents 15.1 Introduction ..........153 15.2 Functions .
Page 5: Introduction
Introduction Introduction The TM4C123GH6PM ROM contains the TivaWare™ Peripheral Driver Library and the TivaWare Boot Loader. The peripheral driver library can be utilized by applications to reduce their ﬂash footprint, allowing the ﬂash to be used for other purposes (such as additional features in the appli- cation).
Page 6 Introduction ROM_GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_0, GPIO_DIR_MODE_OUT); // ..See the “Using the ROM” chapter of the TivaWare Peripheral Driver Library User’s Guide for more details on calling the ROM functions and using driverlib/rom.h. The API provided by the ROM can be utilized by any compiler so long as it complies with the Embedded Applications Binary Interface (EABI), which includes all recent compilers for the Cortex- M4 microcontroller.
Page 7: Boot Loader
Boot Loader Boot Loader Introduction ....................7 Serial Interfaces .
Page 8 Boot Loader Therefore, the UART must be conﬁgured and the UART pins switched to their hardware function before calling the boot loader. 2.2.2 SSI Interface The SSI pins SSIFss, SSIClk, SSITx, and SSIRx are used to communicate with the boot loader. The device communicating with the boot loader is responsible for driving the SSIRx, SSIClk, and SSIFss pins, while the microcontroller drives the SSITx pin.
Page 9 Boot Loader 4. Wait for a single-byte acknowledgment from the device that it either properly received the data or that it detected an error in the transmission. The following steps must be performed to successfully receive a packet: 1. Wait for non-zero data to be returned from the device. This is important as the device may send zero bytes between a sent and received data packet.
Page 10 Boot Loader This command is sent to the boot loader to indicate where COMMAND_DOWNLOAD = 0x21 to store data and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB ﬁrst. The ﬁrst 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent.
Page 11 Boot Loader This command returns the status of the last command that was COMMAND_GET_STATUS = 0x23 issued. Typically, this command should be received after every command is sent to ensure that the previous command was suc- cessful or, if unsuccessful, to properly respond to a failure. The command requires one byte in the data of the packet and the boot loader should respond by sending a packet with one byte of data that contains the current status code.
Page 12: Usb Interface
Boot Loader This command is used to tell the boot loader to reset. This is COMMAND_RESET = 0x25 used after downloading a new image to the microcontroller to cause the new application to start from a reset. The normal boot sequence occurs and the image runs as if from a hardware reset.
Page 13 Boot Loader tionally, upload the existing ﬁrmware image to the USB host. The full speciﬁcation for the device class can be downloaded from the USB Implementer’s Forum web site at http://www.usb.org/developers/devclass_docs#approved. All communication with the DFU device takes place using the USB control endpoint, endpoint 0. The device publishes a standard device descriptor with vendor, product, device revisions and strings.
Page 14 Boot Loader This IN request is used to request a block of binary data from DFU_UPLOAD the device. The data returned is device-speciﬁc but is typi- cally the contents of a region of the device’s ﬂash memory or a device-speciﬁc response to a command previously sent via a DFU_DNLOAD request.
Page 15 Boot Loader DFU Device Enumerated Send DFU_DNLOAD with a block of firmware image data. Send DFU_DNLOAD with More data a zero-length payload. to send? Send DFU_GETSTATUS Send DFU_GETSTATUS State is State is State is DNLOAD_SYNC DNLOAD_IDLE? ERROR? or DNBUSY? State is Report the error condition ERROR? Exit...
Page 16 Boot Loader 2.3.4 Tiva-Speciﬁc USB Download Commands The DFU class speciﬁcation provides the framework necessary to download and upload ﬁrmware ﬁles to the USB device but does not specify the actual format of the binary data that is transferred. As a result, different device implementations have used different methods to perform operations that are not deﬁned in the standard such as: Setting the address to ﬂash a downloaded binary.
Page 17 Boot Loader IDLE state to contain a command header but does not look for a command unless the state is IDLE. This protocol allows an application that is unaware of the command header to download a DFU- wrapped binary image using a standard sequence of multiple DFU_DNLOAD and DFU_GETSTATUS requests without the need to insert additional command headers during the download.
Page 18 Boot Loader This command is used to set the address range of the content to be returned DFU_CMD_READ on subsequent DFU_UPLOAD requests from the host. The start address is provided in terms of 1024-byte ﬂash blocks. To convert a byte address to a block address, divide by 1024. The start address must always be on a 1024-byte boundary.
Page 19 Boot Loader This command is used to check a region of ﬂash to ensure that it is completely DFU_CMD_CHECK erased. The start address is provided in terms of 1024-byte ﬂash blocks. To convert a byte address to a block address, divide by 1024. The start address must always be on a 1024-byte boundary.
Page 20 Boot Loader This command is used to query information relating to the target de- DFU_CMD_INFO vice and programmable region of ﬂash. The device information structure, tDFUDeviceInfo, is returned on the next DFU_UPLOAD request following this command. The format of the command is as follows: uint8_t pui8Data[8];...
Page 21 When the USB boot loader is entered because the ﬂash was empty, the boot ROM offers no customization and provides generic “Texas Instruments” and “Device Firmware Update” strings to the host as identiﬁers. The USB boot loader is called by an application via a call to ROM_UpdateUSB(), which takes a single pointer as an argument that is a pointer to an array containing the values that the boot loader uses for customization.
Page 22 Device Version (default 0x110) All strings in multiple languages The defaults for the strings are a Manufacturer set to “Texas Instruments”, Product set to “Device Firmware Update”, and serial number set to “1.0”. If the application is providing a structure to the boot loader with custom values, then the ﬁrst 12 bytes must contain valid data.
Page 23 Boot Loader Byte Description Size of the header(Number of Languages * 2) + 2 USB_DTYPE_STRING Language ID 0 bits[7:0] Language ID 0 bits[15:8] Language ID n bits[7:0] Language ID n bits[15:8] Language 0 Manufacturer string size in bytes + 2 USB_DTYPE_STRING Language 0 Manufacturer Unicode String Language 0 Product string size in bytes + 2...
Page 24 // Language code for US English. (17 * 2) + 2, // Size of Manufacturer String. // "Texas Instruments" USB_DTYPE_STRING, ’T’, 0, ’e’, 0, ’x’, 0, ’a’, 0, ’s’, 0, ’ ’, 0, ’I’, 0, ’n’, 0, ’s’, 0, ’t’, 0, ’r’, 0, ’u’, 0, ’m’, 0, ’e’, 0, ’n’, 0, ’t’, 0, ’s’, 0,...
Page 25 Boot Loader // "My Company" USB_DTYPE_STRING, ’M’, 0, ’y’, 0, ’ ’, 0, ’C’, 0, ’o’, 0, ’m’, 0, ’p’, 0, ’a’, 0, ’n’, 0, ’y’, 0 (23 * 2) + 2, // Size of Product String. USB_DTYPE_STRING, // "Device Firmware Upgrade" ’D’, 0, ’e’, 0, ’v’, 0, ’i’, 0, ’c’, 0, ’e’, 0, ’...
Page 26 Boot Loader April 8, 2013...
Page 27: Aes Data Tables
AES Data Tables AES Data Tables Introduction ....................27 Functions .
Page 28 AES Data Tables ulForwardTable This table contains the forward polynomial table, as used by the XySSL AES implementation. ucReverseSBox This table contains the reverse S-Box, as deﬁned by the AES standard. This is simply the reverse of ucForwardSBox. ulReverseTable This table contains the reverse polynomial table, as used by the XySSL AES implementation.
Page 29: Analog Comparator
Analog Comparator Analog Comparator Introduction ....................29 Functions .
Page 30 Analog Comparator Parameters: ui32Base is the base address of the comparator module. ui32Comp is the index of the comparator to conﬁgure. ui32Conﬁg is the conﬁguration of the comparator. Description: This function conﬁgures a comparator. The ui32Conﬁg parameter is the result of a logical OR operation between the COMP_TRIG_xxx, COMP_INT_xxx, COMP_ASRCP_xxx, and COMP_OUTPUT_xxx values.
Page 31 Analog Comparator ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_COMPARATORTABLE is an array of pointers located at ROM_APITABLE[6]. ROM_ComparatorIntClear is a function pointer located at ROM_COMPARATORTABLE[0]. Parameters: ui32Base is the base address of the comparator module. ui32Comp is the index of the comparator.
Page 32 Analog Comparator 4.2.1.4 ROM_ComparatorIntEnable Enables the comparator interrupt. Prototype: void ROM_ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_COMPARATORTABLE is an array of pointers located at ROM_APITABLE[6]. ROM_ComparatorIntEnable is a function pointer located at ROM_COMPARATORTABLE[4]. Parameters: ui32Base is the base address of the comparator module.
Page 33 Analog Comparator 4.2.1.6 ROM_ComparatorRefSet Sets the internal reference voltage. Prototype: void ROM_ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_COMPARATORTABLE is an array of pointers located at ROM_APITABLE[6]. ROM_ComparatorRefSet is a function pointer located at ROM_COMPARATORTABLE[2]. Parameters: ui32Base is the base address of the comparator module.
Page 34 Analog Comparator COMP_REF_2_26875V to set the reference voltage to 2.26875 V COMP_REF_2_371875V to set the reference voltage to 2.371875 V Returns: None. 4.2.1.7 ROM_ComparatorValueGet Gets the current comparator output value. Prototype: bool ROM_ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_COMPARATORTABLE is an array of pointers located at ROM_APITABLE[6].
Page 35: Analog To Digital Converter (Adc)
Analog to Digital Converter (ADC) Analog to Digital Converter (ADC) Introduction ....................35 Functions .
Page 36 Analog to Digital Converter (ADC) void ROM_ADCPhaseDelaySet (uint32_t ui32Base, uint32_t ui32Phase) void ROM_ADCProcessorTrigger (uint32_t ui32Base, uint32_t ui32SequenceNum) uint32_t ROM_ADCReferenceGet (uint32_t ui32Base) void ROM_ADCReferenceSet (uint32_t ui32Base, uint32_t ui32Ref) void ROM_ADCSequenceConﬁgure (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Trigger, uint32_t ui32Priority) int32_t ROM_ADCSequenceDataGet (uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t pui32Buffer) void ROM_ADCSequenceDisable...
Page 37 Analog to Digital Converter (ADC) ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when ADC output is in the low-band only if ADC output has been in the high-band since the last trigger output. ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC output transitions into low-band only if ADC output has been in the high-band since the last trigger output.
Page 38 Analog to Digital Converter (ADC) 5.2.1.2 ROM_ADCComparatorIntClear Clears sample sequence comparator interrupt source. Prototype: void ROM_ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCComparatorIntClear is a function pointer located at ROM_ADCTABLE[21]. Parameters: ui32Base is the base address of the ADC module.
Page 39 Analog to Digital Converter (ADC) 5.2.1.4 ROM_ADCComparatorIntEnable Enables a sample sequence comparator interrupt. Prototype: void ROM_ADCComparatorIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCComparatorIntEnable is a function pointer located at ROM_ADCTABLE[19]. Parameters: ui32Base is the base address of the ADC module.
Page 40 Analog to Digital Converter (ADC) Prototype: void ROM_ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32LowRef, uint32_t ui32HighRef) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCComparatorRegionSet is a function pointer located at ROM_ADCTABLE[16]. Parameters: ui32Base is the base address of the ADC module.
Page 41 Analog to Digital Converter (ADC) Description: Because the digital comparator uses current and previous ADC values, this function is provide to allow the comparator to be reset to its initial value to prevent stale data from being used when a sequence is enabled. Returns: None.
Page 42 Analog to Digital Converter (ADC) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCIntClear is a function pointer located at ROM_ADCTABLE[4]. Parameters: ui32Base is the base address of the ADC module. ui32SequenceNum is the sample sequence number.
Page 43 Analog to Digital Converter (ADC) Prototype: void ROM_ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCIntEnable is a function pointer located at ROM_ADCTABLE[2]. Parameters: ui32Base is the base address of the ADC module.
Page 44 Analog to Digital Converter (ADC) 5.2.1.13 ROM_ADCPhaseDelayGet Gets the phase delay between a trigger and the start of a sequence. Prototype: uint32_t ROM_ADCPhaseDelayGet(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCPhaseDelayGet is a function pointer located at ROM_ADCTABLE[25].
Page 45 Analog to Digital Converter (ADC) as ADC_PHASE_0 and ADC_PHASE_180) and having each ADC module sample the same analog input, it is possible to increase the sampling rate of the analog input (with samples N, N+2, N+4, and so on, coming from the ﬁrst ADC and samples N+1, N+3, N+5, and so on, coming from the second ADC).
Page 46 Analog to Digital Converter (ADC) Parameters: ui32Base is the base address of the ADC module. Description: Returns the value of the ADC reference setting. The returned value is one of ADC_REF_INT or ADC_REF_EXT_3V. Returns: The current setting of the ADC reference. 5.2.1.17 ROM_ADCReferenceSet Selects the ADC reference.
Page 47 Analog to Digital Converter (ADC) Parameters: ui32Base is the base address of the ADC module. ui32SequenceNum is the sample sequence number. ui32Trigger is the trigger source that initiates the sample sequence; must be one of the ADC_TRIGGER_ values. ui32Priority is the relative priority of the sample sequence with respect to the other sample sequences.
Page 48 Analog to Digital Converter (ADC) 5.2.1.19 ROM_ADCSequenceDataGet Gets the captured data for a sample sequence. Prototype: int32_t ROM_ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t * pui32Buffer) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCSequenceDataGet is a function pointer located at ROM_ADCTABLE[0].
Page 49 Analog to Digital Converter (ADC) Returns: None. 5.2.1.21 ROM_ADCSequenceEnable Enables a sample sequence. Prototype: void ROM_ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCSequenceEnable is a function pointer located at ROM_ADCTABLE[5]. Parameters: ui32Base is the base address of the ADC module.
Page 50 Analog to Digital Converter (ADC) 5.2.1.23 ROM_ADCSequenceOverﬂowClear Clears the overﬂow condition on a sample sequence. Prototype: void ROM_ADCSequenceOverflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5]. ROM_ADCSequenceOverflowClear is a function pointer located at ROM_ADCTABLE[10].
Page 51 Analog to Digital Converter (ADC) Description: This function will set the conﬁguration of the ADC for one step of a sample sequence. The ADC can be conﬁgured for single-ended or differential operation (the ADC_CTL_D bit selects differential operation when set), the channel to be sampled can be chosen (the ADC_CTL_CH0 through ADC_CTL_CH23 values), and the internal temperature sensor can be selected (the ADC_CTL_TS bit).
Page 52 Analog to Digital Converter (ADC) Returns: Returns zero if there was not an underﬂow, and non-zero if there was. 5.2.1.26 ROM_ADCSequenceUnderﬂowClear Clears the underﬂow condition on a sample sequence. Prototype: void ROM_ADCSequenceUnderflowClear(uint32_t ui32Base, uint32_t ui32SequenceNum) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_ADCTABLE is an array of pointers located at ROM_APITABLE[5].
Page 53: Controller Area Network (Can)
Controller Area Network (CAN) Controller Area Network (CAN) Introduction ....................53 Functions .
Page 54: Functions
Controller Area Network (CAN) conﬁguration of a message object. Reading the message object using this function will also clear any pending interrupt on the message object. Once a message object has been conﬁgured using ROM_CANMessageSet(), it has allocated the message object and will continue to perform its programmed function unless it is released with a call to ROM_CANMessageClear().
Page 55 Controller Area Network (CAN) void ROM_CANBitTimingGet (uint32_t ui32Base, tCANBitClkParms psClkParms) void ROM_CANBitTimingSet (uint32_t ui32Base, tCANBitClkParms psClkParms) void ROM_CANDisable (uint32_t ui32Base) void ROM_CANEnable (uint32_t ui32Base) bool ROM_CANErrCntrGet (uint32_t ui32Base, uint32_t pui32RxCount, uint32_t pui32TxCount) void ROM_CANInit (uint32_t ui32Base) void ROM_CANIntClear (uint32_t ui32Base, uint32_t ui32IntClr) void ROM_CANIntDisable (uint32_t ui32Base, uint32_t ui32IntFlags)
Page 56 Controller Area Network (CAN) network length is short. If tighter timing requirements or longer network lengths are needed, then the ROM_CANBitTimingSet() function is available for full customization of all of the CAN bit timing values. Since not all bit rates can be matched exactly, the bit rate is set to the value closest to the desired bit rate without being higher than the ui32BitRate value.
Page 57 Controller Area Network (CAN) Parameters: ui32Base is the base address of the CAN controller. psClkParms points to the structure with the clock parameters. Description: Conﬁgures the various timing parameters for the CAN bus bit timing: Propagation segment, Phase Buffer 1 segment, Phase Buffer 2 segment, and the Synchronization Jump Width. The values for Propagation and Phase Buffer 1 segments are derived from the combination psClkParms- ui32SyncPropPhase1Seg parameter.
Page 58 Controller Area Network (CAN) 6.2.1.5 ROM_CANEnable Enables the CAN controller. Prototype: void ROM_CANEnable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_CANTABLE is an array of pointers located at ROM_APITABLE[18]. ROM_CANEnable is a function pointer located at ROM_CANTABLE[2]. Parameters: ui32Base is the base address of the CAN controller to enable.
Page 59 Controller Area Network (CAN) Returns: Returns true if the receive error count has reached the error passive limit, and false if the error count is below the error passive limit. 6.2.1.7 ROM_CANInit Initializes the CAN controller after reset. Prototype: void ROM_CANInit(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 60 Controller Area Network (CAN) CAN_INT_INTID_STATUS - Clears a status interrupt. 1-32 - Clears the speciﬁed message object interrupt It is not necessary to use this function to clear an interrupt. This should only be used if the application wants to clear an interrupt source without taking the normal interrupt action. Normally, the status interrupt is cleared by reading the controller status using ROM_CANStatusGet().
Page 61 Controller Area Network (CAN) Prototype: void ROM_CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_CANTABLE is an array of pointers located at ROM_APITABLE[18]. ROM_CANIntEnable is a function pointer located at ROM_CANTABLE[10]. Parameters: ui32Base is the base address of the CAN controller. ui32IntFlags is the bit mask of the interrupt sources to be enabled.
Page 62 Controller Area Network (CAN) Description: Returns the value of one of two interrupt status registers. The interrupt status register read is determined by the eIntStsReg parameter, which can have one of the following values: CAN_INT_STS_CAUSE - indicates the cause of the interrupt CAN_INT_STS_OBJECT - indicates pending interrupts of all message objects CAN_INT_STS_CAUSE returns the value of the controller interrupt register and indicates the cause of the interrupt.
Page 63 Controller Area Network (CAN) Prototype: void ROM_CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID, tCANMsgObject * pMsgObject, bool bClrPendingInt) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_CANTABLE is an array of pointers located at ROM_APITABLE[18]. ROM_CANMessageGet is a function pointer located at ROM_CANTABLE[7]. Parameters: ui32Base is the base address of the CAN controller.
Page 64 Controller Area Network (CAN) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_CANTABLE is an array of pointers located at ROM_APITABLE[18]. ROM_CANMessageSet is a function pointer located at ROM_CANTABLE[6]. Parameters: ui32Base is the base address of the CAN controller. ui32ObjID is the object number to conﬁgure (1-32).
Page 65 Controller Area Network (CAN) 6. Call this function with ui32ObjID set to one of the 32 object buffers. Example: To receive a speciﬁc data frame, take the following steps: 1. Set eMsgObjType to MSG_OBJ_TYPE_RX. 2. Set pMsgObject- ui32MsgID to the full message ID, or a partial mask to use partial ID matching.
Page 66 Controller Area Network (CAN) Prototype: void ROM_CANRetrySet(uint32_t ui32Base, bool bAutoRetry) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_CANTABLE is an array of pointers located at ROM_APITABLE[18]. ROM_CANRetrySet is a function pointer located at ROM_CANTABLE[14]. Parameters: ui32Base is the base address of the CAN controller. bAutoRetry enables automatic retransmission.
Page 67 Controller Area Network (CAN) CAN_STATUS_EWARN - an error counter has reached a limit of at least 96 CAN_STATUS_EPASS - CAN controller is in the error passive state CAN_STATUS_RXOK - a message was received successfully (independent of any mes- sage ﬁltering). CAN_STATUS_TXOK - a message was successfully transmitted CAN_STATUS_LEC_MSK - mask of last error code bits (3 bits) CAN_STATUS_LEC_NONE - no error...
Page 68 Controller Area Network (CAN) April 8, 2013...
Page 69: Crc
Introduction ....................69 Functions .
Page 70 7.2.1 Function Documentation 7.2.1.1 ROM_Crc16 Calculates the CRC-16 of an array of bytes. Prototype: uint16_t ROM_Crc16(uint16_t ui16Crc, const uint8_t * pui8Data, uint32_t ui32Count) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SOFTWARETABLE is an array of pointers located at ROM_APITABLE[21]. ROM_Crc16 is a function pointer located at ROM_SOFTWARETABLE[3].
Page 71 ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SOFTWARETABLE is an array of pointers located at ROM_APITABLE[21]. ROM_Crc16Array is a function pointer located at ROM_SOFTWARETABLE[1]. Parameters: ui32WordLen is the length of the array in words. pui32Data is a pointer to the array of words. Description: This function is used to calculate a standard CRC-16 cyclical redundancy check on the data passed to it.
Page 72 Prototype: uint8_t ROM_Crc8CCITT(uint8_t ui8Crc, const uint8_t * pui8Data, uint32_t ui32Count) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SOFTWARETABLE is an array of pointers located at ROM_APITABLE[21]. ROM_Crc8CCITT is a function pointer located at ROM_SOFTWARETABLE[4]. Parameters: ui8Crc is the starting CRC-8-CCITT value. pui8Data is a pointer to the data buffer.
Page 73: Flash
Flash Flash Introduction ....................73 Functions .
Page 74 Flash int32_t ROM_FlashUserGet (uint32_t pui32User0, uint32_t pui32User1) int32_t ROM_FlashUserSave (void) int32_t ROM_FlashUserSet (uint32_t ui32User0, uint32_t ui32User1) 8.2.1 Function Documentation 8.2.1.1 ROM_FlashErase Erases a block of ﬂash. Prototype: int32_t ROM_FlashErase(uint32_t ui32Address) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_FLASHTABLE is an array of pointers located at ROM_APITABLE[7].
Page 75 Flash Note: Because there is a write buffer in the Cortex-M4 processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared.
Page 76 Flash Description: Enables the indicated ﬂash controller interrupt sources. Only the sources that are enabled can be reﬂected to the processor interrupt; disabled sources have no effect on the processor. Returns: None. 8.2.1.5 ROM_FlashIntStatus Gets the current interrupt status. Prototype: uint32_t ROM_FlashIntStatus(bool bMasked) ROM Location:...
Page 77 Flash Description: This function will program a sequence of words into the on-chip ﬂash. Each word in a page of ﬂash can only be programmed one time between an erase of that page; programming a word multiple times will result in an unpredictable value in that word of ﬂash. Since the ﬂash is programmed one word at a time, the starting address and byte count must both be multiples of four.
Page 78 Flash Description: This function will make the currently programmed ﬂash protection settings permanent. This is a non-reversible operation; a chip reset or power cycle will not change the ﬂash protection. This function will not return until the protection has been saved. Returns: Returns 0 on success, or -1 if a hardware error is encountered.
Page 79 Flash ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_FLASHTABLE is an array of pointers located at ROM_APITABLE[7]. ROM_FlashUserGet is a function pointer located at ROM_FLASHTABLE[7]. Parameters: pui32User0 is a pointer to the location to store USER Register 0. pui32User1 is a pointer to the location to store USER Register 1.
Page 80 Flash Parameters: ui32User0 is the value to store in USER Register 0. ui32User1 is the value to store in USER Register 1. Description: This function will set the contents of the user registers (0 and 1) to the speciﬁed values. Returns: Returns 0 on success, or -1 if a hardware error is encountered.
Page 81: Floating-Point Unit (Fpu)
Floating-Point Unit (FPU) Floating-Point Unit (FPU) Introduction ....................81 API Functions .
Page 82: Api Functions
Floating-Point Unit (FPU) API Functions Functions void ROM_FPUDisable (void) void ROM_FPUEnable (void) void ROM_FPUFlushToZeroModeSet (uint32_t ui32Mode) void ROM_FPUHalfPrecisionModeSet (uint32_t ui32Mode) void ROM_FPULazyStackingEnable (void) void ROM_FPUNaNModeSet (uint32_t ui32Mode) void ROM_FPURoundingModeSet (uint32_t ui32Mode) void ROM_FPUStackingDisable (void) void ROM_FPUStackingEnable (void) 9.2.1 Function Documentation 9.2.1.1 ROM_FPUDisable Disables the ﬂoating-point unit.
Page 83 Floating-Point Unit (FPU) Description: This function enables the ﬂoating-point unit, allowing the ﬂoating-point instructions to be exe- cuted. This function must be called prior to performing any hardware ﬂoating-point operations; failure to do so results in a NOCP usage fault. Returns: None.
Page 84 Floating-Point Unit (FPU) Parameters: ui32Mode is the format for half-precision ﬂoating-point values; which is either FPU_HALF_IEEE or FPU_HALF_ALTERNATE. Description: This function selects between the IEEE half-precision ﬂoating-point representation and the Cortex-M processor alternative representation. The alternative representation has a larger range but does not have a way to encode inﬁnity (positive or negative) or NaN (quiet or signal- ing).
Page 85 Floating-Point Unit (FPU) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_FPUTABLE is an array of pointers located at ROM_APITABLE[26]. ROM_FPUNaNModeSet is a function pointer located at ROM_FPUTABLE[5]. Parameters: ui32Mode is the mode for NaN results; which is either FPU_NAN_PROPAGATE or FPU_NAN_DEFAULT.
Page 86 Floating-Point Unit (FPU) 9.2.1.8 ROM_FPUStackingDisable Disables the stacking of ﬂoating-point registers. Prototype: void ROM_FPUStackingDisable(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_FPUTABLE is an array of pointers located at ROM_APITABLE[26]. ROM_FPUStackingDisable is a function pointer located at ROM_FPUTABLE[7]. Description: This function disables the stacking of ﬂoating-point registers s0-s15 when an interrupt is han- dled.
Page 87: Gpio
GPIO GPIO Introduction ....................87 Functions .
Page 88 GPIO uint32_t ROM_GPIODirModeGet (uint32_t ui32Port, uint8_t ui8Pin) void ROM_GPIODirModeSet (uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32PinIO) void ROM_GPIODMATriggerDisable (uint32_t ui32Port, uint8_t ui8Pins) void ROM_GPIODMATriggerEnable (uint32_t ui32Port, uint8_t ui8Pins) uint32_t ROM_GPIOIntTypeGet (uint32_t ui32Port, uint8_t ui8Pin) void ROM_GPIOIntTypeSet (uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32IntType) void ROM_GPIOPadConﬁgGet (uint32_t ui32Port, uint8_t ui8Pin, uint32_t pui32Strength,...
Page 89 GPIO ui8Pins is the bit-packed representation of the pin(s). Description: This function disables a GPIO pin to be used as a trigger to start an ADC se- quence. This function can be used to disable this feature if it was enabled via a call to ROM_GPIOADCTriggerEnable().
Page 90 GPIO Parameters: ui32Port is the base address of the GPIO port. ui8Pin is the pin number. Description: This function gets the direction and control mode for a speciﬁed pin on the selected GPIO port. The pin can be conﬁgured as either an input or output under software control, or it can be under hardware control.
Page 91 GPIO Returns: None. 10.2.1.5 ROM_GPIODMATriggerDisable Disables a GPIO pin as a trigger to start a DMA transaction. Prototype: void ROM_GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIODMATriggerDisable is a function pointer located at ROM_GPIOTABLE[32].
Page 92 GPIO Returns: None. 10.2.1.7 ROM_GPIOIntTypeGet Gets the interrupt type for a pin. Prototype: uint32_t ROM_GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIOIntTypeGet is a function pointer located at ROM_GPIOTABLE[4]. Parameters: ui32Port is the base address of the GPIO port.
Page 93 GPIO Description: This function sets up the various interrupt trigger mechanisms for the speciﬁed pin(s) on the selected GPIO port. The parameter ui32IntType is an enumerated data type that can be one of the following values: GPIO_FALLING_EDGE GPIO_RISING_EDGE GPIO_BOTH_EDGES GPIO_LOW_LEVEL GPIO_HIGH_LEVEL where the different values describe the interrupt detection mechanism (edge or level) and the particular triggering event (falling, rising, or both edges for edge detect, low or high for level...
Page 94 GPIO however, the only meaningful data returned is whether the pin is terminated with a pull-up or down resistor. Returns: None 10.2.1.10 ROM_GPIOPadConﬁgSet Sets the pad conﬁguration for the speciﬁed pin(s). Prototype: void ROM_GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, uint32_t ui32Strength, uint32_t ui32PinType) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 95 GPIO where GPIO_PIN_TYPE_STD speciﬁes a push-pull pin, GPIO_PIN_TYPE_OD speciﬁes an open-drain pin, _WPU speciﬁes a weak pull-up, _WPD speciﬁes a weak pull-down, and GPIO_PIN_TYPE_ANALOG speciﬁes an analog input. The pin(s) are speciﬁed using a bit-packed byte, where each bit that is set identiﬁes the pin to be accessed, and where bit 0 of the byte represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
Page 96 GPIO Parameters: ui32Port is the base address of the GPIO port. ui8Pins is the bit-packed representation of the pin(s). Description: The values at the speciﬁed pin(s) are read, as speciﬁed by ui8Pins. Values are returned for both input and output pin(s), and the value for pin(s) that are not speciﬁed by ui8Pins are set to 0.
Page 97 GPIO 10.2.1.14 ROM_GPIOPinTypeCAN Conﬁgures pin(s) for use as a CAN device. Prototype: void ROM_GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIOPinTypeCAN is a function pointer located at ROM_GPIOTABLE[12]. Parameters: ui32Port is the base address of the GPIO port.
Page 98 GPIO Description: The analog comparator input pins must be properly conﬁgured for the analog comparator to function correctly. This function provides the proper conﬁguration for those pin(s). The pin(s) are speciﬁed using a bit-packed byte, where each bit that is set identiﬁes the pin to be accessed, and where bit 0 of the byte represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
Page 99 GPIO ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIOPinTypeGPIOOutput is a function pointer located at ROM_GPIOTABLE[15]. Parameters: ui32Port is the base address of the GPIO port. ui8Pins is the bit-packed representation of the pin(s). Description: The GPIO pins must be properly conﬁgured in order to function correctly as GPIO outputs.
Page 100 GPIO Prototype: void ROM_GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIOPinTypeI2C is a function pointer located at ROM_GPIOTABLE[16]. Parameters: ui32Port is the base address of the GPIO port. ui8Pins is the bit-packed representation of the pin(s).
Page 101 GPIO Note: This cannot be used to turn any pin into an I2C SCL pin; it only conﬁgures an I2C SCL pin for proper operation. Returns: None. 10.2.1.21 ROM_GPIOPinTypePWM Conﬁgures pin(s) for use by the PWM peripheral. Prototype: void ROM_GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 102 GPIO ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIOPinTypeQEI is a function pointer located at ROM_GPIOTABLE[18]. Parameters: ui32Port is the base address of the GPIO port. ui8Pins is the bit-packed representation of the pin(s). Description: The QEI pins must be properly conﬁgured for the QEI peripheral to function correctly.
Page 103 GPIO Note: This cannot be used to turn any pin into a SSI pin; it only conﬁgures a SSI pin for proper operation. Returns: None. 10.2.1.24 ROM_GPIOPinTypeTimer Conﬁgures pin(s) for use by the Timer peripheral. Prototype: void ROM_GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 104 GPIO ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIOPinTypeUART is a function pointer located at ROM_GPIOTABLE[21]. Parameters: ui32Port is the base address of the GPIO port. ui8Pins is the bit-packed representation of the pin(s). Description: The UART pins must be properly conﬁgured for the UART peripheral to function correctly.
Page 105 GPIO Note: This cannot be used to turn any pin into a USB pin; it only conﬁgures a USB pin for proper operation. Returns: None. 10.2.1.27 ROM_GPIOPinTypeUSBDigital Conﬁgures pin(s) for use by the USB peripheral. Prototype: void ROM_GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 106 GPIO ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4]. ROM_GPIOPinWrite is a function pointer located at ROM_GPIOTABLE[0]. Parameters: ui32Port is the base address of the GPIO port. ui8Pins is the bit-packed representation of the pin(s). ui8Val is the value to write to the pin(s).
Page 107: Hibernation Module
Hibernation Module Hibernation Module Introduction ................... . . 107 Functions .
Page 108: Functions
Hibernation Module interrupt status can be found by calling ROM_HibernateIntStatus(). In the interrupt handler, all pending interrupts must be cleared. Use the ROM_HibernateIntClear() function to clear pending interrupts. Finally, once the module is appropriately conﬁgured, the state saved, and the software applica- tion is ready to hibernate, call the ROM_HibernateRequest() function.
Page 109 Hibernation Module Prototype: uint32_t ROM_HibernateBatCheckDone(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19]. function pointer located ROM_HibernateBatCheckDone ROM_HIBERNATETABLE[30]. Description: This function returns if the forced battery check initiated by a call to the HibernateBatCheck- Start() function has completed.
Page 110 Hibernation Module 11.2.1.3 ROM_HibernateClockConﬁg Conﬁgures the clock input for the Hibernation module. Prototype: void ROM_HibernateClockConfig(uint32_t ui32Config) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19]. ROM_HibernateClockConfig is a function pointer located at ROM_HIBERNATETABLE[28]. Parameters: ui32Conﬁg is one of the possible conﬁguration options for the clock input listed below.
Page 111 Hibernation Module ui32Count is the count of 32-bit words to read. Description: Retrieves a set of data from the Hibernation module non-volatile memory that was previously stored with the ROM_HibernateDataSet() function. The caller must ensure that pui32Data points to a large enough memory block to hold all the data that is read from the non-volatile memory.
Page 112 Hibernation Module Description: Disables the Hibernation module for operation. After this function is called, none of the Hiber- nation module features are available. Returns: None. 11.2.1.7 ROM_HibernateEnableExpClk Enables the Hibernation module for operation. Prototype: void ROM_HibernateEnableExpClk(uint32_t ui32HibClk) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19].
Page 113 Hibernation Module Description: Clears the speciﬁed interrupt sources. This must be done from within the interrupt handler or else the handler is called again upon exit. The ui32IntFlags parameter has the same deﬁnition as the ui32IntFlags parameter to the ROM_HibernateIntEnable() function.
Page 114 Hibernation Module ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19]. ROM_HibernateIntEnable is a function pointer located at ROM_HIBERNATETABLE[21]. Parameters: ui32IntFlags is the bit mask of the interrupts to be enabled. Description: Enables the speciﬁed interrupt sources from the Hibernation module.
Page 115 Hibernation Module Prototype: uint32_t ROM_HibernateIsActive(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19]. ROM_HibernateIsActive is a function pointer located at ROM_HIBERNATETABLE[24]. Description: This function queries the control register to determine if the module is already active. This function can be called at a power-on reset to help determine if the reset is due to a wake from hibernation or a cold start.
Page 116 Hibernation Module Prototype: void ROM_HibernateLowBatSet(uint32_t ui32LowBatFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19]. ROM_HibernateLowBatSet is a function pointer located at ROM_HIBERNATETABLE[8]. Parameters: ui32LowBatFlags speciﬁes behavior of low battery detection. Description: Enables the low battery detection and whether hibernation is allowed if a low battery is de- tected.
Page 117 Hibernation Module to execute instructions for some time and the caller should be prepared for this function to return. There are various reasons why the power may not be removed. For example, if the ROM_HibernateLowBatSet() function was used to conﬁgure an abort if low battery is detected, then the power will not be removed if the battery voltage is too low.
Page 118 Hibernation Module 11.2.1.18 ROM_HibernateRTCGet Gets the value of the real time clock (RTC) counter. Prototype: uint32_t ROM_HibernateRTCGet(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19]. ROM_HibernateRTCGet is a function pointer located at ROM_HIBERNATETABLE[11]. Description: Gets the value of the RTC and returns it to the caller.
Page 119 Hibernation Module ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_HIBERNATETABLE is an array of pointers located at ROM_APITABLE[19]. ROM_HibernateRTCSSGet is a function pointer located at ROM_HIBERNATETABLE[27]. Description: This function will return the current value of the sub second count for the for the RTC in 1/32768 of a second increments.
Page 120 Hibernation Module trim register is applied to the predivider to allow ﬁne-tuning of the RTC rate, in order to make corrections to the rate. The software application can make adjustments to the predivider trim register to account for variations in the accuracy of the input time source. The nominal value is 0x7FFF, and it can be adjusted up or down in order to ﬁne-tune the RTC rate.
Page 121 Hibernation Module HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted. HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs. Returns: None. April 8, 2013...
Page 122 Hibernation Module April 8, 2013...
Page 123: Inter-Integrated Circuit (I2C)
Inter-Integrated Circuit (I2C) Inter-Integrated Circuit (I2C) Introduction ................... . . 123 Functions .
Page 124: Functions
Inter-Integrated Circuit (I2C) using ROM_I2CMasterErr(). If there are no errors, then the data has been sent or is ready to be read using ROM_I2CMasterDataGet(). For the burst send and receive cases, the polling method also involves calling the ROM_I2CMasterControl() function for each byte transmitted or received (using either the I2C_MASTER_CMD_BURST_SEND_CONT I2C_MASTER_CMD_BURST_RECEIVE_CONT commands),...
Page 125 Inter-Integrated Circuit (I2C) Prototype: bool ROM_I2CMasterBusBusy(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterBusBusy is a function pointer located at ROM_I2CTABLE[17]. Parameters: ui32Base is the base address of the I2C Master module. Description: This function returns an indication of whether or not the I2C bus is busy.
Page 126 Inter-Integrated Circuit (I2C) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterControl is a function pointer located at ROM_I2CTABLE[18]. Parameters: ui32Base is the base address of the I2C Master module. ui32Cmd command to be issued to the I2C Master module Description: This function is used to control the state of the Master module send and receive operations.
Page 127 Inter-Integrated Circuit (I2C) 12.2.1.5 ROM_I2CMasterDataPut Transmits a byte from the I2C Master. Prototype: void ROM_I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterDataPut is a function pointer located at ROM_I2CTABLE[0]. Parameters: ui32Base is the base address of the I2C Master module.
Page 128 Inter-Integrated Circuit (I2C) Prototype: void ROM_I2CMasterEnable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterEnable is a function pointer located at ROM_I2CTABLE[3]. Parameters: ui32Base is the base address of the I2C Master module. Description: This will enable operation of the I2C Master block.
Page 129 Inter-Integrated Circuit (I2C) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterInitExpClk is a function pointer located at ROM_I2CTABLE[1]. Parameters: ui32Base is the base address of the I2C Master module. ui32I2CClk is the rate of the clock supplied to the I2C module.
Page 130 Inter-Integrated Circuit (I2C) 12.2.1.11 ROM_I2CMasterIntClearEx Clears I2C Master interrupt sources. Prototype: void ROM_I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterIntClearEx is a function pointer located at ROM_I2CTABLE[32]. Parameters: ui32Base is the base address of the I2C Master module.
Page 131 Inter-Integrated Circuit (I2C) Returns: None. 12.2.1.13 ROM_I2CMasterIntDisableEx Disables individual I2C Master interrupt sources. Prototype: void ROM_I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterIntDisableEx is a function pointer located at ROM_I2CTABLE[30]. Parameters: ui32Base is the base address of the I2C Master module.
Page 132 Inter-Integrated Circuit (I2C) 12.2.1.15 ROM_I2CMasterIntEnableEx Enables individual I2C Master interrupt sources. Prototype: void ROM_I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterIntEnableEx is a function pointer located at ROM_I2CTABLE[29]. Parameters: ui32Base is the base address of the I2C Master module.
Page 133 Inter-Integrated Circuit (I2C) Returns: The current interrupt status, returned as true if active or false if not active. 12.2.1.17 ROM_I2CMasterIntStatusEx Gets the current I2C Master interrupt status. Prototype: uint32_t ROM_I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3].
Page 134 Inter-Integrated Circuit (I2C) 12.2.1.19 ROM_I2CMasterSlaveAddrSet Sets the address that the I2C Master will place on the bus. Prototype: void ROM_I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, bool bReceive) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_I2CMasterSlaveAddrSet is a function pointer located at ROM_I2CTABLE[15].
Page 135 Inter-Integrated Circuit (I2C) Returns: None. 12.2.1.21 ROM_UpdateI2C Starts an update over the I2C0 interface. Prototype: void ROM_UpdateI2C(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_I2CTABLE is an array of pointers located at ROM_APITABLE[3]. ROM_UpdateI2C is a function pointer located at ROM_I2CTABLE[24]. Description: Calling this function commences an update of the ﬁrmware via the I2C0 interface.
Page 136 Inter-Integrated Circuit (I2C) April 8, 2013...
Page 137: Interrupt Controller (Nvic)
Interrupt Controller (NVIC) Interrupt Controller (NVIC) Introduction ................... . . 137 Functions .
Page 138 Interrupt Controller (NVIC) void ROM_IntPendSet (uint32_t ui32Interrupt) int32_t ROM_IntPriorityGet (uint32_t ui32Interrupt) uint32_t ROM_IntPriorityGroupingGet (void) void ROM_IntPriorityGroupingSet (uint32_t ui32Bits) uint32_t ROM_IntPriorityMaskGet (void) void ROM_IntPriorityMaskSet (uint32_t ui32PriorityMask) void ROM_IntPrioritySet (uint32_t ui32Interrupt, uint8_t ui8Priority) 13.2.1 Function Documentation 13.2.1.1 ROM_IntDisable Disables an interrupt. Prototype: void ROM_IntDisable(uint32_t ui32Interrupt) ROM Location:...
Page 139 Interrupt Controller (NVIC) Description: The speciﬁed interrupt is enabled in the interrupt controller. Other enables for the interrupt (such as at the peripheral level) are unaffected by this function. Returns: None. 13.2.1.3 ROM_IntIsEnabled Returns if a peripheral interrupt is enabled. Prototype: uint32_t ROM_IntIsEnabled(uint32_t ui32Interrupt)
Page 140 Interrupt Controller (NVIC) 13.2.1.5 ROM_IntMasterEnable Enables the processor interrupt. Prototype: bool ROM_IntMasterEnable(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_INTERRUPTTABLE is an array of pointers located at ROM_APITABLE[14]. ROM_IntMasterEnable is a function pointer located at ROM_INTERRUPTTABLE[1]. Description: Allows the processor to respond to interrupts.
Page 141 Interrupt Controller (NVIC) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_INTERRUPTTABLE is an array of pointers located at ROM_APITABLE[14]. ROM_IntPendSet is a function pointer located at ROM_INTERRUPTTABLE[8]. Parameters: ui32Interrupt speciﬁes the interrupt to be pended. Description: The speciﬁed interrupt is pended in the interrupt controller.
Page 142 Interrupt Controller (NVIC) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_INTERRUPTTABLE is an array of pointers located at ROM_APITABLE[14]. function pointer located ROM_IntPriorityGroupingGet ROM_INTERRUPTTABLE[5]. Description: This function returns the split between preemptable priority levels and subpriority levels in the interrupt priority speciﬁcation.
Page 143 Interrupt Controller (NVIC) Description: This function gets the current setting of the interrupt priority masking level. The value returned is the priority level such that all interrupts of that and lesser priority are masked. A value of 0 means that priority masking is disabled. Smaller numbers correspond to higher interrupt priorities.
Page 144 Interrupt Controller (NVIC) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_INTERRUPTTABLE is an array of pointers located at ROM_APITABLE[14]. ROM_IntPrioritySet is a function pointer located at ROM_INTERRUPTTABLE[6]. Parameters: ui32Interrupt speciﬁes the interrupt in question. ui8Priority speciﬁes the priority of the interrupt. Description: This function is used to set the priority of an interrupt.
Page 145: Memory Protection Unit (Mpu)
Memory Protection Unit (MPU) Memory Protection Unit (MPU) Introduction ................... . . 145 Functions .
Page 146: Functions
Memory Protection Unit (MPU) enabled, a default memory map is applied. If this feature is not enabled, then a memory manage- ment fault is generated if the MPU is enabled and no regions are conﬁgured and enabled. The MPU can also be set to use a default memory map when in the Hard Fault or NMI handlers, instead of using the conﬁgured regions.
Page 147 Memory Protection Unit (MPU) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_MPUTABLE is an array of pointers located at ROM_APITABLE[20]. ROM_MPUEnable is a function pointer located at ROM_MPUTABLE[0]. Parameters: ui32MPUConﬁg is the logical OR of the possible conﬁgurations. Description: This function enables the Cortex-M4 memory protection unit.
Page 148 Memory Protection Unit (MPU) 14.2.1.4 ROM_MPURegionDisable Disables a speciﬁc region. Prototype: void ROM_MPURegionDisable(uint32_t ui32Region) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_MPUTABLE is an array of pointers located at ROM_APITABLE[20]. ROM_MPURegionDisable is a function pointer located at ROM_MPUTABLE[4]. Parameters: ui32Region is the region number to disable.
Page 149 Memory Protection Unit (MPU) Prototype: void ROM_MPURegionGet(uint32_t ui32Region, uint32_t * pui32Addr, uint32_t * pui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_MPUTABLE is an array of pointers located at ROM_APITABLE[20]. ROM_MPURegionGet is a function pointer located at ROM_MPUTABLE[6]. Parameters: ui32Region is the region number to get.
Page 150 Memory Protection Unit (MPU) The ui32Flags parameter is the logical OR of all of the attributes of the region. It is a com- bination of choices for region size, execute permission, read/write permissions, disabled sub- regions, and a ﬂag to determine if the region is enabled. The size ﬂag determines the size of a region, and must be one of the following: MPU_RGN_SIZE_32B MPU_RGN_SIZE_64B...
Page 151 Memory Protection Unit (MPU) The region is automatically divided into 8 equally-sized sub-regions by the MPU. Sub-regions can only be used in regions of size 256 bytes or larger. Any of these 8 sub-regions can be disabled. This allows for creation of “holes” in a region which can be left open, or overlaid by another region with different attributes.
Page 152 Memory Protection Unit (MPU) April 8, 2013...
Page 153: Pulse Width Modulator (Pwm)
Pulse Width Modulator (PWM) Pulse Width Modulator (PWM) Introduction ................... . . 153 Functions .
Page 154 Pulse Width Modulator (PWM) void ROM_PWMDeadBandEnable (uint32_t ui32Base, uint32_t ui32Gen, uint16_t ui16Rise, uint16_t ui16Fall) void ROM_PWMFaultIntClear (uint32_t ui32Base) void ROM_PWMFaultIntClearExt (uint32_t ui32Base, uint32_t ui32FaultInts) void ROM_PWMGenConﬁgure (uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Conﬁg) void ROM_PWMGenDisable (uint32_t ui32Base, uint32_t ui32Gen) void ROM_PWMGenEnable (uint32_t ui32Base, uint32_t ui32Gen) void ROM_PWMGenFaultClear...
Page 155 Pulse Width Modulator (PWM) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMDeadBandDisable is a function pointer located at ROM_PWMTABLE[8]. Parameters: ui32Base is the base address of the PWM module. ui32Gen is the PWM generator to modify.
Page 156 Pulse Width Modulator (PWM) 15.2.1.3 ROM_PWMFaultIntClear Clears the fault interrupt for a PWM module. Prototype: void ROM_PWMFaultIntClear(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMFaultIntClear is a function pointer located at ROM_PWMTABLE[20]. Parameters: ui32Base is the base address of the PWM module.
Page 157 Pulse Width Modulator (PWM) Description: Clears one or more fault interrupts by writing to the appropriate bit of the PWM interrupt status register. The parameter ui32FaultInts must be the logical OR of any of PWM_INT_FAULT0, PWM_INT_FAULT1, PWM_INT_FAULT2, or PWM_INT_FAULT3. When running on a device supporting extended PWM fault handling, the fault interrupts are derived by performing a logical OR of each of the conﬁgured fault trigger signals for a given generator.
Page 158 Pulse Width Modulator (PWM) up from zero to the preset value, count back down to zero, and then repeat the process. This will produce center-aligned PWM signals (that is, the middle of the high/low period of the PWM signals produced by the generator will occur at the same time). When the PWM generator parameters (period and pulse width) are modiﬁed, their affect on the output PWM signals can be delayed.
Page 159 Pulse Width Modulator (PWM) 15.2.1.6 ROM_PWMGenDisable Disables the timer/counter for a PWM generator block. Prototype: void ROM_PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMGenDisable is a function pointer located at ROM_PWMTABLE[5].
Page 160 Pulse Width Modulator (PWM) 15.2.1.8 ROM_PWMGenFaultClear Clears one or more latched fault triggers for a given PWM generator. Prototype: void ROM_PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Group, uint32_t ui32FaultTriggers) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMGenFaultClear is a function pointer located at ROM_PWMTABLE[28].
Page 161 Pulse Width Modulator (PWM) Parameters: ui32Base is the base address of the PWM module. ui32Gen is the PWM generator whose fault conﬁguration is being set. Must be one of PWM_GEN_0, PWM_GEN_1, PWM_GEN_2, or PWM_GEN_3. ui32MinFaultPeriod is the minimum fault active period expressed in PWM clock cycles. ui32FaultSenses indicates which sense of each FAULT input should be considered the “as- serted”...
Page 162 Pulse Width Modulator (PWM) If latched faults are conﬁgured, the application must call ROM_PWMGenFaultClear() to clear each trigger. Note: This function is only available on devices supporting extended PWM fault handling. Returns: Returns the current state of the fault triggers for the given PWM generator. A set bit indicates that the associated trigger is active.
Page 163 Pulse Width Modulator (PWM) 15.2.1.12 ROM_PWMGenFaultTriggerSet Conﬁgures the set of fault triggers for a given PWM generator. Prototype: void ROM_PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Group, uint32_t ui32FaultTriggers) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMGenFaultTriggerSet is a function pointer located at ROM_PWMTABLE[25].
Page 164 Pulse Width Modulator (PWM) Prototype: void ROM_PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Ints) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMGenIntClear is a function pointer located at ROM_PWMTABLE[17]. Parameters: ui32Base is the base address of the PWM module.
Page 165 Pulse Width Modulator (PWM) bMasked speciﬁes whether masked or raw interrupt status is returned. Description: If bMasked is set as true, then the masked interrupt status is returned; otherwise, the raw interrupt status is returned. Returns: Returns the contents of the interrupt status register, or the contents of the raw interrupt status register, for the speciﬁed PWM generator.
Page 166 Pulse Width Modulator (PWM) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMGenIntTrigEnable is a function pointer located at ROM_PWMTABLE[14]. Parameters: ui32Base is the base address of the PWM module. ui32Gen is the PWM generator to have interrupts and triggers enabled.
Page 167 Pulse Width Modulator (PWM) 15.2.1.18 ROM_PWMGenPeriodSet Set the period of a PWM generator. Prototype: void ROM_PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, uint32_t ui32Period) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMGenPeriodSet is a function pointer located at ROM_PWMTABLE[2].
Page 168 Pulse Width Modulator (PWM) Description: Masks the speciﬁed interrupt(s) by clearing the speciﬁed bits of the interrupt enable register for the selected PWM module. Returns: None. 15.2.1.20 ROM_PWMIntEnable Enables generator and fault interrupts for a PWM module. Prototype: void ROM_PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 169 Pulse Width Modulator (PWM) Description: If bMasked is set as true, then the masked interrupt status is returned; otherwise, the raw interrupt status is returned. Returns: The current interrupt status, enumerated as a bit ﬁeld of PWM_INT_GEN_0, PWM_INT_GEN_1, PWM_INT_GEN_2, PWM_INT_GEN_3, PWM_INT_FAULT0, PWM_INT_FAULT1, PWM_INT_FAULT2, and PWM_INT_FAULT3.
Page 170 Pulse Width Modulator (PWM) Prototype: void ROM_PWMOutputFaultLevel(uint32_t ui32Base, uint32_t ui32PWMOutBits, bool bDriveHigh) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMOutputFaultLevel is a function pointer located at ROM_PWMTABLE[22]. Parameters: ui32Base is the base address of the PWM module.
Page 171 Pulse Width Modulator (PWM) ui32PWMOutBits are the PWM outputs to be modiﬁed. Must be the logical OR of any of PWM_OUT_0_BIT, PWM_OUT_1_BIT, PWM_OUT_2_BIT, PWM_OUT_3_BIT, PWM_OUT_4_BIT, PWM_OUT_5_BIT, PWM_OUT_6_BIT, or PWM_OUT_7_BIT. bInvert determines if the signal is inverted or passed through. Description: This function is used to select the inversion mode for the selected PWM outputs.
Page 172 Pulse Width Modulator (PWM) Prototype: uint32_t ROM_PWMPulseWidthGet(uint32_t ui32Base, uint32_t ui32PWMOut) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMPulseWidthGet is a function pointer located at ROM_PWMTABLE[6]. Parameters: ui32Base is the base address of the PWM module. ui32PWMOut is the PWM output to query.
Page 173 Pulse Width Modulator (PWM) Returns: None. 15.2.1.28 ROM_PWMSyncTimeBase Synchronizes the counters in one or multiple PWM generator blocks. Prototype: void ROM_PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_PWMTABLE is an array of pointers located at ROM_APITABLE[8]. ROM_PWMSyncTimeBase is a function pointer located at ROM_PWMTABLE[10].
Page 174 Pulse Width Modulator (PWM) Returns: None. April 8, 2013...
Page 175: Quadrature Encoder (Qei)
Quadrature Encoder (QEI) Quadrature Encoder (QEI) Introduction ................... . . 175 Functions .
Page 176 Quadrature Encoder (QEI) bool ROM_QEIErrorGet (uint32_t ui32Base) void ROM_QEIIntClear (uint32_t ui32Base, uint32_t ui32IntFlags) void ROM_QEIIntDisable (uint32_t ui32Base, uint32_t ui32IntFlags) void ROM_QEIIntEnable (uint32_t ui32Base, uint32_t ui32IntFlags) uint32_t ROM_QEIIntStatus (uint32_t ui32Base, bool bMasked) uint32_t ROM_QEIPositionGet (uint32_t ui32Base) void ROM_QEIPositionSet (uint32_t ui32Base, uint32_t ui32Position) void ROM_QEIVelocityConﬁgure (uint32_t ui32Base,...
Page 177 Quadrature Encoder (QEI) ui32MaxPosition is the maximum value of the position integrator, and is the value used to reset the position capture when in index reset mode and moving in the reverse (negative) direction. Returns: None. 16.2.1.2 ROM_QEIDirectionGet Gets the current direction of rotation. Prototype: int32_t ROM_QEIDirectionGet(uint32_t ui32Base)
Page 178 Quadrature Encoder (QEI) 16.2.1.4 ROM_QEIEnable Enables the quadrature encoder. Prototype: void ROM_QEIEnable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_QEITABLE is an array of pointers located at ROM_APITABLE[9]. ROM_QEIEnable is a function pointer located at ROM_QEITABLE[1]. Parameters: ui32Base is the base address of the quadrature encoder module.
Page 179 Quadrature Encoder (QEI) 16.2.1.6 ROM_QEIIntClear Clears quadrature encoder interrupt sources. Prototype: void ROM_QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_QEITABLE is an array of pointers located at ROM_APITABLE[9]. ROM_QEIIntClear is a function pointer located at ROM_QEITABLE[14]. Parameters: ui32Base is the base address of the quadrature encoder module.
Page 180 Quadrature Encoder (QEI) Description: Disables the indicated quadrature encoder interrupt sources. Only the sources that are enabled can be reﬂected to the processor interrupt; disabled sources have no effect on the processor. Returns: None. 16.2.1.8 ROM_QEIIntEnable Enables individual quadrature encoder interrupt sources. Prototype: void ROM_QEIIntEnable(uint32_t ui32Base,...
Page 181 Quadrature Encoder (QEI) Description: This returns the interrupt status for the quadrature encoder module. Either the raw interrupt status or the status of interrupts that are allowed to reﬂect to the processor can be returned. Returns: Returns the current interrupt status, enumerated as a bit ﬁeld of QEI_INTERROR, QEI_INTDIR, QEI_INTTIMER, and QEI_INTINDEX.
Page 182 Quadrature Encoder (QEI) Description: This sets the current position of the encoder; the encoder position will then be measured relative to this value. Returns: None. 16.2.1.12 ROM_QEIVelocityConﬁgure Conﬁgures the velocity capture. Prototype: void ROM_QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, uint32_t ui32Period) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 183 Quadrature Encoder (QEI) Parameters: ui32Base is the base address of the quadrature encoder module. Description: This will disable operation of the velocity capture in the quadrature encoder module. Returns: None. 16.2.1.14 ROM_QEIVelocityEnable Enables the velocity capture. Prototype: void ROM_QEIVelocityEnable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 184 Quadrature Encoder (QEI) Description: This returns the current speed of the encoder. The value returned is the number of pulses detected in the speciﬁed time period; this number can be multiplied by the number of time periods per second and divided by the number of pulses per revolution to obtain the number of revolutions per second.
Page 185: Synchronous Serial Interface (Ssi)
Motorola® SPI™, National Semiconductor® Microwire, or the Texas Instruments® synchronous serial interface frame formats. The size of the data frame is also conﬁgurable, and can be set to be between 4 and 16 bits, inclusive.
Page 186 Synchronous Serial Interface (SSI) void ROM_SSIIntEnable (uint32_t ui32Base, uint32_t ui32IntFlags) uint32_t ROM_SSIIntStatus (uint32_t ui32Base, bool bMasked) void ROM_UpdateSSI (void) 17.2.1 Function Documentation 17.2.1.1 ROM_SSIBusy Determines whether the SSI transmitter is busy or not. Prototype: bool ROM_SSIBusy(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SSITABLE is an array of pointers located at ROM_APITABLE[2].
Page 187 Synchronous Serial Interface (SSI) Returns: None. 17.2.1.3 ROM_SSIClockSourceSet Sets the data clock source for the speciﬁed SSI peripheral. Prototype: void ROM_SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SSITABLE is an array of pointers located at ROM_APITABLE[2]. ROM_SSIClockSourceSet is a function pointer located at ROM_SSITABLE[16].
Page 188 Synchronous Serial Interface (SSI) ui32SSIClk is the rate of the clock supplied to the SSI module. ui32Protocol speciﬁes the data transfer protocol. ui32Mode speciﬁes the mode of operation. ui32BitRate speciﬁes the clock rate. ui32DataWidth speciﬁes number of bits transferred per frame. Description: This function conﬁgures the synchronous serial interface.
Page 189 Synchronous Serial Interface (SSI) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SSITABLE is an array of pointers located at ROM_APITABLE[2]. ROM_SSIDataGet is a function pointer located at ROM_SSITABLE[9]. Parameters: ui32Base speciﬁes the SSI module base address. pui32Data is a pointer to a storage location for data that was received over the SSI interface.
Page 190 Synchronous Serial Interface (SSI) 17.2.1.7 ROM_SSIDataPut Puts a data element into the SSI transmit FIFO. Prototype: void ROM_SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SSITABLE is an array of pointers located at ROM_APITABLE[2]. ROM_SSIDataPut is a function pointer located at ROM_SSITABLE[0].
Page 191 Synchronous Serial Interface (SSI) Note: The upper 32 - N bits of the ui32Data are discarded by the hardware, where N is the data width as conﬁgured by ROM_SSIConﬁgSetExpClk(). For example, if the interface is conﬁgured for 8-bit data width, the upper 24 bits of ui32Data are discarded. Returns: Returns the number of elements written to the SSI transmit FIFO.
Page 192 Synchronous Serial Interface (SSI) SSI_DMA_RX - disable DMA for receive SSI_DMA_TX - disable DMA for transmit Returns: None. 17.2.1.11 ROM_SSIDMAEnable Enable SSI DMA operation. Prototype: void ROM_SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SSITABLE is an array of pointers located at ROM_APITABLE[2].
Page 193 Synchronous Serial Interface (SSI) Parameters: ui32Base speciﬁes the SSI module base address. Description: This function enables operation of the synchronous serial interface. The synchronous serial interface must be conﬁgured before it is enabled. Returns: None. 17.2.1.13 ROM_SSIIntClear Clears SSI interrupt sources. Prototype: void ROM_SSIIntClear(uint32_t ui32Base,...
Page 194 Synchronous Serial Interface (SSI) Prototype: void ROM_SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SSITABLE is an array of pointers located at ROM_APITABLE[2]. ROM_SSIIntDisable is a function pointer located at ROM_SSITABLE[5]. Parameters: ui32Base speciﬁes the SSI module base address. ui32IntFlags is a bit mask of the interrupt sources to be disabled.
Page 195 Synchronous Serial Interface (SSI) Prototype: uint32_t ROM_SSIIntStatus(uint32_t ui32Base, bool bMasked) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SSITABLE is an array of pointers located at ROM_APITABLE[2]. ROM_SSIIntStatus is a function pointer located at ROM_SSITABLE[6]. Parameters: ui32Base speciﬁes the SSI module base address. bMasked is false if the raw interrupt status is required or true if the masked interrupt status is required.
Page 196 Synchronous Serial Interface (SSI) April 8, 2013...
Page 197: System Control
System Control System Control Introduction ................... . . 197 Functions .
Page 198: Functions
System Control 18.2 Functions Functions uint32_t ROM_SysCtlADCSpeedGet (void) void ROM_SysCtlADCSpeedSet (uint32_t ui32Speed) uint32_t ROM_SysCtlClockGet (void) void ROM_SysCtlClockSet (uint32_t ui32Conﬁg) void ROM_SysCtlDeepSleep (void) void ROM_SysCtlDeepSleepClockSet (uint32_t ui32Conﬁg) void ROM_SysCtlDelay (uint32_t ui32Count) uint32_t ROM_SysCtlFlashSizeGet (void) void ROM_SysCtlIntClear (uint32_t ui32Ints) void ROM_SysCtlIntDisable (uint32_t ui32Ints) void ROM_SysCtlIntEnable (uint32_t ui32Ints)
Page 199 System Control Prototype: uint32_t ROM_SysCtlADCSpeedGet(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlADCSpeedGet is a function pointer located at ROM_SYSCTLTABLE[28]. Description: This function gets the current sample rate of the ADC. Returns: Returns the current ADC sample rate;...
Page 200 System Control ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlClockGet is a function pointer located at ROM_SYSCTLTABLE[24]. Description: This function determines the clock rate of the processor clock. This is also the clock rate of all the peripheral modules (with the exception of PWM, which has its own clock divider).
Page 201 System Control SYSCTL_XTAL_16MHZ, SYSCTL_XTAL_16_3MHZ. Values below SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. The oscillator source is chosen with one of the following values: SYSCTL_OSC_MAIN, SYSCTL_OSC_INT, SYSCTL_OSC_INT4, SYSCTL_OSC_EXT32, or SYSCTL_OSC_INT30. SYSCTL_OSC_EXT32 is only available when the hibernate module has been enabled. The internal and main oscillators are disabled with the SYSCTL_INT_OSC_DIS and SYSCTL_MAIN_OSC_DIS ﬂags, respectively.
Page 202 System Control 18.2.1.6 ROM_SysCtlDeepSleepClockSet Sets the clocking of the device while in deep-sleep mode. Prototype: void ROM_SysCtlDeepSleepClockSet(uint32_t ui32Config) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlDeepSleepClockSet is a function pointer located at ROM_SYSCTLTABLE[46]. Parameters: ui32Conﬁg is the required conﬁguration of the device clocking while in deep-sleep mode.
Page 203 System Control Description: This function provides a means of generating a constant length delay. It is written in assembly to keep the delay consistent across tool chains, avoiding the need to tune the delay based on the tool chain in use. The loop takes 3 cycles/loop.
Page 204 System Control Note: Because there is a write buffer in the Cortex-M4 processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared.
Page 205 System Control Parameters: ui32Ints is a bit mask of the interrupt sources to be enabled. Must be a logical OR of SYSCTL_INT_PLL_LOCK, SYSCTL_INT_CUR_LIMIT, SYSCTL_INT_IOSC_FAIL, SYSCTL_INT_MOSC_FAIL, SYSCTL_INT_POR, SYSCTL_INT_BOR, and/or SYSCTL_INT_PLL_FAIL. Description: Enables the indicated system control interrupt sources. Only the sources that are enabled can be reﬂected to the processor interrupt;...
Page 206 System Control Parameters: ui32Conﬁg is the required conﬁguration of the MOSC control. Description: This function conﬁgures the control of the main oscillator. The ui32Conﬁg is speciﬁed as follows: SYSCTL_MOSC_VALIDATE enables the MOSC veriﬁcation circuit that detects a failure of the main oscillator (such as a loss of the clock). SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an interrupt instead of resetting the processor.
Page 207 System Control ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. function pointer located ROM_SysCtlPeripheralDeepSleepDisable ROM_SYSCTLTABLE[11]. Parameters: ui32Peripheral is the peripheral to disable in deep-sleep mode. Description: This function causes a peripheral to stop operating when the processor goes into deep-sleep mode.
Page 208 System Control ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. function pointer located ROM_SysCtlPeripheralDeepSleepEnable ROM_SYSCTLTABLE[10]. Parameters: ui32Peripheral is the peripheral to enable in deep-sleep mode. Description: This function allows a peripheral to continue operating when the processor goes into deep- sleep mode.
Page 209 System Control ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlPeripheralDisable is a function pointer located at ROM_SYSCTLTABLE[7]. Parameters: ui32Peripheral is the peripheral to disable. Description: Peripherals are disabled with this function. Once disabled, they will not operate or respond to register reads/writes.
Page 210 System Control Description: Peripherals are enabled with this function. At power-up, all peripherals are disabled; they must be enabled in order to operate or respond to register reads/writes. ui32Peripheral parameter must only follow- values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CAN2, SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_COMP1, SYSCTL_PERIPH_COMP2, SYSCTL_PERIPH_EEPROM0,...
Page 211 System Control ui32Peripheral paramter must only follow- values: SYSCTL_PERIPH_ADC0, SYSCTL_PERIPH_ADC1, SYSCTL_PERIPH_CAN0, SYSCTL_PERIPH_CAN1, SYSCTL_PERIPH_CAN2, SYSCTL_PERIPH_COMP0, SYSCTL_PERIPH_COMP1, SYSCTL_PERIPH_COMP2, SYSCTL_PERIPH_EEPROM0, SYSCTL_PERIPH_GPIOA, SYSCTL_PERIPH_GPIOB, SYSCTL_PERIPH_GPIOC, SYSCTL_PERIPH_GPIOD, SYSCTL_PERIPH_GPIOE, SYSCTL_PERIPH_GPIOF, SYSCTL_PERIPH_HIBERNATE, SYSCTL_PERIPH_I2C0, SYSCTL_PERIPH_I2C1, SYSCTL_PERIPH_I2C2, SYSCTL_PERIPH_I2C3, SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4,...
Page 212 System Control SYSCTL_PERIPH_I2C4, SYSCTL_PERIPH_I2C5, SYSCTL_PERIPH_PWM0, SYSCTL_PERIPH_PWM1, SYSCTL_PERIPH_QEI0, SYSCTL_PERIPH_QEI1, SYSCTL_PERIPH_SSI0, SYSCTL_PERIPH_SSI1, SYSCTL_PERIPH_SSI2, SYSCTL_PERIPH_SSI3, SYSCTL_PERIPH_TIMER0, SYSCTL_PERIPH_TIMER1, SYSCTL_PERIPH_TIMER2, SYSCTL_PERIPH_TIMER3, SYSCTL_PERIPH_TIMER4, SYSCTL_PERIPH_TIMER5, SYSCTL_PERIPH_UART0, SYSCTL_PERIPH_UART1, SYSCTL_PERIPH_UART2, SYSCTL_PERIPH_UART3, SYSCTL_PERIPH_UART4, SYSCTL_PERIPH_UART5, SYSCTL_PERIPH_UART6, SYSCTL_PERIPH_UART7, SYSCTL_PERIPH_UDMA, SYSCTL_PERIPH_USB0, SYSCTL_PERIPH_WDOG0, SYSCTL_PERIPH_WDOG1, SYSCTL_PERIPH_WTIMER0, SYSCTL_PERIPH_WTIMER1, SYSCTL_PERIPH_WTIMER2, SYSCTL_PERIPH_WTIMER3, SYSCTL_PERIPH_WTIMER4, or SYSCTL_PERIPH_WTIMER5. Returns: None. 18.2.1.21 ROM_SysCtlPeripheralPresent Determines if a peripheral is present.
Page 213 System Control Returns: Returns true if the speciﬁed peripheral is present and false if it is not. 18.2.1.22 ROM_SysCtlPeripheralReady Determines if a peripheral is ready. Prototype: bool ROM_SysCtlPeripheralReady(uint32_t ui32Peripheral) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13].
Page 214 System Control Prototype: void ROM_SysCtlPeripheralReset(uint32_t ui32Peripheral) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlPeripheralReset is a function pointer located at ROM_SYSCTLTABLE[5]. Parameters: ui32Peripheral is the peripheral to reset. Description: This function performs a software reset of the speciﬁed peripheral.
Page 215 System Control function pointer located ROM_SysCtlPeripheralSleepDisable ROM_SYSCTLTABLE[9]. Parameters: ui32Peripheral is the peripheral to disable in sleep mode. Description: This function causes a peripheral to stop operating when the processor goes into sleep mode. Disabling peripherals while in sleep mode helps to lower the current draw of the device. If en- abled (via ROM_SysCtlPeripheralEnable()), the peripheral will automatically resume operation when the processor leaves sleep mode, maintaining its entire state from before sleep mode was entered.
Page 216 System Control function pointer located ROM_SysCtlPeripheralSleepEnable ROM_SYSCTLTABLE[8]. Parameters: ui32Peripheral is the peripheral to enable in sleep mode. Description: This function allows a peripheral to continue operating when the processor goes into sleep mode. Since the clocking conﬁguration of the device does not change, any peripheral can safely continue operating while the processor is in sleep mode, and can therefore wake the processor from sleep mode.
Page 217 System Control Parameters: ui32Type is the type of calibration to perform. Description: This function performs a calibration of the PIOSC. There are three types of calibration available; the desired calibration type as speciﬁed in ui32Type is one of: SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the 32 kHz clock from the hibernate module as a reference.
Page 218 System Control ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlPWMClockSet is a function pointer located at ROM_SYSCTLTABLE[25]. Parameters: ui32Conﬁg is the conﬁguration for the PWM clock; it must be one of SYSCTL_PWMDIV_1, SYSCTL_PWMDIV_2, SYSCTL_PWMDIV_4, SYSCTL_PWMDIV_8,...
Page 219 System Control ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlResetCauseClear is a function pointer located at ROM_SYSCTLTABLE[22]. Parameters: ui32Causes are the reset causes to be cleared; must be a logical OR of SYSCTL_CAUSE_LDO, SYSCTL_CAUSE_SW, SYSCTL_CAUSE_WDOG,...
Page 220 System Control ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlSleep is a function pointer located at ROM_SYSCTLTABLE[0]. Description: This function places the processor into sleep mode; it will not return until the processor re- turns to run mode.
Page 221 System Control 18.2.1.35 ROM_SysCtlUSBPLLEnable Powers up the USB PLL. Prototype: void ROM_SysCtlUSBPLLEnable(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13]. ROM_SysCtlUSBPLLEnable is a function pointer located at ROM_SYSCTLTABLE[31]. Description: This function will enable the USB controller’s PLL which is used by it’s physical layer.
Page 222 System Control April 8, 2013...
Page 223: System Exception Module
System Exception Module System Exception Module Introduction ................... . . 223 API Functions .
Page 224 System Exception Module SYSEXCP_INT_FP_UFC - Floating-point underﬂow exception interrupt SYSEXCP_INT_FP_IOC - Floating-point invalid operation interrupt SYSEXCP_INT_FP_DZC - Floating-point divide by zero exception interrupt SYSEXCP_INT_FP_IDC - Floating-point input denormal exception interrupt Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared.
Page 225 System Exception Module 19.2.1.3 ROM_SysExcIntEnable Enables individual system exception interrupt sources. Prototype: void ROM_SysExcIntEnable(uint32_t ui32IntFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSEXCTABLE is an array of pointers located at ROM_APITABLE[30]. ROM_SysExcIntEnable is a function pointer located at ROM_SYSEXCTABLE[3]. Parameters: ui32IntFlags is the bit mask of the interrupt sources to be enabled.
Page 226 System Exception Module Returns: Returns the current system exception interrupt status, enumerated as the logical OR of SYSEXCP_INT_FP_IXC, SYSEXCP_INT_FP_OFC, SYSEXCP_INT_FP_UFC, SY- SEXCP_INT_FP_IOC, SYSEXCP_INT_FP_DZC, and SYSEXCP_INT_FP_IDC. April 8, 2013...
Page 227: System Tick (Systick)
System Tick (SysTick) System Tick (SysTick) Introduction ................... . . 227 Functions .
Page 228 System Tick (SysTick) Returns: None. 20.2.1.2 ROM_SysTickEnable Enables the SysTick counter. Prototype: void ROM_SysTickEnable(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSTICKTABLE is an array of pointers located at ROM_APITABLE[10]. ROM_SysTickEnable is a function pointer located at ROM_SYSTICKTABLE[1]. Description: This will start the SysTick counter.
Page 229 System Tick (SysTick) 20.2.1.4 ROM_SysTickIntEnable Enables the SysTick interrupt. Prototype: void ROM_SysTickIntEnable(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSTICKTABLE is an array of pointers located at ROM_APITABLE[10]. ROM_SysTickIntEnable is a function pointer located at ROM_SYSTICKTABLE[3]. Description: This function will enable the SysTick interrupt, allowing it to be reﬂected to the processor.
Page 230 System Tick (SysTick) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_SYSTICKTABLE is an array of pointers located at ROM_APITABLE[10]. ROM_SysTickPeriodSet is a function pointer located at ROM_SYSTICKTABLE[5]. Parameters: ui32Period is the number of clock ticks in each period of the SysTick counter; must be be- tween 1 and 16,777,216, inclusive.
Page 231: Timer
Timer Timer Introduction ................... . . 231 Functions .
Page 232 Timer void ROM_TimerDisable (uint32_t ui32Base, uint32_t ui32Timer) void ROM_TimerEnable (uint32_t ui32Base, uint32_t ui32Timer) void ROM_TimerIntClear (uint32_t ui32Base, uint32_t ui32IntFlags) void ROM_TimerIntDisable (uint32_t ui32Base, uint32_t ui32IntFlags) void ROM_TimerIntEnable (uint32_t ui32Base, uint32_t ui32IntFlags) uint32_t ROM_TimerIntStatus (uint32_t ui32Base, bool bMasked) uint32_t ROM_TimerLoadGet (uint32_t ui32Base, uint32_t ui32Timer) uint64_t ROM_TimerLoadGet64 (uint32_t ui32Base)
Page 233 Timer that can operate independently or be concatenated to form a 32-bit timer. Similarly, the 32/64- bit variety is comprised of two 32-bit timers that can operate independently or be concatenated to form a 64-bit timer. The conﬁguration is speciﬁed in ui32Conﬁg as one of the following values: TIMER_CFG_ONE_SHOT - Full-width one-shot timer TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up instead of down (not available on all parts)
Page 234 Timer Parameters: ui32Base is the base address of the timer module. ui32Timer speciﬁes the timer(s) to be adjusted; must be one of TIMER_A, TIMER_B, or TIMER_BOTH. ui32Event speciﬁes the type of event; must be one of TIMER_EVENT_POS_EDGE, TIMER_EVENT_NEG_EDGE, or TIMER_EVENT_BOTH_EDGES. Description: This function sets the signal edge(s) that triggers the timer when in capture mode.
Page 235 Timer ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerControlStall is a function pointer located at ROM_TIMERTABLE[7]. Parameters: ui32Base is the base address of the timer module. ui32Timer speciﬁes the timer(s) to be adjusted; must be one of TIMER_A, TIMER_B, or TIMER_BOTH.
Page 236 Timer Prototype: void ROM_TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. function pointer located ROM_TimerControlWaitOnTrigger ROM_TIMERTABLE[22]. Parameters: ui32Base is the base address of the timer module. ui32Timer speciﬁes the timer(s) to be adjusted;...
Page 237 Timer 21.2.1.8 ROM_TimerEnable Enables the timer(s). Prototype: void ROM_TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerEnable is a function pointer located at ROM_TIMERTABLE[1]. Parameters: ui32Base is the base address of the timer module.
Page 238 Timer Note: Because there is a write buffer in the Cortex-M4 processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared.
Page 239 Timer Parameters: ui32Base is the base address of the timer module. ui32IntFlags is the bit mask of the interrupt sources to be enabled. Description: Enables the indicated timer interrupt sources. Only the sources that are enabled can be re- ﬂected to the processor interrupt; disabled sources have no effect on the processor. The ui32IntFlags parameter must be the logical OR of any combination of the following: TIMER_CAPB_EVENT - Capture B event interrupt TIMER_CAPB_MATCH - Capture B match interrupt...
Page 240 Timer 21.2.1.13 ROM_TimerLoadGet Gets the timer load value. Prototype: uint32_t ROM_TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerLoadGet is a function pointer located at ROM_TIMERTABLE[15]. Parameters: ui32Base is the base address of the timer module.
Page 241 Timer 21.2.1.15 ROM_TimerLoadSet Sets the timer load value. Prototype: void ROM_TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerLoadSet is a function pointer located at ROM_TIMERTABLE[14]. Parameters: ui32Base is the base address of the timer module.
Page 242 Timer Description: This function sets the timer load value for a 64-bit timer; if the timer is running then the value is immediately loaded into the timer. Returns: None. 21.2.1.17 ROM_TimerMatchGet Gets the timer match value. Prototype: uint32_t ROM_TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 243 Timer Description: This function gets the match value for the speciﬁed timer. Returns: Returns the match value for the timer. 21.2.1.19 ROM_TimerMatchSet Sets the timer match value. Prototype: void ROM_TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11].
Page 244 Timer ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerMatchSet64 is a function pointer located at ROM_TIMERTABLE[26]. Parameters: ui32Base is the base address of the timer module. ui64Value is the match value. Description: This function sets the match value for a timer.
Page 245 Timer ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerPrescaleMatchGet is a function pointer located at ROM_TIMERTABLE[13]. Parameters: ui32Base is the base address of the timer module. ui32Timer speciﬁes the timer; must be one of TIMER_A or TIMER_B. Description: This function gets the value of the input clock prescaler match value.
Page 246 Timer Prototype: void ROM_TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerPrescaleSet is a function pointer located at ROM_TIMERTABLE[10]. Parameters: ui32Base is the base address of the timer module. ui32Timer speciﬁes the timer(s) to adjust;...
Page 247 Timer Prototype: void ROM_TimerRTCEnable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerRTCEnable is a function pointer located at ROM_TIMERTABLE[8]. Parameters: ui32Base is the base address of the timer module. Description: This function causes the timer to start counting when in RTC mode.
Page 248 Timer 21.2.1.28 ROM_TimerValueGet64 Gets the current 64-bit timer value. Prototype: uint64_t ROM_TimerValueGet64(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_TIMERTABLE is an array of pointers located at ROM_APITABLE[11]. ROM_TimerValueGet64 is a function pointer located at ROM_TIMERTABLE[25]. Parameters: ui32Base is the base address of the timer module.
Page 249: Uart
UART UART Introduction ................... . . 249 Functions .
Page 250 UART void ROM_UARTClockSourceSet (uint32_t ui32Base, uint32_t ui32Source) void ROM_UARTConﬁgGetExpClk (uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t pui32Baud, uint32_t pui32Conﬁg) void ROM_UARTConﬁgSetExpClk (uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Conﬁg) void ROM_UARTDisable (uint32_t ui32Base) void ROM_UARTDisableSIR (uint32_t ui32Base) void ROM_UARTDMADisable (uint32_t ui32Base, uint32_t ui32DMAFlags) void ROM_UARTDMAEnable (uint32_t ui32Base, uint32_t ui32DMAFlags)
Page 251 UART ui8Addr is the address to be transmitted. Description: This function waits until all data has been sent from the speciﬁed port and then sends the given address as an address byte. It then waits until the address byte has been transmitted before returning.
Page 252 UART ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UART9BitDisable is a function pointer located at ROM_UARTTABLE[34]. Parameters: ui32Base is the base address of the UART port. Description: This function disables the 9-bit operational mode of the UART.
Page 253 UART bBreakState controls the output level. Description: Calling this function with bBreakState set to true asserts a break condition on the UART. Calling this function with bBreakState set to false removes the break condition. For proper transmis- sion of a break command, the break must be asserted for at least two complete frames. Returns: None.
Page 254 UART Description: Gets a character from the receive FIFO for the speciﬁed port. If there are no characters avail- able, this function waits until a character is received before returning. Returns: Returns the character read from the speciﬁed port, cast as a int32_t. 22.2.1.8 ROM_UARTCharGetNonBlocking Receives a character from the speciﬁed port.
Page 255 UART Returns: None. 22.2.1.10 ROM_UARTCharPutNonBlocking Sends a character to the speciﬁed port. Prototype: bool ROM_UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTCharPutNonBlocking is a function pointer located at ROM_UARTTABLE[15]. Parameters: ui32Base is the base address of the UART port.
Page 256 UART 22.2.1.12 ROM_UARTClockSourceGet Gets the baud clock source for the speciﬁed UART. Prototype: uint32_t ROM_UARTClockSourceGet(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTClockSourceGet is a function pointer located at ROM_UARTTABLE[32]. Parameters: ui32Base is the base address of the UART port.
Page 257 UART 22.2.1.14 ROM_UARTConﬁgGetExpClk Gets the current conﬁguration of a UART. Prototype: void ROM_UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t * pui32Baud, uint32_t * pui32Config) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTConfigGetExpClk is a function pointer located at ROM_UARTTABLE[6].
Page 258 UART Parameters: ui32Base is the base address of the UART port. ui32UARTClk is the rate of the clock supplied to the UART module. ui32Baud is the desired baud rate. ui32Conﬁg is the data format for the port (number of data bits, number of stop bits, and parity). Description: This function conﬁgures the UART for operation in the speciﬁed data format.
Page 259 UART 22.2.1.17 ROM_UARTDisableSIR Disables SIR (IrDA) mode on the speciﬁed UART. Prototype: void ROM_UARTDisableSIR(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTDisableSIR is a function pointer located at ROM_UARTTABLE[10]. Parameters: ui32Base is the base address of the UART port.
Page 260 UART 22.2.1.19 ROM_UARTDMAEnable Enable UART DMA operation. Prototype: void ROM_UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTDMAEnable is a function pointer located at ROM_UARTTABLE[22]. Parameters: ui32Base is the base address of the UART port.
Page 261 UART 22.2.1.21 ROM_UARTEnableSIR Enables SIR (IrDA) mode on the speciﬁed UART. Prototype: void ROM_UARTEnableSIR(uint32_t ui32Base, bool bLowPower) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTEnableSIR is a function pointer located at ROM_UARTTABLE[9]. Parameters: ui32Base is the base address of the UART port.
Page 262 UART Prototype: void ROM_UARTFIFOEnable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTFIFOEnable is a function pointer located at ROM_UARTTABLE[24]. Parameters: ui32Base is the base address of the UART port. Description: This functions enables the transmit and receive FIFOs in the UART.
Page 263 UART Prototype: void ROM_UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, uint32_t ui32RxLevel) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTFIFOLevelSet is a function pointer located at ROM_UARTTABLE[3]. Parameters: ui32Base is the base address of the UART port. ui32TxLevel is the transmit FIFO interrupt level, speciﬁed as one of UART_FIFO_TX1_8, UART_FIFO_TX2_8, UART_FIFO_TX4_8, UART_FIFO_TX6_8, or UART_FIFO_TX7_8.
Page 264 UART source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).
Page 265 UART ui32IntFlags is the bit mask of the interrupt sources to be enabled. Description: Enables the indicated UART interrupt sources. Only the sources that are enabled can be reﬂected to the processor interrupt; disabled sources have no effect on the processor. The ui32IntFlags parameter is the logical OR of any of the following: UART_INT_9BIT - 9-bit address match interrupt UART_INT_OE - Overrun Error interrupt...
Page 266 UART 22.2.1.30 ROM_UARTParityModeGet Gets the type of parity currently being used. Prototype: uint32_t ROM_UARTParityModeGet(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTParityModeGet is a function pointer located at ROM_UARTTABLE[2]. Parameters: ui32Base is the base address of the UART port.
Page 267 UART 22.2.1.32 ROM_UARTRxErrorClear Clears all reported receiver errors. Prototype: void ROM_UARTRxErrorClear(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTRxErrorClear is a function pointer located at ROM_UARTTABLE[30]. Parameters: ui32Base is the base address of the UART port.
Page 268 UART 22.2.1.34 ROM_UARTSpaceAvail Determines if there is any space in the transmit FIFO. Prototype: bool ROM_UARTSpaceAvail(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTSpaceAvail is a function pointer located at ROM_UARTTABLE[12]. Parameters: ui32Base is the base address of the UART port.
Page 269 UART 22.2.1.36 ROM_UARTTxIntModeSet Sets the operating mode for the UART transmit interrupt. Prototype: void ROM_UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UARTTABLE is an array of pointers located at ROM_APITABLE[1]. ROM_UARTTxIntModeSet is a function pointer located at ROM_UARTTABLE[27]. Parameters: ui32Base is the base address of the UART port.
Page 270 UART April 8, 2013...
Page 271: Udma Controller
uDMA Controller uDMA Controller Introduction ................... . . 271 Functions .
Page 272 uDMA Controller Peripheral scatter/gather mode is similar to memory scatter/gather mode except that it is controlled by a peripheral request. Detailed explanation of the various transfer modes is beyond the scope of this document. Please refer to the device data sheet for more information on the operation of the uDMA controller. The naming convention for the microDMA controller is to use the Greek letter “mu”...
Page 273: Functions
uDMA Controller There are additional functions that can be used to query the status of a channel, either from an interrupt handler or in polling fashion. The function ROM_uDMAChannelSizeGet() is used to ﬁnd the amount of data remaining to transfer on a channel. This will be zero when a transfer is complete. The function ROM_uDMAChannelModeGet() can be used to ﬁnd the transfer mode of a uDMA...
Page 274 uDMA Controller void ROM_uDMADisable (void) void ROM_uDMAEnable (void) void ROM_uDMAErrorStatusClear (void) uint32_t ROM_uDMAErrorStatusGet (void) void ROM_uDMAIntClear (uint32_t ui32ChanMask) uint32_t ROM_uDMAIntStatus (void) 23.2.1 Function Documentation 23.2.1.1 ROM_uDMAChannelAssign Assigns a peripheral mapping for a uDMA channel. Prototype: void ROM_uDMAChannelAssign(uint32_t ui32Mapping) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 275 uDMA Controller Parameters: ui32ChannelNum is the channel to conﬁgure. ui32Attr is a combination of attributes for the channel. Description: This function is used to disable attributes of a uDMA channel. The ui32ChannelNum parameter must be only one of the following values: UDMA_CHANNEL_ADC0 UDMA_CHANNEL_ADC1 UDMA_CHANNEL_ADC2...
Page 276 uDMA Controller UDMA_CHANNEL_USBEP1TX UDMA_CHANNEL_USBEP2RX UDMA_CHANNEL_USBEP2TX UDMA_CHANNEL_USBEP3RX UDMA_CHANNEL_USBEP3TX UDMA_CHANNEL_SW UDMA_SEC_CHANNEL_SW The ui32Attr parameter is the logical OR of any of the following: UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. UDMA_ATTR_ALTSELECT is used to select the alternate control structure for this chan- nel.
Page 277 uDMA Controller UDMA_SEC_CHANNEL_ADC13 UDMA_CHANNEL_SSI0RX UDMA_CHANNEL_SSI0TX UDMA_CHANNEL_SSI1RX UDMA_CHANNEL_SSI1TX UDMA_SEC_CHANNEL_SSI1RX UDMA_SEC_CHANNEL_SSI1TX UDMA_CHANNEL_TMR0A UDMA_CHANNEL_TMR0B UDMA_CHANNEL_TMR1A UDMA_CHANNEL_TMR1B UDMA_SEC_CHANNEL_TMR1A UDMA_SEC_CHANNEL_TMR1B UDMA_SEC_CHANNEL_TMR2A_4 UDMA_SEC_CHANNEL_TMR2B_5 UDMA_SEC_CHANNEL_TMR2A_6 UDMA_SEC_CHANNEL_TMR2B_7 UDMA_SEC_CHANNEL_TMR2A_14 UDMA_SEC_CHANNEL_TMR2B_15 UDMA_SEC_CHANNEL_TMR3A UDMA_SEC_CHANNEL_TMR3B UDMA_CHANNEL_UART0RX UDMA_CHANNEL_UART0TX UDMA_CHANNEL_UART1RX UDMA_CHANNEL_UART1TX UDMA_SEC_CHANNEL_UART1RX UDMA_SEC_CHANNEL_UART1TX UDMA_SEC_CHANNEL_UART2RX_0 UDMA_SEC_CHANNEL_UART2TX_1 UDMA_SEC_CHANNEL_UART2RX_12 UDMA_SEC_CHANNEL_UART2TX_13 UDMA_CHANNEL_USBEP1RX UDMA_CHANNEL_USBEP1TX UDMA_CHANNEL_USBEP2RX UDMA_CHANNEL_USBEP2TX UDMA_CHANNEL_USBEP3RX UDMA_CHANNEL_USBEP3TX UDMA_CHANNEL_SW UDMA_SEC_CHANNEL_SW The ui32Attr parameter is the logical OR of any of the following: UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
Page 278 uDMA Controller UDMA_ATTR_REQMASK is used to mask the hardware request signal from the periph- eral for this channel. Returns: None. 23.2.1.4 ROM_uDMAChannelAttributeGet Gets the enabled attributes of a uDMA channel. Prototype: uint32_t ROM_uDMAChannelAttributeGet(uint32_t ui32ChannelNum) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17].
Page 279 uDMA Controller UDMA_SEC_CHANNEL_TMR2A_6 UDMA_SEC_CHANNEL_TMR2B_7 UDMA_SEC_CHANNEL_TMR2A_14 UDMA_SEC_CHANNEL_TMR2B_15 UDMA_SEC_CHANNEL_TMR3A UDMA_SEC_CHANNEL_TMR3B UDMA_CHANNEL_UART0RX UDMA_CHANNEL_UART0TX UDMA_CHANNEL_UART1RX UDMA_CHANNEL_UART1TX UDMA_SEC_CHANNEL_UART1RX UDMA_SEC_CHANNEL_UART1TX UDMA_SEC_CHANNEL_UART2RX_0 UDMA_SEC_CHANNEL_UART2TX_1 UDMA_SEC_CHANNEL_UART2RX_12 UDMA_SEC_CHANNEL_UART2TX_13 UDMA_CHANNEL_USBEP1RX UDMA_CHANNEL_USBEP1TX UDMA_CHANNEL_USBEP2RX UDMA_CHANNEL_USBEP2TX UDMA_CHANNEL_USBEP3RX UDMA_CHANNEL_USBEP3TX UDMA_CHANNEL_SW UDMA_SEC_CHANNEL_SW Returns: Returns the logical OR of the attributes of the uDMA channel, which can be any of the following: UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
Page 280 uDMA Controller Parameters: ui32ChannelStructIndex is the logical OR of the uDMA channel number with UDMA_PRI_SELECT or UDMA_ALT_SELECT. ui32Control is logical OR of several control values to set the control parameters for the chan- nel. Description: This function is used to set control parameters for a uDMA transfer. These are typically param- eters that are not changed often.
Page 281 uDMA Controller Parameters: ui32ChannelNum is the channel number to disable. Description: This function disables a speciﬁc uDMA channel. Once disabled, a channel will not respond to uDMA transfer requests until re-enabled via ROM_uDMAChannelEnable(). The ui32ChannelNum parameter must be only one of the following values: UDMA_CHANNEL_ADC0 UDMA_CHANNEL_ADC1 UDMA_CHANNEL_ADC2...
Page 282 uDMA Controller UDMA_CHANNEL_USBEP1TX UDMA_CHANNEL_USBEP2RX UDMA_CHANNEL_USBEP2TX UDMA_CHANNEL_USBEP3RX UDMA_CHANNEL_USBEP3TX UDMA_CHANNEL_SW UDMA_SEC_CHANNEL_SW Returns: None. 23.2.1.7 ROM_uDMAChannelEnable Enables a uDMA channel for operation. Prototype: void ROM_uDMAChannelEnable(uint32_t ui32ChannelNum) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17]. ROM_uDMAChannelEnable is a function pointer located at ROM_UDMATABLE[5].
Page 283 uDMA Controller UDMA_CHANNEL_TMR0A UDMA_CHANNEL_TMR0B UDMA_CHANNEL_TMR1A UDMA_CHANNEL_TMR1B UDMA_SEC_CHANNEL_TMR1A UDMA_SEC_CHANNEL_TMR1B UDMA_SEC_CHANNEL_TMR2A_4 UDMA_SEC_CHANNEL_TMR2B_5 UDMA_SEC_CHANNEL_TMR2A_6 UDMA_SEC_CHANNEL_TMR2B_7 UDMA_SEC_CHANNEL_TMR2A_14 UDMA_SEC_CHANNEL_TMR2B_15 UDMA_SEC_CHANNEL_TMR3A UDMA_SEC_CHANNEL_TMR3B UDMA_CHANNEL_UART0RX UDMA_CHANNEL_UART0TX UDMA_CHANNEL_UART1RX UDMA_CHANNEL_UART1TX UDMA_SEC_CHANNEL_UART1RX UDMA_SEC_CHANNEL_UART1TX UDMA_SEC_CHANNEL_UART2RX_0 UDMA_SEC_CHANNEL_UART2TX_1 UDMA_SEC_CHANNEL_UART2RX_12 UDMA_SEC_CHANNEL_UART2TX_13 UDMA_CHANNEL_USBEP1RX UDMA_CHANNEL_USBEP1TX UDMA_CHANNEL_USBEP2RX UDMA_CHANNEL_USBEP2TX UDMA_CHANNEL_USBEP3RX UDMA_CHANNEL_USBEP3TX UDMA_CHANNEL_SW UDMA_SEC_CHANNEL_SW Returns: None. 23.2.1.8 ROM_uDMAChannelIsEnabled Checks if a uDMA channel is enabled for operation. Prototype: bool ROM_uDMAChannelIsEnabled(uint32_t ui32ChannelNum)
Page 284 uDMA Controller Parameters: ui32ChannelNum is the channel number to check. Description: This function checks to see if a speciﬁc uDMA channel is enabled. This can be used to check the status of a transfer, since the channel will be automatically disabled at the end of a transfer. The ui32ChannelNum parameter must be only one of the following values: UDMA_CHANNEL_ADC0 UDMA_CHANNEL_ADC1...
Page 285 uDMA Controller UDMA_CHANNEL_USBEP1TX UDMA_CHANNEL_USBEP2RX UDMA_CHANNEL_USBEP2TX UDMA_CHANNEL_USBEP3RX UDMA_CHANNEL_USBEP3TX UDMA_CHANNEL_SW UDMA_SEC_CHANNEL_SW Returns: Returns true if the channel is enabled, false if disabled. 23.2.1.9 ROM_uDMAChannelModeGet Gets the transfer mode for a uDMA channel control structure. Prototype: uint32_t ROM_uDMAChannelModeGet(uint32_t ui32ChannelStructIndex) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17].
Page 286 uDMA Controller Parameters: ui32ChannelNum is the channel number on which to request a uDMA transfer. Description: This function allows software to request a uDMA channel to begin a transfer. This could be used for performing a memory to memory transfer, or if for some reason a transfer needs to be initiated by software instead of the peripheral associated with that channel.
Page 287 uDMA Controller UDMA_CHANNEL_USBEP1RX UDMA_CHANNEL_USBEP1TX UDMA_CHANNEL_USBEP2RX UDMA_CHANNEL_USBEP2TX UDMA_CHANNEL_USBEP3RX UDMA_CHANNEL_USBEP3TX UDMA_CHANNEL_SW UDMA_SEC_CHANNEL_SW Note: If the channel is UDMA_CHANNEL_SW and interrupts are used, then the completion is sig- naled on the uDMA dedicated interrupt. If a peripheral channel is used, then the completion is signaled on the peripheral’s interrupt.
Page 288 uDMA Controller 23.2.1.12 ROM_uDMAChannelSelectDefault Selects the default peripheral for a set of uDMA channels. Prototype: void ROM_uDMAChannelSelectDefault(uint32_t ui32DefPeriphs) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17]. ROM_uDMAChannelSelectDefault is a function pointer located at ROM_UDMATABLE[18]. Parameters: ui32DefPeriphs is the logical or of the uDMA channels for which to use the default peripheral, instead of the secondary peripheral.
Page 289 uDMA Controller 23.2.1.13 ROM_uDMAChannelSelectSecondary Selects the secondary peripheral for a set of uDMA channels. Prototype: void ROM_uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17]. function pointer located ROM_uDMAChannelSelectSecondary ROM_UDMATABLE[17].
Page 290 uDMA Controller 23.2.1.14 ROM_uDMAChannelSizeGet Gets the current transfer size for a uDMA channel control structure. Prototype: uint32_t ROM_uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17]. ROM_uDMAChannelSizeGet is a function pointer located at ROM_UDMATABLE[15]. Parameters: ui32ChannelStructIndex is the logical OR of the uDMA channel number with either UDMA_PRI_SELECT or UDMA_ALT_SELECT.
Page 291 uDMA Controller Description: This function is used to set the parameters for a uDMA transfer. These are typically parameters that are changed often. The function ROM_uDMAChannelControlSet() MUST be called at least once for this channel prior to calling this function. The ui32ChannelStructIndex parameter should be the logical OR of the channel number with one of UDMA_PRI_SELECT or UDMA_ALT_SELECT to choose whether the primary or alter- nate data structure is used.
Page 292 uDMA Controller Prototype: void * ROM_uDMAControlAlternateBaseGet(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17]. function pointer located ROM_uDMAControlAlternateBaseGet ROM_UDMATABLE[21]. Description: This function gets the base address of the second half of the channel control table that holds the alternate control structures for each channel.
Page 293 uDMA Controller Description: This function sets the base address of the channel control table. This table resides in system memory and holds control information for each uDMA channel. The table must be aligned on a 1024 byte boundary. The base address must be set before any of the channel functions can be used.
Page 294 uDMA Controller 23.2.1.21 ROM_uDMAErrorStatusClear Clears the uDMA error interrupt. Prototype: void ROM_uDMAErrorStatusClear(void) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_UDMATABLE is an array of pointers located at ROM_APITABLE[17]. ROM_uDMAErrorStatusClear is a function pointer located at ROM_UDMATABLE[4]. Description: This function clears a pending uDMA error interrupt.
Page 295 uDMA Controller Parameters: ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. Description: Clears bits in the uDMA interrupt status register according to which bits are set in ui32ChanMask . There is one bit for each channel. If a a bit is set in ui32ChanMask , then that corresponding channel’s interrupt status is cleared (if it was set).
Page 296 uDMA Controller April 8, 2013...
Page 297: Usb Controller
USB Controller USB Controller Introduction ................... . . 297 Using uDMA with USB .
Page 298: Using Usb With The Udma Controller
USB Controller // 64-576 - endpoint 1 IN (512 bytes). // 576-1088 - endpoint 1 OUT (512 bytes). // 1088-1600 - endpoint 2 IN (512 bytes). // FIFO for endpoint 1 IN starts at address 64 and is 512 bytes in size. ROM_USBFIFOConfigSet(USB0_BASE, USB_EP_1, 64, USB_FIFO_SZ_512, USB_EP_DEV_IN);...
Page 299 USB Controller Example: Endpoint conﬁguration for a device IN endpoint: // Endpoint 1 is a device mode BULK IN endpoint using uDMA. ROM_USBDevEndpointConfigSet(USB0_BASE, USB_EP_1, 64, (USB_EP_MODE_BULK | USB_EP_DEV_IN | USB_EP_DMA_MODE_0 | USB_EP_AUTO_SET)); The application must provide the conﬁguration of the actual uDMA controller. First, to clear out any previous settings, the application should call ROM_uDMAChannelAttributeDisable().
Page 300 USB Controller Because the uDMA interrupt occurs on the same interrupt vector as any other USB interrupt, the application must perform an extra check to determine what was the actual source of the interrupt. It is important to note that this DMA interrupt does not mean that the USB transfer is complete, but that the data has been transferred to the USB controller’s FIFO.
Page 301 USB Controller by a call to ROM_uDMAChannelAttributeEnable() with the DMA_ATTR_USEBURST value. Note: All uDMA transfers used by the USB controller must use burst mode. The ﬁnal call sets the read access size to 8 bits wide, the source address increment to 0, the destination address increment to 8 bits and the uDMA arbitration size to 64 bytes.
Page 302: Functions
USB Controller // Handle a short packet. else if((g_ui32Flags & EP1_DMA_OUT_PEND) && (ROM_uDMAChannelModeGet(UDMA_CHANNEL_USBEP1RX) == UDMA_MODE_STOP)) // Handle the uDMA complete case. // Restart receive uDMA if desired. 24.3 Functions Functions void ROM_UpdateUSB (uint8_t pui8USBBootROMInfo) uint32_t ROM_USBDevAddrGet (uint32_t ui32Base) void ROM_USBDevAddrSet (uint32_t ui32Base, uint32_t ui32Address) void ROM_USBDevConnect...
Page 303 USB Controller void ROM_USBEndpointDMADisable (uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) void ROM_USBEndpointDMAEnable (uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) uint32_t ROM_USBEndpointStatus (uint32_t ui32Base, uint32_t ui32Endpoint) uint32_t ROM_USBFIFOAddrGet (uint32_t ui32Base, uint32_t ui32Endpoint) void ROM_USBFIFOConﬁgGet (uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t pui32FIFOAddress, uint32_t pui32FIFOSize, uint32_t ui32Flags) void ROM_USBFIFOConﬁgSet (uint32_t ui32Base,...
Page 304 USB Controller uint32_t ROM_USBModeGet (uint32_t ui32Base) uint32_t ROM_USBNumEndpointsGet (uint32_t ui32Base) void ROM_USBOTGMode (uint32_t ui32Base) void ROM_USBPHYPowerOff (uint32_t ui32Base) void ROM_USBPHYPowerOn (uint32_t ui32Base) 24.3.1 Function Documentation 24.3.1.1 ROM_UpdateUSB Starts an update over the USB interface. Prototype: void ROM_UpdateUSB(uint8_t * pui8USBBootROMInfo) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 305 USB Controller Description: This function will return the current device address. This address was set by a call to ROM_USBDevAddrSet(). Note: This function should only be called in device mode. Returns: The current device address. 24.3.1.3 ROM_USBDevAddrSet Sets the address in device mode. Prototype: void ROM_USBDevAddrSet(uint32_t ui32Base,...
Page 306 USB Controller Parameters: ui32Base speciﬁes the USB module base address. Description: This function will cause the soft connect feature of the USB controller to be enabled. Call ROM_USBDevDisconnect() to remove the USB device from the bus. Note: This function should only be called in device mode. Returns: None.
Page 307 USB Controller ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBDevEndpointConfigGet is a function pointer located at ROM_USBTABLE[41]. Parameters: ui32Base speciﬁes the USB module base address. ui32Endpoint is the endpoint to access. pui32MaxPacketSize is a pointer which is written with the maximum packet size for this end- point.
Page 308 USB Controller The USB_EP_MODE_ ﬂags deﬁne what the type is for the given endpoint. USB_EP_MODE_CTRL is a control endpoint. USB_EP_MODE_ISOC is an isochronous endpoint. USB_EP_MODE_BULK is a bulk endpoint. USB_EP_MODE_INT is an interrupt endpoint. The USB_EP_DMA_MODE_ ﬂags determines the type of DMA access to the endpoint data FI- FOs.
Page 309 USB Controller zero. The bIsLastPacket parameter is not used for endpoints other than endpoint zero. This call can be used if processing is required between reading the data and acknowledging that the data has been read. Note: This function should only be called in device mode. Returns: None.
Page 310 USB Controller ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBDevEndpointStallClear is a function pointer located at ROM_USBTABLE[8]. Parameters: ui32Base speciﬁes the USB module base address. ui32Endpoint speciﬁes which endpoint to remove the stall condition. ui32Flags speciﬁes whether to remove the stall condition from the IN or the OUT portion of this endpoint.
Page 311 USB Controller 24.3.1.12 ROM_USBDevMode Change the mode of the USB controller to device. Prototype: void ROM_USBDevMode(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBDevMode is a function pointer located at ROM_USBTABLE[55]. Parameters: ui32Base speciﬁes the USB module base address.
Page 312 USB Controller 24.3.1.14 ROM_USBEndpointDataGet Retrieves data from the given endpoint’s FIFO. Prototype: int32_t ROM_USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint8_t * pui8Data, uint32_t * pui32Size) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBEndpointDataGet is a function pointer located at ROM_USBTABLE[10].
Page 313 USB Controller ui32Endpoint is the endpoint to access. pui8Data is a pointer to the data area used as the source for the data to put into the FIFO. ui32Size is the amount of data to put into the FIFO. Description: This function will put the data from the pui8Data parameter into the FIFO for this endpoint.
Page 314 USB Controller 24.3.1.17 ROM_USBEndpointDataToggleClear Sets the Data toggle on an endpoint to zero. Prototype: void ROM_USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBEndpointDataToggleClear is a function pointer located at ROM_USBTABLE[13].
Page 315 USB Controller be used with transmit endpoints. This allows the 3 receive and 3 transmit DMA channels to be mapped to any endpoint other than 0. The values that should be passed into the ui32Channel value are the UDMA_CHANNEL_USBEP values deﬁned in udma.h. Note: This function only has an effect on microcontrollers that have the ability to change the DMA channel for an endpoint.
Page 316 USB Controller ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBEndpointDMAEnable is a function pointer located at ROM_USBTABLE[42]. Parameters: ui32Base speciﬁes the USB module base address. ui32Endpoint is the endpoint to access. ui32Flags speciﬁes which direction and what mode to use when enabling DMA.
Page 317 USB Controller USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than the speciﬁed timeout period. USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT request. USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. USB_HOST_OUT_ERROR - Failed to communicate with a device using this OUT end- point.
Page 318 USB Controller ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBFIFOAddrGet is a function pointer located at ROM_USBTABLE[15]. Parameters: ui32Base speciﬁes the USB module base address. ui32Endpoint speciﬁes which endpoint’s FIFO address to return. Description: This function returns the actual physical address of the FIFO.
Page 319 USB Controller 24.3.1.24 ROM_USBFIFOConﬁgSet Sets the FIFO conﬁguration for an endpoint. Prototype: void ROM_USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBFIFOConfigSet is a function pointer located at ROM_USBTABLE[17].
Page 320 USB Controller ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBFIFOFlush is a function pointer located at ROM_USBTABLE[18]. Parameters: ui32Base speciﬁes the USB module base address. ui32Endpoint is the endpoint to access. ui32Flags speciﬁes if the IN or OUT endpoint should be accessed.
Page 321 USB Controller ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostAddrGet is a function pointer located at ROM_USBTABLE[20]. Parameters: ui32Base speciﬁes the USB module base address. ui32Endpoint is the endpoint to access. ui32Flags determines if this is an IN or an OUT endpoint.
Page 322 USB Controller 24.3.1.29 ROM_USBHostEndpointConﬁg Sets the base conﬁguration for a host endpoint. Prototype: void ROM_USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, uint32_t ui32TargetEndpoint, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostEndpointConfig is a function pointer located at ROM_USBTABLE[22].
Page 323 USB Controller other is DISABLE_NAK_LIMIT which indicates that there should be no limit on the number of NAKs. The USB_EP_DMA_MODE_ ﬂags enables the type of DMA used to access the endpoint’s data FIFOs. The choice of the DMA mode depends on how the DMA controller is conﬁgured and how it is being used.
Page 324 USB Controller 24.3.1.31 ROM_USBHostEndpointDataToggle Sets the value data toggle on an endpoint in host mode. Prototype: void ROM_USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, bool bDataToggle, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostEndpointDataToggle is a function pointer located at ROM_USBTABLE[24].
Page 325 USB Controller ui32Endpoint is the endpoint to access. ui32Flags are the status bits that should be cleared. Description: This function will clear the status of any bits that are passed in the ui32Flags parameter. The ui32Flags parameter can take the value returned from the ROM_USBEndpointStatus() call.
Page 326 USB Controller uint32_t ui32Endpoint, uint32_t ui32Addr, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostHubAddrSet is a function pointer located at ROM_USBTABLE[27]. Parameters: ui32Base speciﬁes the USB module base address. ui32Endpoint is the endpoint to access.
Page 327 USB Controller 24.3.1.36 ROM_USBHostPwrConﬁg Sets the conﬁguration for USB power fault. Prototype: void ROM_USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostPwrConfig is a function pointer located at ROM_USBTABLE[30]. Parameters: ui32Base speciﬁes the USB module base address.
Page 328 USB Controller Note: This function should only be called in host mode. Returns: None. 24.3.1.37 ROM_USBHostPwrDisable Disables the external power pin. Prototype: void ROM_USBHostPwrDisable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostPwrDisable is a function pointer located at ROM_USBTABLE[28].
Page 329 USB Controller Note: This function should only be called in host mode. Returns: None. 24.3.1.39 ROM_USBHostPwrFaultDisable Disables power fault detection. Prototype: void ROM_USBHostPwrFaultDisable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostPwrFaultDisable is a function pointer located at ROM_USBTABLE[31].
Page 330 USB Controller Note: This function should only be called in host mode. Returns: None. 24.3.1.41 ROM_USBHostRequestIN Schedules a request for an IN transaction on an endpoint in host mode. Prototype: void ROM_USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16].
Page 331 USB Controller ui32Endpoint is the endpoint to access. Description: This function clears a previously scheduled IN transaction if it is still pending. This function is used to safely disable any scheduled IN transactions if the endpoint speciﬁed by ui32Endpoint is reconﬁgured for communications with other devices. Note: This function must only be called in host mode and only for IN endpoints.
Page 332 USB Controller Parameters: ui32Base speciﬁes the USB module base address. bStart speciﬁes whether to start or stop signaling reset on the USB bus. Description: When this function is called with the bStart parameter set to true, this function will cause the start of a reset condition on the USB bus.
Page 333 USB Controller Prototype: uint32_t ROM_USBHostSpeedGet(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBHostSpeedGet is a function pointer located at ROM_USBTABLE[37]. Parameters: ui32Base speciﬁes the USB module base address. Description: This function will return the current speed of the USB bus.
Page 334 USB Controller Prototype: void ROM_USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBIntDisableControl is a function pointer located at ROM_USBTABLE[48]. Parameters: ui32Base speciﬁes the USB module base address. ui32Flags speciﬁes which control interrupts to disable.
Page 335 USB Controller 24.3.1.50 ROM_USBIntEnableControl Enables control interrupts on a given USB controller. Prototype: void ROM_USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBIntEnableControl is a function pointer located at ROM_USBTABLE[49]. Parameters: ui32Base speciﬁes the USB module base address.
Page 336 USB Controller 24.3.1.52 ROM_USBIntStatusControl Returns the control interrupt status on a given USB controller. Prototype: uint32_t ROM_USBIntStatusControl(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBIntStatusControl is a function pointer located at ROM_USBTABLE[50]. Parameters: ui32Base speciﬁes the USB module base address.
Page 337 USB Controller Prototype: uint32_t ROM_USBIntStatusEndpoint(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBIntStatusEndpoint is a function pointer located at ROM_USBTABLE[53]. Parameters: ui32Base speciﬁes the USB module base address. Description: This function will read endpoint interrupt status for a USB controller.
Page 338 USB Controller USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode on the A-side of the cable. USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode on the B-side of the cable. USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode on the B-side of the cable.
Page 339 USB Controller 24.3.1.56 ROM_USBOTGMode Change the mode of the USB controller to OTG. Prototype: void ROM_USBOTGMode(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBOTGMode is a function pointer located at ROM_USBTABLE[59]. Parameters: ui32Base speciﬁes the USB module base address.
Page 340 USB Controller ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_USBTABLE is an array of pointers located at ROM_APITABLE[16]. ROM_USBPHYPowerOn is a function pointer located at ROM_USBTABLE[57]. Parameters: ui32Base speciﬁes the USB module base address. Description: This function will power on the USB PHY, enabling it return to normal operation. By default, the PHY is powered on, so this function only needs to be called if ROM_USBPHYPowerOff() previously been called.
Page 341: Watchdog Timer
Watchdog Timer Watchdog Timer Introduction ................... . . 341 Functions .
Page 342 Watchdog Timer void ROM_WatchdogUnlock (uint32_t ui32Base) uint32_t ROM_WatchdogValueGet (uint32_t ui32Base) 25.2.1 Function Documentation 25.2.1.1 ROM_WatchdogEnable Enables the watchdog timer. Prototype: void ROM_WatchdogEnable(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_WATCHDOGTABLE is an array of pointers located at ROM_APITABLE[12]. ROM_WatchdogEnable is a function pointer located at ROM_WATCHDOGTABLE[2].
Page 343 Watchdog Timer Note: Because there is a write buffer in the Cortex-M4 processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared.
Page 344 Watchdog Timer Parameters: ui32Base is the base address of the watchdog timer module. bMasked is false if the raw interrupt status is required and true if the masked interrupt status is required. Description: This returns the interrupt status for the watchdog timer module. Either the raw interrupt status or the status of interrupt that is allowed to reﬂect to the processor can be returned.
Page 345 Watchdog Timer ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_WATCHDOGTABLE is an array of pointers located at ROM_APITABLE[12]. ROM_WatchdogLock is a function pointer located at ROM_WATCHDOGTABLE[5]. Parameters: ui32Base is the base address of the watchdog timer module. Description: Locks out write access to the watchdog timer conﬁguration registers.
Page 346 Watchdog Timer Description: This function gets the value that is loaded into the watchdog timer when the count reaches zero for the ﬁrst time. See also: ROM_WatchdogReloadSet() Returns: None. 25.2.1.9 ROM_WatchdogReloadSet Sets the watchdog timer reload value. Prototype: void ROM_WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010.
Page 347 Watchdog Timer ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_WATCHDOGTABLE is an array of pointers located at ROM_APITABLE[12]. ROM_WatchdogResetDisable is a function pointer located at ROM_WATCHDOGTABLE[4]. Parameters: ui32Base is the base address of the watchdog timer module. Description: Disables the capability of the watchdog timer to issue a reset to the processor upon a second timeout condition.
Page 348 Watchdog Timer 25.2.1.12 ROM_WatchdogRunning Determines if the watchdog timer is enabled. Prototype: bool ROM_WatchdogRunning(uint32_t ui32Base) ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_WATCHDOGTABLE is an array of pointers located at ROM_APITABLE[12]. ROM_WatchdogRunning is a function pointer located at ROM_WATCHDOGTABLE[1]. Parameters: ui32Base is the base address of the watchdog timer module.
Page 349 Watchdog Timer ROM Location: ROM_APITABLE is an array of pointers located at 0x0100.0010. ROM_WATCHDOGTABLE is an array of pointers located at ROM_APITABLE[12]. ROM_WatchdogStallEnable is a function pointer located at ROM_WATCHDOGTABLE[13]. Parameters: ui32Base is the base address of the watchdog timer module. Description: This function allows the watchdog timer to stop counting when the processor is stopped by the debugger.
Page 350 Watchdog Timer Parameters: ui32Base is the base address of the watchdog timer module. Description: This function reads the current value of the watchdog timer. Returns: Returns the current value of the watchdog timer. April 8, 2013...
Page 351 April 8, 2013...
Page 352: Important Notice
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

Texas Instruments Tiva TM4C123GH6PM User Manual

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1 Introduction

2 Boot Loader

3 AES Data Tables

4 Analog Comparator

5 Analog to Digital Converter (ADC)

6 Controller Area Network (CAN)

7 Crc

8 Flash

9 Floating-Point Unit (FPU)

10 Gpio

11 Hibernation Module

12 Inter-Integrated Circuit (I2C)

13 Interrupt Controller (NVIC)

14 Memory Protection Unit (MPU)

15 Pulse Width Modulator (PWM)

16 Quadrature Encoder (QEI)

17 Synchronous Serial Interface (SSI)

18 System Control

19 System Exception Module

20 System Tick (Systick)

21 Timer

22 Uart

23 Udma Controller

24 USB Controller

25 Watchdog Timer

Important Notice

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