Mitsubishi Electric MELSEC A Series Manual page 27

Programmable logic controller
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3. SPECIFICATIONS
(2) A – D conversion ready (X1)
The X1 signal goes ON when A-D conversion processing is ready in a normal
(other than test) mode when the power supply to the PC CPU goes ON or the
PC CPU is reset.
The signal goes OFF when the test terminals on the front panel are shorted.
This signal can be used as an interlock for buffer memory read/write operations.
REMARK
Definition of A-D conversion-ready status:
channels and the digital output values are stored in buffer memory.
IMPORTANT
A FROM/TO instruction cannot be executed in the test mode. Use the D/A
conversion ready signal (X1) as an interlock for any program that contains a
FROM/TO instruction.
If a FROM/TO instruction is executed in the test mode, the preset offset and/or
gain value might be lost, or a CPU error may occur causing the calculation to
stop.
(3) Error flag (X2)
The X2 signal goes ON when an error (other than a watchdog timer error) is
detected by the A68ADN. When the X2 signal is turned ON, an error code is
stored in the error code storage area in buffer memory.
The signal goes OFF when the error reset signal (Y12) is turned ON.
(4) Error reset (Y12)
Turning Y12 ON causes the error flag (X2) to go OFF and writes "0" to the error
code storing area (address 18H) in buffer memory, after clearing the error code
stored there.
The RUN LED, which flashes on the front panel after an error is detected, stops
flashing when the Y12 signal is turned ON (which indicates "normal operation").
Error flag (X2)
Error reset (Y12)
Buffer memory
address 18H
When A-D conversion is completed in all eight
Error code
0
0
3 − 12
MELSEC-A
The system is turned
ON/OFF
To be turned ON/OFF
by the user program

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