Figure 156. Control Circuit In Normal Mode, Internal Clock Divided By 1; Figure 157. Ti2 External Clock Connection Example - ST STM32F101xx Reference Manual

General-purpose timers (TIM9 to TIM14)

Figure 156. Control circuit in normal mode, internal clock divided by 1

External clock source mode 1(
This mode is selected when SMS='111' in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.

Figure 157. TI2 external clock connection example

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = '01' in
the TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F='0000').
3. Select the rising edge polarity by writing CC2P='0' and CC2NP='0' in the TIMx_CCER
register.
4. Configure the timer in external clock mode 1 by writing SMS='111' in the TIMx_SMCR
register.
5. Select TI2 as the trigger input source by writing TS='110' in the TIMx_SMCR register.
6. Enable the counter by writing CEN='1' in the TIMx_CR1 register.
Note: The capture prescaler is not used for triggering, so you don't need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
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Internal clock
CEN=CNT_EN
CNT_INIT
Counter clock = CK_CNT = CK_PSC
Counter register
TI2F_Rising
TI2 Edge
Filter
Detector
TI2F_Falling
ICF[3:0]
TIMx_CCMR1
Doc ID 13902 Rev 12
UG
31 32 33 34 35 36
TIM9 and TIM12)
TIMx_SMCR
TS[2:0]
TI2F
or
TI1F
ITRx
0xx
TI1_ED
100
TRGI
TI1FP1
101
0
TI2FP2
110
1
CK_INT
(internal clock)
CC2P
TIMx_CCER
00 01 02 03 04 05 06 07
or
or
external clock
mode 1
CK_PSC
internal clock
mode
SMS[2:0]
TIMx_SMCR
RM0008