Texas Instruments TMS320C2x User Manual page 87

System Control
When an RS signal is received, the following actions take place:
1) RAM configuration bits are set so that all on-chip RAM resides in data
2) The program counter (PC) is set to 0, and the address bus A15–A0 is driv-
3) The data bus D15–D0 is placed in the high-impedance state.
4) All memory and I/O space control signals (PS, DS, IS, R/W, STRB, and
5) All interrupts are disabled by setting the INTM (interrupt mode) bit to 1.
6) Status bits are set:
7) The global memory allocation register (GREG) is cleared to make all
8) The RPTC (repeat counter) is cleared.
9) The DX (data transmit) pin is placed in the high-impedance state. Any
10) The TIM register is set to the maximum value (0FFFFh) on reset. Also, the
11) The IACK (interrupt acknowledge) signal is generated in the same manner
12) The state of the RAM is undefined following RS.
13) The ARB, ARP, DP, IMR, OVM, and TC bits are not initialized by reset.
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space.
en with all zeros while RS is low.
BR) are deasserted by setting them to high levels while RS is low.
(Note that RS is nonmaskable.) The interrupt flag register (IFR) is reset to
all zeros.
For all TMS320C2x devices, 0
0 CNF (0 CNF0, 0 CNF1 for the TMS320C26), 1
1 HM, 1 C, and 1
TMS320C2x are unchanged.
memory local.
transmit/receive operations on the serial port are terminated, and the TXM
(transmit mode) bit is reset to a low level. This configures the FSX framing
pulse to be an input. A transmit/receive operation may be started by fram-
ing pulses only after the removal of RS.
PRD register on the TMS320C25 is initialized by reset to 0FFFFh. (See
Example 5–1). The TIM register begins decrementing only after RS is
deasserted.
as a maskable interrupt.
Therefore, it is critical that you initialize these bits in software following re-
set.
OV, 1 XF, 0 FO, 0
FSM. The remaining status bits on the
TXM,
SXM, 0 PM,
Architecture