Texas Instruments TMS320C2x User Manual page 342

5.2.3 Timer Operation
The TMS320C2x 16-bit on-chip timer and its associated interrupt perform vari-
ous functions at regular time intervals. On the TMS320C25, the timer is a down
counter that is continuously clocked by CLKOUT1 and counts (PRD + 1)
cycles of CLKOUT1. By programming the period (PRD) register from 1 to
65,535 (0FFFFh), a timer interrupt (TINT) can be generated every 2 to 65,536
cycles. (A period register value of zero is not allowed.)
Two memory-mapped registers operate the timer. The timer (TIM) register,
data memory location 2, holds the current count of the timer. At every
CLKOUT1 cycle, the TIM register is decremented by one. The PRD register,
data memory location 3, holds the starting count for the timer. When the TIM
register decrements to zero, a timer interrupt (TINT) is generated. In the follow-
ing cycle, the contents of the PRD register are loaded into the TIM register. In
this way, a TINT is generated every (PRD + 1) cycles of CLKOUT1 on the
TMS320C25.
You can read from or write to the timer and period registers on any cycle. You
can monitor the count by reading the TIM register and write a new counter peri-
od to the PRD register without disturbing the current timer count. The timer will
then start the new period after the current count is complete. If both the PRD
and TIM registers are loaded with a new period, the timer begins decrementing
the new period without generating an interrupt. Thus, you have complete con-
trol of the current and next periods of the timer.
For the TMS320C25, the TIM register is set to the maximum value on reset
(0FFFFh), and the PRD register is also initialized by reset to 0FFFFh. The TIM
register begins decrementing only after RS is deasserted. If the timer is not
used, TINT should be masked. The PRD register can then be used as a gener-
al-purpose data memory location. If you use TINT, you should program the
PRD and TIM registers before unmasking the TINT.
Example 5–8 shows the assembly code that implements the timer to divide
down the CLKOUT1 signal. To generate a 9600-Hz clock signal, load the PRD
register with 520. In the timer interrupt service routine, the XF line is toggled.
The XF output is used also as an input for BIO in this example. The output of
XF will provide a 50-percent duty cycle clock signal as long as the main routine
or other interrupt routines do not disable interrupts. Interrupts may be disabled
by direct or implied use of DINT or by executing instructions in the repeat
mode. The value for the PRD register is calculated as follows:
TMS320C25:
CLKOUT1/(PRD + 1) = 2
10 MHz/(520 + 1) = 2 9600 Hz (= 9597 Hz for divided signal)
Program Control
frequency of signal
5-25