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Texas Instruments TMS320C28x Reference Manual

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TMS320C28x DSP

CPU and Instruction Set

Reference Guide

Literature Number: SPRU430D

August 2001 − Revised March 2004

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Summary of Contents for Texas Instruments TMS320C28x

Page 1 TMS320C28x DSP CPU and Instruction Set Reference Guide Literature Number: SPRU430D August 2001 − Revised March 2004...
Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
Page 3: Architectural Overview
About This Manual This manual describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x 32-bit fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. A summary of the chapters and appendixes follows:...
Page 4 Notational Conventions About This Manual / Notational Conventions Chapter 7 Emulation Features This chapter describes the TMS320C28x emulation features that can be used with only a JTAG port and two additional emulation pins. Appendix A Register Quick Reference This appendix is a concise central resource for information about the status and control registers of the CPU.
Page 5 Notational Conventions value from 0 to 5; where the 6bit appears, you type a 6-bit constant. The rest of the instruction, including the square brackets, must be entered as shown. When braces or brackets enclose an operand, as in {operand}, the oper- and is optional.
Page 6 DSP (in which case, the polarity is irrelevant), the name of the signal is left unqualified (for example, DLOGINT). Related Documentation From Texas Instruments The following books describe the TMS320C28x DSP and related support tools. The documents are available for downloading on the Texas Instruments website (www.ti.com).
Page 7 TMS320C28x Boot ROM Reference Guide (literature number SPRU095) describes the purpose and features of the bootloader (factory-pro- grammed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is lo- cated within that memory.
Page 8 Intel is a trademark of Intel Corporation. MS-DOS is a registered trademark of Microsoft Corporation. is a registered trademark of Advanced Micro Devices, Inc.  SunOS is a trademark of Sun Microsystems, Inc. C2xLP, C27x, C28x, TMS320C28x, and XDS510 are trademarks of Texas Instruments Incorporated. viii...
Page 9: Table Of Contents
............Describes the registers and primary functions of the TMS320C28x CPU.
Page 10 ............Describes the TMS320C28x interrupts and how they are handled by the CPU. Also explains the effects of a hardware reset.
Page 11 Contents Addressing Modes Select Bit (AMODE) ........Assembler/Compiler Tracking of AMODE Bit .
Page 12 ............Is a concise, central resource for information about the status and control registers of the TMS320C28x CPU. Reset Values of and Instructions for Accessing the Registers .
Page 13 Contents F.1.2 Full Context Save and Restore ........F.1.3 B0/B1 Memory Map Consideration .
Page 14 1−2. TMS320C28x High-Level Memory Map ......... .
Page 15 Figures A−5. Interrupt enable register (IER) ..........A−6.
Page 16 Tables Tables 1−1. Compatibility Modes ............1−2.
Page 17 Tables D−1. Code to Save Contents Of IMR (IER) And Disabling Lower Priority Interrupts At Beginning Of ISR ............. D−2.
Page 18 Examples Examples 3−1. Typical ISR ..............3-16 4−1.
Page 19 Chapter 1 Architectural Overview The TMS320C28xt is one of several fixed-point generations of digital signal processors (DSPs) in the TMS320 family. The C28xt is source-code and ob- ject-code compatible with the C27xt. In addition, much of the code written for the C2xLP CPU can be reassembled to run on a C28x device.
Page 20: 1.1 Introduction To The Cpu
Introduction to the CPU 1.1 Introduction to the CPU The CPU is a low-cost 32-bit fixed-point digital signal processor (DSP). This device draws from the best features of digital signal processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
Page 21: Switching To C28X Mode From Reset
Introduction to the CPU the C28x code-generation tools. For more information on operating in this mode and migration from a C2xLP CPU, see Appendices C, D, and E. C27x Object-Compatible Mode: At reset, the C28x CPU operates in C27x object-compatible mode. In this mode, the C28x is 100% object-code and cycle-count compatible with the C27x CPU.
Page 22: 1.2 Components Of The Cpu
Components of the CPU 1.2 Components of the CPU As shown in Figure 1−1, the CPU contains: A CPU for generating data- and program-memory addresses; decoding and executing instructions; performing arithmetic, logical, and shift opera- tions; and controlling data transfers among CPU registers, data memory, and program memory Emulation logic for monitoring and controlling various parts and functiona- lities of the DSP and for testing device operation...
Page 23: Emulation Logic
Components of the CPU registers, math registers, and data pointers. The system-control registers are accessed by special instructions. The other registers are accessed by special instructions or by a special addressing mode (register addressing mode). Arithmetic logic unit (ALU). The 32-bit ALU performs 2s-complement arith- metic and Boolean logic operations.
Page 24: Signals
Components of the CPU 1.2.3 Signals The CPU has four main types of signals: Memory-interface signals. These signals transfer data among the CPU, memory, and peripherals; indicate program-memory accesses and data- memory accesses; and differentiate between accesses of different sizes (16-bit or 32-bit).
Page 25: 1.3 Memory Map
Memory Map 1.3 Memory Map The CPU contains no memory, but can access memory elsewhere on the C28x DSP or outside the DSP. The C28x uses 32-bit data addresses and 22-bit program addresses. This al- lows for a total address reach of 4G words (1 word = 16 bits) in data space and 4M words in program space.
Page 26: Tms320C28X High-Level Memory Map
Memory Map Figure 1−2. TMS320C28x High-Level Memory Map Program Data 0000 Vectors in RAM M0 Vectors in RAM M0 (VMAP = 0) (VMAP = 0) Block M0 1 K × 16 Block M0 1 K × 16 <−SP (Reset) Low 64K Block M1 1 K ×...
Page 27: 1.4 Memory Interface
Memory Interface 1.4 Memory Interface The C28x memory map is accessible outside the CPU by the memory inter- face, which connects the CPU logic to memories, peripherals, or other inter- faces. The memory interface includes separate buses for program space and data space.
Page 28: Special Bus Operations
Memory Interface Table 1−2 summarizes how these buses are used during accesses. Table 1−2. Summary of Bus Use During Data-Space and Program-Space Accesses Access Type Address Bus Data Bus Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 29: Special Bus Operations
Memory Interface Table 1−3. Special Bus Operations Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Instruction Special Bus Operation Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 30 1-12...
Page 31: Central Processing Unit
Chapter 2 Central Processing Unit The central processing unit (CPU) is responsible for controlling the flow of a program and the processing of instructions. It performs arithmetic, Boolean- logic, multiply, and shift operations. When performing signed math, the CPU uses 2s-complement notation. This chapter describes the architecture, regis- ters, and primary functions of the CPU.
Page 32: 2.1 Cpu Architecture
CPU Architecture 2.1 CPU Architecture All C28x devices contain a central processing unit (CPU), emulation logic, and signals for interfacing with memory and peripherals. Included with these sig- nals are three address buses and three data buses. Figure 2−1 shows the ma- jor blocks and data paths of the C28x CPU.
Page 33: Conceptual Block Diagram Of The Cpu
CPU Architecture Figure 2−1. Conceptual Block Diagram of the CPU Program-read data bus, PRDB(0:31) Program address bus, PAB(0:21) Data-read address bus, DRAB(0:31) Program control Program-address logic generation logic Data-read data bus, DRDB(0:31) Data-read buffer register Address from stack Immediate address Operand bus XAR7 Immediate...
Page 34: 2.2 Cpu Registers
CPU Registers 2.2 CPU Registers Table 2−1 lists the main CPU registers and their values after reset. Sections 2.2.1 through 2.2.10 describe the registers in more detail. Figure 2−2 shows the registers. Table 2−1. CPU Register Summary Register Size Description Value After Reset 32 bits Accumulator...
Page 35 CPU Registers Table 2−1. CPU Register Summary (Continued) Register Size Description Value After Reset 16 bits Data-page pointer 0x0000 16 bits Interrupt flag register 0x0000 16 bits Interrupt enable register 0x0000 (INT1 to INT14, DLOGINT, RTOSINT disabled) DBGIER 16 bits Debug interrupt enable 0x0000 (INT1 to INT14, DLOGINT, register...
Page 36: Accumulator (Acc, Ah, Al)
CPU Registers Figure 2−2. C28x Registers T[16] TL[16] XT[32] PH[16] PL[16] P[32] AH[16] AL[16] ACC[32] SP[16] 6/7-bit DP[16] offset † AR0[16] XAR0[32] AR0H[16] AR1H[16] AR1[16] XAR1[32] AR2H[16] XAR2[32] AR2[16] XAR3[32] AR3H[16] AR3[16] AR4H[16] XAR4[32] AR4[16] AR5H[16] XAR5[32] AR5[16] AR6[16] XAR6[32] AR6H[16] AR7H[16] AR7[16]...
Page 37: Individually Accessible Portions Of The Accumulator
CPU Registers compare operations from 32-bit-wide data memory. It can also accept the 32-bit result of a multiplication operation. The halves and quarters of the ACC can also be accessed (see Figure 2−3). ACC can be treated as two independent 16-bit registers: AH (high 16 bits) and AL (low 16 bits).
Page 38: Multiplicand Register (Xt)
CPU Registers Table 2−2. Available Operations for Shifting Values in the Accumulator Register Shift Direction Shift Type Instruction Left Logical LSL or LSLL Rotation Right Arithmetic SFR with SXM = 1 or ASRL Logical SFR with SXM = 0 or LSRL Rotation AH or AL Left...
Page 39: Product Register (P, Ph, Pl)
CPU Registers Figure 2−4. Individually Accessible Halves of the XT Register T = XT(16:31) TL = XT(15:0) 2.2.3 Product Register (P, PH, PL) The product register (P register) is typically used to hold the 32-bit result of a multiplication. It can also be loaded directly from a 16- or 32-bit data-memory location, a 16-bit constant, the 32-bit ACC, or a 16-bit or a 32-bit addressable CPU register.
Page 40: Data Page Pointer (Dp)
CPU Registers Table 2−3. Product Shift Modes PM Value Product Shift Mode Left shift by 1 No shift Right shift by 1 Right shift by 2 Right shift by 3 Right shift by 4 (if AMODE = 1, left 4) Right shift by 5 Right shift by 6 2.2.4...
Page 41: Stack Pointer (Sp)
CPU Registers Figure 2−6. Pages of Data Memory Data page Offset Data memory 00 0000 0000 0000 00 00 0000 Page 0: 0000 0000−0000 003F 00 0000 0000 0000 00 11 1111 00 0000 0000 0000 01 00 0000 Page 1: 0000 0040−0000 007F 00 0000 0000 0000 01 11 1111...
Page 42: Auxiliary Registers (Xar0−Xar7, Ar0−Ar7)
CPU Registers Figure 2−7. Address Reach of the Stack Pointer Data memory Range accessible 0000 0000−0000 FFFF by way of SP Range not accessible 0001 0000−FFFF FFFF by way of SP The operation of the stack is as follows: The stack grows from low memory to high memory. The SP always points to the next empty location in the stack.
Page 43: Xar0 − Xar7 Registers
CPU Registers Modes, on page 5-10 . The auxiliary registers are: XAR0, XAR1, XAR2, XAR3, XAR4, XAR5, XAR6, and XAR7. Many instructions allow you to access the 16 LSBs of XAR0−XAR7. As shown in Figure 2−8, the 16 LSBs of the auxiliary registers are referred to as AR0−AR7.
Page 44: Program Counter (Pc)
CPU Registers 2.2.7 Program Counter (PC) When the pipeline is full, the 22-bit program counter (PC) always points to the instruction that is currently being processed — the instruction that has just reached the decode 2 phase of the pipeline. Once an instruction reaches this phase of the pipeline, it cannot be flushed from the pipeline by an interrupt.
Page 45 CPU Registers software, the corresponding interrupt will be serviced if it is enabled. You en- able or disable a maskable interrupt with its corresponding bit in the IER. The DBGIER indicates the time-critical interrupts that will be serviced (if enabled) while the DSP is in real-time emulation mode and the CPU is halted.
Page 46: Status Register (St0)
Status Register (ST0) 2.3 Status Register (ST0) The following figure shows the bit fields of status register (ST0). All of these bit fields are modified in the execute phase of the pipeline. Detailed descrip- tions of these bits follow the figure. Figure 2−10.
Page 47: Instructions That Affect Ovc/Ovcu
Status Register (ST0) Table 2−4. Instructions That Affect OVC/OVCU Signed Addition Instructions Effect on OVC/OVCU ACC,loc16 << shift if(OVM == 0) Inc OVC on +ve signed overflow ACC,#16bit << shift ACC,loc16 << T loc16,#16bitSigned ADDB ACC,#8bit ADDCL ACC,loc32 ADDCU ACC,loc16 ADDL ACC,loc32 ADDL loc32,ACC ADDU ACC,loc16...
Page 48 Status Register (ST0) Table 2−4. Instructions That Affect OVC/OVCU (Continued) Signed Addition Instructions Effect on OVC/OVCU MPYS P,T,loc16 QMPYSL P,XT,loc32 SBBU ACC,loc16 SQRS loc16 ACC,#16bit << shift ACC,loc16 << shift ACC,loc16 << T SUBB ACC,#8bit SUBBL ACC,loc32 SUBL ACC,loc32 SUBL loc32,ACC SUBRL loc32,ACC SUBU ACC,loc16 SUBUL ACC,loc32...
Page 49 Status Register (ST0) Table 2−4. Instructions That Affect OVC/OVCU (Continued) Signed Addition Instructions Effect on OVC/OVCU MOVU OVC,loc16 OVC = [loc16(5:0)] Condition Operation Performed by SAT ACC Instruction OVC = 0 Leave ACC and OVC unchanged. OVC > 0 Saturate ACC in the positive direction (fill ACC with 7FFF FFFF ), and clear OVC.
Page 50: Instructions Affected By The Pm Bits
Status Register (ST0) Table 2−5. Instructions Affected by the PM Bits Instruction Effect of PM CMPL ACC,P << PM flags set on(ACC − P << PM) DMAC ACC:P,loc32,*XAR7/++ ACC = ACC + MSW*MSW << PM P = P + LSW*LSW << PM IMACL P,loc32,*XAR7/++ P = ([loc32] * Prog[*XAR7/++]) <<...
Page 51: Instructions Affected By V Flag
Status Register (ST0) Overflow flag. If the result of an operation causes an overflow in the register holding the result, V is set and latched. If no overflow occurs, V is not modified. Once V is latched, it Bit 6 remains set until it is cleared by reset or by a conditional branch instruction that tests V.
Page 52 Status Register (ST0) Table 2−6. Instructions Affected by V flag (Continued) Instruction Description ADDUL P,loc32 V = 1 on signed overflow 16bitOff,COND V = 0 if tested 16bitOff,COND V = 0 if tested loc16 V = 1 on signed overflow DMAC ACC:P,loc32,*XAR7/++ V = 1 on signed overflow IMACL P,loc32,*XAR7/++...
Page 53 Status Register (ST0) Table 2−6. Instructions Affected by V flag (Continued) Instruction Description NEGTC ACC if(TC == 1) if(ACC == 0x8000 0000) V = 1 QMACL P,loc32,*XAR7/++ V = 1 on signed overflow QMPYAL P,XT,loc32 V = 1 on signed overflow QMPYSL P,XT,loc32 V = 1 on signed overflow if(OVC == 0) V = 0 else V = 1...
Page 54: Negative Flag Under Overflow Conditions
Status Register (ST0) Table 2−6. Instructions Affected by V flag (Continued) Instruction Description XMACD P,loc16,*(pma) V = 1 on signed overflow XRETC COND V = 0 if tested Negative flag. During certain operations, N is set if the result of the operation is a negative number or cleared if the result is a positive number.
Page 55: Bits Affected By The C Bit
Status Register (ST0) Zero flag. Z is set if the result of certain operations is 0 or is cleared if the result is nonzero. This applies to results that are loaded into ACC, AH, AL, another register, or a data-memory Bit 4 location.
Page 56 Status Register (ST0) Table 2−8. Bits Affected by the C Bit (Continued) Instruction Affect of or Affect on C ACC,loc16 << T C = 1 on carry else C = 0 AX,loc16 C = 1 on carry else C = 0 loc16,#16bitSigned C = 1 on carry else C = 0 loc16,AX...
Page 57 Status Register (ST0) Table 2−8. Bits Affected by the C Bit (Continued) Instruction Affect of or Affect on C loc16,#16bitSigned for([loc16] − 16bitSigned) C = 0 on borrow else C = 1 CMPB AX,#8bit C = 0 on borrow else C = 1 CMPL ACC,loc32 for(ACC −...
Page 58 Status Register (ST0) Table 2−8. Bits Affected by the C Bit (Continued) Instruction Affect of or Affect on C LSR64 ACC:P,T if(T == 0) C = 0 else C = P(bit(T−1)) LSRL ACC,T if(T == 0) C = 0 else C = ACC(bit(T−1)) P,loc16,*XAR7/++ C = 1 on carry else C = 0 P,loc16,0:pma...
Page 59 Status Register (ST0) Table 2−8. Bits Affected by the C Bit (Continued) Instruction Affect of or Affect on C NEGTC ACC if(TC == 1) if( ACC == 0) C = 1 else C = 0 QMACL P,loc32,*XAR7/++ C = 1 on carry else C = 0 QMPYAL P,XT,loc32 C = 1 on carry else C = 0 QMPYSL P,XT,loc32...
Page 60 Status Register (ST0) Table 2−8. Bits Affected by the C Bit (Continued) Instruction Affect of or Affect on C SUBBL ACC,loc32 ACC = ACC − ([loc32] + ~C) C = 0 on borrow else C = 1 SUBCU ACC,loc16 for(ACC − [loc16]<<15) C = 0 on borrow else C = 1 SUBCUL ACC,loc32 for(ACC<<1 + P(31) −...
Page 61: Instructions That Affect The Tc Bit
Status Register (ST0) Table 2−9. Instructions That Affect the TC Bit Instruction Affect on the TC bit ABSTC ACC if( ACC < 0 ) TC = TC ^ 1 16bitOff,COND TC bit used as test condition 16bitOff,COND TC bit used as test condition CLRC TC TC = 0 CMPR...
Page 62 Status Register (ST0) Overflow mode bit. When ACC accepts the result of an addition or subtraction and the result causes an overflow, OVM determines how the CPU handles the overflow as fol- Bit 1 lows:. Results overflow normally in ACC. The OVC reflects the overflow (see the de- scription for the OVC on page 2-16) ACC is filled with either its most positive or most negative value as follows: If ACC overflows in the positive direction (from 7FFF FFFF...
Page 63: Instructions Affected By Sxm
Status Register (ST0) Table 2−10. Instructions Affected by SXM Instruction Description ACC,#16bit << shift Affected By SXM ACC,loc16 << shift Affected By SXM ACC,loc16 << T Affected By SXM CLRC SXM SXM = 0 ACC,#16bit << shift Affected By SXM ACC,loc16 <<...
Page 64: 2.4 Status Register St1
Status Register ST1 2.4 Status Register ST1 The following figure shows the bit fields of status register ST1. All of these bit fields are modified in the decode 2 phase of the pipeline. Detailed descriptions of these bits follow the figure. Figure 2−11.Bit Fields of Status Register 1 (ST1) Reserved AMODE...
Page 65 Status Register ST1 Reserved Reserved. This bit is reserved. Writes to this bit have no effect. Bit 10 OBJMODE Object compatibility mode bit. This mode is used to select between C27x object mode (OBJMODE == 0) and C28x object mode (OBJMODE == 1) compatibility. This bit Bit 9 is set by the ”C28OBJ”...
Page 66 Status Register ST1 When the CPU services an interrupt, the current value of LOOP is saved on the stack (when ST1 is saved on the stack), and then LOOP is cleared. Upon return from the in- terrupt, LOOP is not restored from the stack. Stack pointer alignment bit.
Page 67 Status Register ST1 DBGM Debug enable mask bit. When DBGM is set, the emulator cannot accesss memory or registers in real time. The debugger cannot update its windows. Bit 1 In the real-time emulation mode, if DBGM = 1, the CPU ignores halt requests or hard- ware breakpoints until DBGM is cleared.
Page 68 Status Register ST1 When the CPU services an interrupt, the current value of INTM is saved on the stack (when ST1 is saved on the stack), and then INTM is set. Upon return from the interrupt, INTM is restored from the stack. This bit can be individually set and cleared by the SETC INTM instruction and CLRC INTM instruction, respectively.
Page 69: 2.5 Program Flow
Program Flow 2.5 Program Flow The program control logic and program-address generation logic work togeth- er to provide proper program flow. Normally, the flow of a program is sequen- tial: the CPU executes instructions at consecutive program-memory address- es. At times, a discontinuity is required; that is, a program must branch to a nonsequential address and then execute instructions sequentially at that new location.
Page 70: Instruction Pipeline
Program Flow 2.5.4 Instruction Pipeline Each instruction passes through eight independent phases that form an instruction pipeline. At any given time, up to eight instructions may be active, each in a different phase of completion. Not all reads and writes happen in the same phases, but a pipeline-protection mechanism stalls instructions as needed to ensure that reads and writes to the same location happen in the or- der in which they are programmed.
Page 71: Multiply Operations
Multiply Operations 2.6 Multiply Operations The C28x features a hardware multiplier that can perform 16-bit X 16-bit or 32-bit X 32-bit fixed-point multiplication. This functionality is enhanced by 16-bit X 16-bit multiply and accumulate (MAC), 32 X 32 MAC, and 16-bit X 16-bit dual MAC (DMAC) instructions.
Page 72: Conceptual Diagram Of Components Involved In 16 X16-Bit Multiplication
Multiply Operations Figure 2−12. Conceptual Diagram of Components Involved in 16 X16-Bit Multiplication From data memory or a register From data memory or a register From an instruction opcode Multiplier 2.6.2 32-Bit X 32-Bit Multiplication The C28x multiplier can also perform 32-bit by 32-bit multiplication. Figure 2−13 shows the CPU components involved n this multiplication.
Page 73: Conceptual Diagram Of Components Involved In 32 X 32-Bit Multiplication
Multiply Operations If you need support for larger data values, the 32 X 32 multiplication instruc- tions can be combined to implement 32 X 32 = 64-bit or 64 X 64 = 128-bit math. Figure 2−13. Conceptual Diagram of Components Involved in 32 X 32-Bit Multiplication From data memory or register From...
Page 74: Shift Operations
Shift Operations 2.7 Shift Operations The shifter holds 64 bits and accepts either a 16-bit, 32-bit, or 64-bit input value. When the input value has 16 bits, the value is loaded into the 16 least significant bits (LSBs) of the shifter. When the input value has 32 bits, the value is loaded into the 32 LSBs of the shifter.
Page 75: Shift Operations
Shift Operations Table 2−11. Shift Operations Operation Type Illustration Left shift of 16-bit value for ACC 16-bit value to 16 LSBs operation. Syntaxes: ADD ACC, loc16 <<0...16 Shift left 0/Sign ADD ACC, #16Bit <<0...15 ADD ACC, loc16 <<T 32 bits to ALU SUB ACC, loc16 <<...
Page 76 Shift Operations Table 2−11. Shift Operations (Continued) Operation Type Illustration AH/AL to 16 LSBs Logical left shift of AH or AL. The last Last bit to be shifted out fills the carry bit (C). bit out Syntaxes: Shift left LSL AX, 1...16 LSL AX, T (shift = T(3:0)) Note: If T(3:0) = 0, indicating a shift of 0, 16 LSBs to AH/AL...
Page 77 Shift Operations Table 2−11. Shift Operations (Continued) Operation Type Illustration Rotate ACC right by 1 bit. Bit 0 of ACC fills the carry bit (C). C fills bit 31 of ACC. Syntax: Rotate right 32 bits to ACC Logical right shift of ACC:P. ACC:P Syntaxes: Last...
Page 78 Shift Operations Table 2−11. Shift Operations (Continued) Operation Type Illustration Shift of P as per PM bits. Syntaxes: For PM = 0: ADD ACC, P SUB ACC, P Shift left Discard CMP ACC, P MAC P, loc, 0:pmem 32 bits to ALU MOV ACC, P For PM = 1: No shift MOVA T, loc...
Page 79 Shift Operations Table 2−11. Shift Operations (Continued) Operation Type Illustration Store 16 LSBs of shifted P. P is shifted For PM = 0: as per the PM bits. The 16 LSBs of shifter are stored. Syntax: Shift left Discard MOV loc16, P 16 LSBs to ALU For PM = 1: No shift For PM from 2−7:...
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Page 81: Cpu Interrupts And Reset
Chapter 3 CPU Interrupts and Reset This chapter describes the available CPU interrupts and how they are handled by the CPU. It also explains how to control those interrupts that can be con- trolled through software. Finally, it describes how a hardware reset affects the CPU.
Page 82: Cpu Interrupts Overview
CPU Interrupts Overview 3.1 CPU Interrupts Overview Interrupts are hardware- or software-driven signals that cause the C28x CPU to suspend its current program sequence and execute a subroutine. Typically, interrupts are generated by peripherals or hardware devices that need to give data to or take data from the C28x (for example, A/D and D/A converters and other processors).
Page 83 CPU Interrupts Overview Fetch the interrupt vector and load it into the program counter (PC). For devices with a PIE module, the vector fetched will depend on the setting of the PIE enable and flag registers. 4) Execute the interrupt service routine. The C28x branches to its corre- sponding subroutine called an interrupt service routine (ISR).
Page 84: Cpu Interrupt Vectors And Priorities
CPU Interrupt Vectors and Priorities 3.2 CPU Interrupt Vectors and Priorities The C28x supports 32 CPU interrupt vectors, including the reset vector. Each vector is a 22-bit address that is the start address for the corresponding inter- rupt service routine (ISR). Each vector is stored in 32 bits at two consecutive addresses.
Page 85: Interrupt Vectors And Priorities
CPU Interrupt Vectors and Priorities Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Table 3−1. Interrupt Vectors and Priorities (Continued) Á...
Page 86: Maskable Interrupts: Int1−Int14, Dlogint, And Rtosint
Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT 3.3 Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT INT1−INT14 are 14 general-purpose interrupts. DLOGINT (the data log inter- rupt) and RTOSINT (the real-time operating system interrupt) are available for emulation purposes. These interrupts are supported by three dedicated regis- ters: the CPU interrupt flag register (IFR), the CPU interrupt enable register (IER), and the CPU debug interrupt enable register (DBGIER).
Page 87: Interrupt Flag Register (Ifr)
Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT Once an interrupt has been requested and properly enabled, the CPU pre- pares for and then executes the corresponding interrupt service routine. For a detailed description of this process, see section 3.4. Table 3−2. Requirements for Enabling a Maskable Interrupt Interrupt-Handling Process Interrupt Enabled If ...
Page 88: Cpu Interrupt Enable Register (Ier) And Cpu Debug Interrupt Enable Register (Dbgier)
Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT Bits 15 and 14 of the IFR correspond to the interrupts RTOSINT and DLOGINT: RTOSINT Real-time operating system interrupt flag Bit 15 RTOSINT = 0 RTOSINT is not pending. RTOSINT = 1 RTOSINT is pending. DLOGINT Data log interrupt flag Bit 14...
Page 89: Interrupt Enable Register (Ier)
Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT Figure 3−2. Interrupt Enable Register (IER) Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 90 Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT As with the IER, you can read the DBGIER to identify enabled or disabled inter- rupts and write to the DBGIER to enable or disable interrupts. To enable an interrupt, set its corresponding bit to 1. To disable an interrupt, set its corre- sponding bit to 0.
Page 91: Standard Operation For Maskable Interrupts
Standard Operation for Maskable Interrupts 3.4 Standard Operation for Maskable Interrupts The flow chart in Figure 3−4 shows the standard process for handling inter- rupts. Section 7.4.2 on page 7-9 contains information on handling interrupts when the DSP is in real-time mode and the CPU is halted. When more than one interrupt is requested at the same time, the C28x services them one after another according to their set priority ranking.
Page 92: Standard Operation For Cpu Maskable Interrupts
Standard Operation for Maskable Interrupts Figure 3−4. Standard Operation for CPU Maskable Interrupts Interrupt request sent to CPU Set corresponding IFR flag bit. Interrupt enabled in IER? Interrupt enabled by INTM bit? Clear corresponding IFR bit. Empty pipeline. Increment and temporarily store PC. Fetch interrupt vector.
Page 93 Standard Operation for Maskable Interrupts What following list explains the steps shown in Figure 3−4: 1) Interrupt request sent to CPU. One of the following events occurs: One of the pins INT1−INT14 is driven low by an external event, periph- eral or PIE interrupt request..
Page 94: Register Pairs Saved And Sp Positions For Context Saves
Standard Operation for Maskable Interrupts 7) Fetch interrupt vector. The PC is filled with the address of the appropri- ate interrupt vector, and the vector is fetched from that location. To determine which vector address has been assigned to each of the inter- rupts, see section 3.2, Interrupt Vectors, on page 3-4 or, if your device uses a PIE module, see the System and Interrupts Reference Guide for your specific device.
Page 95: Register Pairs Saved And Sp Positions For Context Saves
Standard Operation for Maskable Interrupts Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Table 3−3. Register Pairs Saved and SP Positions for Context Saves (Continued) Á...
Page 96: Typical Isr
Standard Operation for Maskable Interrupts If you want the ISR to inform a peripheral that the interrupt is being serv- iced, you can use the IACK instruction to send an interrupt acknowledge signal. The IACK instruction accepts a 16-bit constant as an operand. For a detailed description of the IACK instruction, see Chapter 6, C28x As- sembly Language Instructions.
Page 97: Nonmaskable Interrupts
Nonmaskable Interrupts 3.5 Nonmaskable Interrupts Nonmaskable interrupts cannot be blocked by any of the enable bits (the INTM bit, the DBGM bit, and enable bits in the IFR, IER, or DBGIER). The C28x im- mediately approves this type of interrupt and branches to the corresponding interrupt service routine.
Page 98: Functional Flow Chart For An Interrupt Initiated By The Trap Instruction
Nonmaskable Interrupts 3.5.2 TRAP Instruction You can use the TRAP instruction to initiate any interrupt, including one of the user-defined software interrupts (see USER1−USER12 in Table 3−1 on page 3-4). The TRAP instruction refers to one of the 32 interrupts by a number from 0 to 31.
Page 99 Nonmaskable Interrupts The following lists explains the steps shown in Figure 3−5: 1) TRAP instruction fetched. The CPU fetches the TRAP instruction from program memory. The desired interrupt vector has been specified as an operand and is now encoded in the instruction word. At this stage, no other interrupts can be serviced until the CPU begins executing the interrupt ser- vice routine (step 9).
Page 100 Nonmaskable Interrupts Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Table 3−4. Register Pairs Saved and SP Positions for Context Saves Á...
Page 101: Hardware Interrupt Nmi
Nonmaskable Interrupts The CPU clears LOOP, EALLOW, and IDLESTAT so that the ISR operates within a new context. 8) Load PC with fetched vector. The PC is loaded with the interrupt vector that was fetched in step 4. The vector forces program control to the ISR. 9) Execute interrupt service routine.
Page 102: Illegal-Instruction Trap
Illegal-Instruction Trap 3.6 Illegal-Instruction Trap Any one of the following three events causes an illegal-instruction trap: An invalid instruction is decoded (this includes invalid addressing modes). The opcode value 0000 is decoded. This opcode corresponds to the ITRAP0 instruction. The opcode value FFFF is decoded.
Page 103: Registers After Reset
Hardware Reset (RS) 3.7 Hardware Reset (RS) When asserted, the reset input signal (RS) places the CPU into a known state. As part of a hardware reset, all current operations are aborted, the pipeline is flushed, and the CPU registers are reset as shown in Table 3−5. Then the RESET interrupt vector is fetched and the corresponding interrupt service rou- tine is executed.
Page 104 Hardware Reset (RS) Table 3−5. Registers After Reset (Continued) Register Bit(s) Value After Reset Comments 0000 0000 3F FFC0 PC is loaded with the reset interrupt vector at program-space address 00 0000 or 3F FFC0 0000 SP = 0x400 SP points to address 0400.
Page 105 Hardware Reset (RS) Table 3−5. Registers After Reset (Continued) Register Bit(s) Value After Reset Comments ‡ 0: INTM Maskable interrupts are globally disabled. They cannot be serviced unless the C28x is in real-time mode with the CPU halted. 1: DBGM Emulation accesses and events are disabled.
Page 106 Hardware Reset (RS) Table 3−5. Registers After Reset (Continued) Register Bit(s) Value After Reset Comments 12: XF XFS output signal is low 13−15: ARP ARP points to AR0. 0000 0000 Note: The registers listed in this table are introduced in section 2.2, CPU Registers, on page 2-4.
Page 107: Pipeline
Chapter 4 Pipeline This chapter explains the operation of the C28x instruction pipeline. The pipe- line contains hardware that prevents reads and writes at the same register or data-memory location from happening out of order. However, you can in- crease the efficiency of your programs if you take into account the operation of the pipeline.
Page 108: Pipelining Of Instructions
Pipelining of Instructions 4.1 Pipelining of Instructions When executing a program, the C28x CPU performs these basic operations: Fetches instructions from program memory Decodes instructions Reads data values from memory or from CPU registers Executes instructions Writes results to memory or to CPU registers For efficiency, the C28x performs these operations in eight independent phases.
Page 109 Pipelining of Instructions Decode 2 The decode 2 (D2) hardware requests an instruction from the (D2) instruction-fetch queue. The requested instruction is loaded into the instruction register, where decoding is completed. Once an instruction reaches the D2 phase, it runs to completion. In this pipeline phase, the following tasks are performed: If data is to be read from memory, the CPU generates the source address or addresses.
Page 110: Decoupled Pipeline Segments
Pipelining of Instructions Although every instruction passes through the eight phases, not every phase is active for a given instruction. Some instructions complete their operations in the decode 2 phase, others in the execute phase, and still others in the write phase.
Page 111: Address Counters Fc, Ic, And Pc
Pipelining of Instructions (such as a branch or an interrupt) occurs, the queue is emptied. When the instruction at the bottom of the queue reaches its D2 phase, that instruction is passed to the instruction register for further decoding. 4.1.3 Address Counters FC, IC, and PC Three program-address counters are involved in the fetching and execution of instructions:...
Page 112: Relationship Between Pipeline And Address Counters Fc, Ic, And Pc
Pipelining of Instructions Example 4−1. Relationship Between Pipeline and Address Counters FC, IC, and PC Program memory (32 bits wide) Instruction 2 Instruction 1 00 0051 00 0050 Instruction 3 00 0052 00 0053 Instruction 5 Instruction 4 00 0054 00 0055 00 0056 00 0057...
Page 113: Visualizing Pipeline Activity
Visualizing Pipeline Activity 4.2 Visualizing Pipeline Activity Consider Example 4−2, which lists eight instructions, I1−I8, and shows a diagram of the pipeline activity for those instructions. The F1 column shows addresses and the F2 column shows the instruction opcodes read at those addresses.
Page 114: Diagramming Pipeline Activity
Visualizing Pipeline Activity Example 4−2. Diagramming Pipeline Activity Address Opcode Instruction Initial Values 00 0040 F345 DP,#VarA ; DP = page that has VarA. VarA address = 00 0203 00 0041 F346 AL,@VarA ; Move content of VarA to AL. VarA = 1230 00 0042 F347...
Page 115: Simplified Diagram Of Pipeline Activity
Visualizing Pipeline Activity Instruction − Note: The opcodes shown in the F2 and D1 columns were chosen for illustrative purposes; they are not the actual opcodes of the instructions shown. The pipeline activity in Example 4−2 can also be represented by the simplified diagram in Example 4−3.
Page 116: Freezes In Pipeline Activity
Freezes in Pipeline Activity 4.3 Freezes in Pipeline Activity This section describes the two causes for freezes in pipeline activity: Wait states An instruction-not-available condition 4.3.1 Wait States When the CPU requests a read from or write to a memory device or peripheral device, that device may take more time to finish the data transfer than the CPU allots by default.
Page 117 Freezes in Pipeline Activity One time that an instruction-not-available condition will occur is when the first instruction after a discontinuity is at an odd address and has 32 bits. A discontinuity is a break in sequential program flow, generally caused by a branch, a call, a return, or an interrupt.
Page 118: Pipeline Protection
Pipeline Protection 4.4 Pipeline Protection Instructions are being executed in parallel in the pipeline, and different instruc- tions perform modifications to memory and registers during different phases of completion. In an unprotected pipeline, this could lead to pipeline conflicts— reads and writes at the same location happening out of the intended order. However, the C28x pipeline has a mechanism that automatically protects against pipeline conflicts.
Page 119: Protection Against Register Conflicts
Pipeline Protection Example 4−4. Conflict Between a Read From and a Write to Same Memory Location MOV @VarA,AL ; Write AL to data−memory location MOV AH,@VarA ; Read same location, store value in AH Cycle You can reduce or eliminate these types of pipeline-protection cycles if you can take other instructions in your program and insert them between the instruc- tions that conflict.
Page 120: Register Conflict
Pipeline Protection Generally, a register conflict involves one of the address registers: 16-bit auxiliary registers AR0−AR7 32-bit auxiliary registers XAR0−XAR7 16-bit data page pointer (DP) 16-bit stack pointer (SP) Example 4−5 shows a register conflict involving auxiliary register XAR0. The pipeline activity shown is for an unprotected pipeline, and for convenience, the F1−D1 phases are not shown.
Page 121 Pipeline Protection need for pipeline protection. As a general rule, if a read operation occurs within three instructions from a write operation to the same register, the pipeline- protection mechanism adds at least one inactive cycle. Pipeline 4-15...
Page 122: Avoiding Unprotected Operations
Avoiding Unprotected Operations 4.5 Avoiding Unprotected Operations This section describes pipeline conflicts that the pipeline-protection mecha- nism does not protect against. These conflicts are avoidable, and this section offers suggestions for avoiding them. 4.5.1 Unprotected Program-Space Reads and Writes The pipeline protects only register and data-space reads and writes. It does not protect the program-space reads done by the PREAD and MAC instruc- tions or the program-space write done by the PWRITE instruction.
Page 123: Write Followed By Read Protection Mode
Avoiding Unprotected Operations This program causes a misread. The TBIT instruction reads bit 15 (in the R2 phase) before the MOV instruction writes to bit 15 (in the W phase). If the TBIT instruction reads a 1, the code prematurely ends the loop. Because DataA and DataB reference different data-memory locations, the pipeline does not identi- fy this conflict.
Page 124 Avoiding Unprotected Operations Example 1: write protected_area write protected_area write protected_area <− pipe protection (3 cycles) read protected_area Example 2: write protected_area write protected_area write protected_area <− no pipe protection invoked read non_protected_area <− pipe protection (2 cycles) read protected_area read protected_area Example 3: write non_protected_area write non_protected_area...
Page 125: C28X Addressing Modes
Chapter 5 C28x Addressing Modes This chapter describes the addressing modes of the C28x and provides exam- ples. Topic Page Types of Addressing Modes ........Addressing Modes Select Bit (AMODE) .
Page 126: Types Of Addressing Modes
Types of Addressing Modes 5.1 Types of Addressing Modes The C28x CPU supports four basic types of addressing modes: Direct Addressing Mode DP (data page pointer): In this mode, the 16-bit DP register behaves like a fixed page pointer. The instruction supplies a 6-bit or 7-bit offset field, which is concatenated with the value in the DP register.
Page 127 Types of Addressing Modes An example C28x instruction description, which uses the above, would be: AL,loc16 Take the 16-bit contents of AL register, add the contents of 16-bit location specified by the ”loc16” field and store the contents in AL register. ADDL loc32,ACC Take the 32-bit contents of the location pointed to by the ”loc32”...
Page 128: Addressing Modes For "Loc16" Or "Loc32
Addressing Modes Select Bit (AMODE) 5.2 Addressing Modes Select Bit (AMODE) To accommodate various types of addressing modes, an addressing mode bit (AMODE) selects the decoding of the 8-bit field (loc16/loc32). This bit is found in Status Register 1 (ST1). The addressing modes have been broadly classi- fied as follows: AMODE = 0 This is the default mode on reset and is the mode used by the C28x C/C++...
Page 129 Addressing Modes Select Bit (AMODE) Table 5−1. Addressing Modes for “loc16” or “loc32” AMODE = 0 AMODE = 1 8-Bit Decode ”loc16/loc32” Syntax 8-Bit Decode ”loc16/loc32” Syntax C2xLP Indirect Addressing Modes (ARP, XAR0 to XAR7): 1 0 111 000 1 0 111 000 1 0 111 001 1 0 111 001 1 0 111 010...
Page 130 Addressing Modes Select Bit (AMODE) Table 5−1. Addressing Modes for “loc16” or “loc32” AMODE = 0 AMODE = 1 8-Bit Decode ”loc16/loc32” Syntax 8-Bit Decode ”loc16/loc32” Syntax 16-Bit Register Addressing Modes (AR0 to AR7, AH, AL, PH, PL, TH, SP): 1 0 100 AAA @ARn 1 0 100 AAA...
Page 131: Assembler/Compiler Tracking Of Amode Bit
Assembler/Compiler Tracking of AMODE Bit 5.3 Assembler/Compiler Tracking of AMODE Bit The compiler will always assume the addressing mode is set to AMODE = 0 and therefore will only use addressing modes that are valid for AMODE = 0. The assembler can be instructed, via the command line options, to default to either AMODE = 0 or AMODE = 1.
Page 132: Direct Addressing Modes (Dp)
Direct Addressing Modes (DP) 5.4 Direct Addressing Modes (DP) AMODE ”loc16/loc32” Syntax Description @6bit 32bitDataAddr(31:22) = 0 32bitDataAddr(21:6) = DP(15:0) 32bitDataAddr(5:0) = 6bit Note: The 6-bit offset value is concatenated with the 16-bit DP register. The offset value enables 0 to 63 words to be addressed relative to the cur- rent DP register value.
Page 133: Stack Addressing Modes (Sp)
Stack Addressing Modes (SP) 5.5 Stack Addressing Modes (SP) AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:16) = 0x0000 *−SP[6bit] 32bitDataAddr(15:0) = SP − 6bit Note: The 6-bit offset value is subtracted from the current 16-bit SP register val- ue. The offset value enables 0 to 63 words to be addressed relative to the current SP register value.
Page 134: Indirect Addressing Modes
Indirect Addressing Modes 5.6 Indirect Addressing Modes This section includes indirect addressing modes for the 28x and 2xLP devices. It also includes circular indirect addressing modes. 5.6.1 C28x Indirect Addressing Modes (XAR0 to XAR7) AMODE ”loc16/loc32” Syntax Description ARP = n *XARn++ 32bitDataAddr(31:0) = XARn if(loc16), XARn = XARn + 1...
Page 135 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description ARP = n *+XARn[AR0] 32bitDataAddr(31:0) = XARn + AR0 Note: The lower 16-bits of XAR0 are added to the selected 32-bit register. Upper 16-bits of XAR0 are ignored. AR0 is treated as an unsigned 16-bit value. Overflow into the upper 16-bits of XARn can occur.
Page 136: C2Xlp Indirect Addressing Modes (Arp, Xar0 To Xar7)
Indirect Addressing Modes 5.6.2 C2xLP Indirect Addressing Modes (ARP, XAR0 to XAR7) AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR(ARP) Note: The XARn register used is the register pointed to by the current value in the ARP pointer. ARP = 0, points to XAR0, ARP = 1, points to XAR1 and so on.
Page 137 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR(ARP) if(loc16), XAR(ARP) = XAR(ARP) + 1 if(loc32), XAR(ARP) = XAR(ARP) + 2 Example(s): MOVL XAR2,#Array1 ; Load XAR2 with start address of Array1 MOVL XAR3,#Array2 ; Load XAR3 with start address of Array2 @AR0,#N−1 ;...
Page 138 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR(ARP) *−− if(loc16), XAR(ARP) = XAR(ARP) + 1 if(loc32), XAR(ARP) = XAR(ARP) + 2 Example(s): MOVL XAR2,#Array1+(N−1)*2 ; Load XAR2 with end address of Array1 MOVL XAR3,#Array2+(N−1)*2 ; Load XAR3 with end address of Array2 @AR0,#N−1 ;...
Page 139 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR(ARP) *0++ XAR(ARP) = XAR(ARP) + AR0 Note: The lower 16-bits of XAR0 are added to the selected 32-bit register. Upper 16-bits of XAR0 ignored. AR0 is treated as an unsigned 16-bit value. Overflow into the upper 16-bits of XAR(ARP) can occur.
Page 140 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR(ARP) *0−− XAR(ARP) = XAR(ARP) − AR0 Note: The lower 16-bits of XAR0 are subtracted from the selected 32-bit regis- ter. Upper 16-bits of XAR0 ignored. AR0 is treated as an unsigned 16-bit value.
Page 141 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR(ARP) *BR0++ XAR(ARP)(15:0) = AR(ARP) rcadd AR0 XAR(ARP)(31:16) = unchanged Note: The lower 16-bits of XAR0 are reverse carry added (rcadd) to the lower 16-bits of the selected register. Upper 16-bits of XAR0 ignored. Upper 16-bits of the selected register unchanged by the operation.
Page 142 Indirect Addressing Modes MOVL *BR0++,ACC,ARP1 ; Store ACC into location pointed to by XAR3, ; post−increment XAR3 with AR0 reverse carry ; add, set ARP pointer to point to XAR1 XBANZ Loop,*−−,ARP2 ; Loop until AR1 == 0, post−decrement AR1, ;...
Page 143 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR(ARP) *BR0−−,ARPn XAR(ARP)(15:0) = AR(ARP) rbsub AR0 XAR(ARP)(31:16) = unchanged ARP = n Note: The lower 16-bits of XAR0 are reverse borrow subtracted (rbsub) from the lower 16-bits of the selected register. Upper 16-bits of XAR0 ignored. Up- per 16-bits of the selected register unchanged by the operation.
Page 144 Indirect Addressing Modes Reverse carry addition or reverse carry subtraction is used to implement bit− reversed addressing as used in the re−ordering of data elements in FFT algo- rithms. Typically, AR0 is initialized with the (FFT size) /2. The value of AR0 is then added or subtracted, with reverse carry addition or subtraction, to gener- ate the bit reversed address: Reverse Carry Addition Example Is Shown Below (FFT size = 16):...
Page 145: Circular Indirect Addressing Modes (Xar6, Xar1)
Indirect Addressing Modes 5.6.3 Circular Indirect Addressing Modes (XAR6, XAR1) AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR6 *AR6%++ if( XAR6(7:0) == XAR1(7:0) ) XAR6(7:0) = 0x00 XAR6(15:8) = unchanged else if(16-bit data), XAR6(15:0) =+ 1 if(32-bit data), XAR6(15:0) =+ 2 XAR6(31:16) = unchanged ARP = 6 As seen in Figure 5−1, buffer size is determined by the 8 LSBs of AR1 or...
Page 146: Circular Buffer With Amode
Indirect Addressing Modes Figure 5−1. Circular Buffer with AMODE = 0 Buffer size = 8 + 1 = 9 Top of buffer XAR6 X X X X X X Must be zero XAR6[7:0] is incremented until it matches AR1[7:0] Bottom of buffer XAR6 Matches AR1[7:0] Example(s):...
Page 147 Indirect Addressing Modes AMODE ”loc16/loc32” Syntax Description 32bitDataAddr(31:0) = XAR6 + AR1 *+XAR6[AR1%++] if( XAR1(15:0) == XAR1(31:16) ) XAR1(15:0) = 0x0000 else if(16-bit data), XAR1(15:0) =+ 1 if(32-bit data), XAR1(15:0) =+ 2 XAR1(31:16) = unchanged ARP = 6 Note: With this addressing mode, there is no circular buffer alignment require- ments.
Page 148: Circular Buffer With Amode
Indirect Addressing Modes Figure 5−2. Circular Buffer with AMODE = 1 16 15 XAR1 Buffer size = Buffer index 9 + 1 = 10 XAR6 003F8010 Top of buffer XAR6 + XAR1[15:0] = 3F8010h 0x0000 XAR1[15:0] increments until it matches XAR1[31:16] Bottom of buffer XAR6 + XAR1[15:0] = 3F8010h + 0009h Matches...
Page 149: Register Addressing Modes
Register Addressing Modes 5.7 Register Addressing Modes This section includes register addressing modes for 32-bit and 16-bit registers. 5.7.1 32-Bit Register Addressing Modes AMODE ”loc32” Syntax Description Access contents of 32-bit ACC register. @ACC When the ”@ACC” register is the destination operand, this may affect the Z,N,V,C,OVC flags.
Page 150: Bit Register Addressing Modes
Register Addressing Modes 5.7.2 16-Bit Register Addressing Modes AMODE ”loc16” Syntax Description Access contents of 16-bit AL register. AH register contents are un-affected. When the ”@AL” register is the destination operand, this may affect the Z,N,V,C,OVC flags. Example(s): PH,@AL ; Load PH with contents of AL AH,@AL ;...
Page 151 Register Addressing Modes AMODE ”loc16” Syntax Description Access contents of 16-bit PH register. PL register contents are un-affected. Example(s): PL,@PH ; Load PL with contents of PH AL,@PH ; AL = AL + PH T,@PH ; Load T with contents of PH AMODE ”loc16”...
Page 152: Data/Program/Io Space Immediate Addressing Modes
Data/Program/IO Space Immediate Addressing Modes 5.8 Data/Program/IO Space Immediate Addressing Modes Syntax Description *(0:16bit) 32BitDataAddr(31:16) = 0 32BitDataAddr(15:0) = 16−bit immediate value Note: If instruction is repeated, the address is post−incremented on each iteration. This addressing mode can only access the low 64K of data space. Instructions that use this addressing mode: loc16,*(0:16bit) ;...
Page 153 Data/Program/IO Space Immediate Addressing Modes Syntax Description *(pma) 22BitProgAddr(21:16) = 0x3F 22BitProgAddr(15:0) = pma 16−bit immediate value Note: If instruction is repeated, the address is post−incremented on each iteration. This addressing mode can only access the upper 64K of program space. Instructions that use this addressing mode: XPREAD loc16,*(pma)
Page 154: Program Space Indirect Addressing Modes
Program Space Indirect Addressing Modes 5.9 Program Space Indirect Addressing Modes Syntax Description 22BitProgAddr(21:16) = 0x3F 22BitProgAddr(15:0) = AL Note: If instruction is repeated, the address in AL is copied to a shadow register and the value post−incremented on each iteration. The AL register is not modified. This ad- dressing mode can only access the upper 64K of program space.
Page 155: Byte Addressing Modes
Byte Addressing Modes 5.10 Byte Addressing Modes Syntax Description *+XARn[AR0] 32BitDataAddr(31:0) = XARn + Offset (Offset = AR0/AR1/3bit) *+XARn[AR1] if( Offset == Even Value ) *+XARn[3bit] Access LSByte Of 16−bit Memory Location; Leave MSByte untouched; if( Offset == Odd Value ) Access MSByte Of 16−bit Memory Location;...
Page 156 Byte Addressing Modes Instructions that use this addressing mode: MOVB AX.LSB,loc16 ; if( address mode == *+XARn[AR0/AR1/3bit] ) if( offset == even ) AX.LSB = [loc16].LSB; AX.MSB = 0x00; if( offset == odd ) AX.LSB = [loc16].MSB; AX.MSB = 0x00; ;...
Page 157: Alignment Of 32-Bit Operations
Alignment of 32-Bit Operations 5.11 Alignment of 32-Bit Operations All 32-bit reads and writes to memory are aligned at the memory interface to an even address boundary with the least significant word of the 32-bit data aligned to the even address. The output of the address generation unit does not force alignment, hence pointer values retain their values.
Page 158: Instruction Set Summary (Organized By Function)
Chapter 6 C28x Assembly Language Instructions This chapter presents summaries of the instruction set, defines special sym- bols and notations used, and describes each instruction in detail in alphabeti- cal order. Topic Page Instruction Set Summary (Organized by Function) ....Register Operations .
Page 159: Instruction Set Summary (Organized By Function)
Instruction Set Summary (Organized by Function) 6.1 Instruction Set Summary (Organized by Function) Note: The examples in this chapter assume that the device is already operating in C28x Mode (OBJMODE = = 1, AMODE = = 0). To put the device into C28x mode following a reset, you must first set the OBJMODE bit in ST1 by execut- ing the “C28OBJ”...
Page 160 Instruction Set Summary (Organized by Function) Table 6−1. Instruction Set Summary (Organized by Function) (Continued) Symbol Description S:8bit 8-bit immediate value, sign extended 10bit 10-bit immediate value 0:10bit 10-bit immediate value, zero extended 16bit 16-bit immediate value 0:16bit 16-bit immediate value, zero extended S:16bit 16-bit immediate value, sign extended 22bit...
Page 161: 6.2 Register Operations
Register Operations 6.2 Register Operations Note: The examples in this chapter assume that the device is already operating in C28x Mode (OBJMODE == 1, AMODE == 0). To put the device into C28x mode following a reset, you must first set the OBJMODE bit in ST1 by executing the “C28OBJ”...
Page 162 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page SP Register Operations (Continued) AR3:AR2 Pop AR3 & AR2 registers from stack 6-268 AR5:AR4 Pop AR5 & AR4 registers from stack 6-268 DBGIER Pop DBGIER register from stack 6-270 DP:ST1 Pop DP &...
Page 163 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page SP Register Operations (Continued) PUSH T:ST0 Push T & ST0 registers on stack 6-296 PUSH Push XT register on stack 6-298 PUSH XARn Push auxiliary register on stack 6-297 SUBB SP,#7bit Subtract 7-bit constant from the stack pointer 6-341...
Page 164 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page AX Register Operations (AH, AL) (Continued) MOVB AX,#8bit Load AX with 8-bit constant 6-189 MOVB AX.LSB,loc16 Load LSB of AX reg, MSB = 0x00 6-190 MOVB AX.MSB,loc16 Load MSB of AX reg, LSB = unchanged 6-192 MOVB loc16,AX.LSB...
Page 165 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page 16-Bit ACC Register Operations (Continued) ACC,loc16 {<< 0..16} Load accumulator with shift 6-159 ACC,#16bit {<< 0..15} Load accumulator with shift 6-159 loc16,ACC << 1..8 Save low word of shifted accumulator 6-167 ACC,loc16 <<...
Page 166 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page 32-Bit ACC Register Operations (Continued) ASRL ACC,T Arithmetic shift right of accumulator by T(4:0) 6-57 CMPL ACC,loc32 Compare 32-bit value 6-80 CMPL ACC,P << PM Compare 32-bit value 6-81 Count sign bits 6-83 ACC,1..16 Logical shift left 1 to 16 places...
Page 167 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page 32-Bit ACC Register Operations (Continued) SUBCU ACC,loc16 Subtract conditional 16-bit value 6-345 SUBCUL ACC,loc32 Subtract conditional 32-bit value 6-347 SUBL ACC,loc32 Subtract 32-bit value 6-350 SUBL loc32,ACC Subtract 32-bit value 6-353 SUBL ACC,P <<...
Page 168 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page P or XT Register Operations (P, PH, PL, XT, T, TL) (Continued) loc16,T Store the T register 6-175 TL,#0 Clear the lower half of the XT register 6-181 MOVA T,loc16 Load the T register and add the previous product 6-183 MOVAD...
Page 169 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page 16x16 Multiply Operations (Continued) MPYB ACC,T,#8bit Multiply by 8-bit constant 6-235 MPYU ACC,T,loc16 16 X 16-bit unsigned multiply 6-240 MPYU P,T,loc16 Unsigned 16 X 16 multiply 6-239 MPYXU P,T,loc16 Multiply signed value by unsigned value 6-242 MPYXU ACC,T,loc16...
Page 170 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page Direct Memory Operations (Continued) loc16,#16bitSigned Bitwise AND 6-50 loc16,#16bitSigned Compare 6-75 loc16 Decrement by 1 6-84 DMOV loc16 Data move contents of 16-bit location 6-89 loc16 Increment by 1 6-113 *(0:16bit),loc16 Move value 6-156...
Page 171 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page Branch/Call/Return Operations 16bitOff,COND Conditional branch 6-58 BANZ 16bitOff,ARn−− Branch if auxiliary register not equal to zero 6-59 16bOf,ARn,ARn,EQ/NEQ Branch on auxiliary register comparison 6-60 16bitOff,COND Branch fast 6-61 XAR7,22bitAddr Fast function call 6-95 IRET Interrupt return...
Page 172 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page Branch/Call/Return Operations (Continued) XCALL pma,COND C2XLP source-compatible conditional call 6-376 XCALL pma,*,ARPn C2XLP source-compatible call with ARP modification 6-375 XCALL C2XLP source-compatible indirect call 6-374 XRET Alias for XRETC UNC 6-391 XRETC COND...
Page 173 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page Status Register Operations (ST0, ST1) (Continued) CLRC Clear OVC bits 6-70 Clear overflow counter 6-395 DINT Disable maskable interrupts (set INTM bit) 6-85 EINT Enable maskable interrupt (clear INTM bit) 6-92 PM,AX Load product shift mode bits PM = AX(2:0)
Page 174 Register Operations Table 6−2. Register Operations (Continued) Mnemonic Description Page Miscellaneous Operations (Continued) ESTOP0 Emulation Stop 0 6-93 ESTOP1 Emulation Stop 1 6-94 C28x Assembly Language Instructions 6-17...
Page 175 ABORTI ABORTI Abort Interrupt SYNTAX OPTIONS OPCODE OBJMODE ABORTI − 0000 0000 0000 0001 Operands None Description Abort interrupt. This instruction is available for emulation purposes. Generally, a program uses the IRET instruction to return from an interrupt. The IRET instruction restores all of the values that were saved to the stack during the automatic context save.
Page 176 ABS ACC ABS ACC Absolute Value of Accumulator SYNTAX OPTIONS OPCODE OBJMODE ABS ACC − 1111 1111 0101 0110 Operands Accumulator register Description The content of the ACC register is replaced with its absolute value: if(ACC = 0x8000 0000) V = 1; If (OVM = 1) ACC = 0x7FFF FFFF;...
Page 177 ABSTC ACC ABSTC ACC Absolute Value of Accumulator and Load TC SYNTAX OPTIONS OPCODE OBJMODE ABSTC ACC − 0101 0110 0101 1111 Operands Accumulator register Description Replace the content of the ACC register with its absolute value and load the test control (TC) bit with the sign bit XORed with the previous value of the test control bit: if(ACC = 0x8000 0000)
Page 178 ABSTC ACC Example ; Calculate signed: Quot16 = Num16/Den16, Rem16 = Num16%Den16 CLRC ; Clear TC flag, used as sign flag ACC,@Den16 << 16 ; AH = Den16, AL = 0 ABSTC ; Take abs value, TC = sign ^ TC T,@AH ;...
Page 179 ADD ACC,#16bit<<#0..15 ADD ACC,#16bit<<#0..15 Add Value to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADD ACC,#16bit<<#0..15 − 1111 1111 0001 SHFT CCCC CCCC CCCC CCCC Accumulator register Operands #16bit 16-bit immediate constant value #0..15 Shift value (default is ”<< #0” if no value specified) Description Add the left shifted 16-bit immediate constant value to the ACC register.
Page 180 ADD ACC,#16bit<<#0..15 ACC,@VarB << #10 ; Load ACC with VarB left shifted by 10 ACC,#23 << #6 ; Add 23 left shifted by 6 to ACC 6-23...
Page 181 ADD ACC,loc16 << T ADD ACC,loc16 << T Add Value to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADD ACC,loc16<< T 0101 0110 0010 0011 0000 0000 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register, XT(31:16) Description Add to the ACC register the left-shifted contents of the 16-bit location pointed to by the “loc16”...
Page 182 ADD ACC,loc16 << #0..16 ADD ACC,loc16 << #0..16 Add Value to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADD ACC,loc16<<#0 1000 0001 LLLL LLLL ADD ACC,loc16 << #1..15 0101 0110 0000 0100 0000 SHFT LLLL LLLL ADD ACC,loc16 << #16 0000 0101 LLLL LLLL ADD ACC,loc16<<0...15 −...
Page 183 ADD ACC,loc16 << #0..16 Example ; Calculate signed value: ACC = VarA << 10 + VarB << 6; SETC SXM ; Turn sign extension mode on ACC,@VarA << #10 ; Load ACC with VarA left shifted by 10 ACC,@VarB << #6 ;...
Page 184 ADD AX, loc16 ADD AX, loc16 Add Value to AX SYNTAX OPTIONS OPCODE OBJMODE ADD AX, loc16 − 1001 010A LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) Description Add the contents of the location pointed to by the “loc16” addressing mode to the specified AX register (AH or AL) and store the result in the AX register: AX = AX + [loc16];...
Page 185 ADD loc16, AX ADD loc16, AX Add AX to Specified Location SYNTAX OPTIONS OPCODE OBJMODE ADD loc16, AX − 0111 001A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Description Add the contents of the specified AX register (AH or AL) to the location pointed to by the “loc16”...
Page 186 ADD loc16,#16bitSigned ADD loc16,#16bitSigned Add Constant to Specified Location SYNTAX OPTIONS OPCODE OBJMODE ADD loc16,#16bitSigned − 0000 1000 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) #16bit- 16-bit immediate signed constant value Signed Description Add the specified signed 16-bit immediate constant to the signed 16-bit content of the location pointed to by the “loc16”...
Page 187 ADDB ACC,#8bit ADDB ACC,#8bit Add 8-bit Constant to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADDB ACC,#8bit − 0000 1001 CCCC CCCC Accumulator register Operands #8bit 8-bit immediate unsigned constant value Description Add an 8-bit, zero-extended constant to the ACC register: ACC = ACC + 0:8bit; After the addition, the Z flag is set if ACC is zero, else Z is cleared.
Page 188 ADDB AX, #8bitSigned ADDB AX, #8bitSigned Add 8-bit Constant to AX SYNTAX OPTIONS OPCODE OBJMODE ADDB AX, #8bitSigned − 1001 110A CCCC CCCC Operands Accumulator high (AH) or accumulator low (AL) register #8bit- 8-bit immediate signed 2s complement constant value (-128 to 127) Signed Description Add the sign extended 8-bit constant to the specified AX register (AH...
Page 189 ADDB SP, #7bit ADDB SP, #7bit Add 7-bit Constant to Stack Pointer SYNTAX OPTIONS OPCODE OBJMODE ADDB SP, #7bit − 1111 1110 0CCC CCCC Operands Stack pointer #7bit 7-bit immediate unsigned constant value Description Add a 7-bit unsigned constant to SP and store the result in SP: SP = SP + 0:7bit;...
Page 190 ADDB XARn, #7bit ADDB XARn, #7bit Add 7-bit Constant to Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE ADDB XARn, #7bit − 1101 1nnn 0CCC CCCC Operands XARn XAR0−XAR7, 32-bit auxiliary registers Description Add a 7-bit unsigned constant to XARn and store the result in XARn: XARn = XARn + 0:7bit;...
Page 191 ADDCL ACC,loc32 ADDCL ACC,loc32 Add 32-bit Value Plus Carry to Accumulator SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0100 0000 ADDCL ACC,loc32 − xxxx xxxx LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Add to the ACC register the 32-bit content of the location pointed to by the “loc32”...
Page 192 ADDCU ACC,loc16 ADDCU ACC,loc16 Add Unsigned Value Plus Carry to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADDCU ACC,loc16 − 0000 1100 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Add the 16-bit contents of the location pointed to by the “loc16” addressing mode, zero extended, plus the content of the carry flag bit to the ACC register: ACC = ACC + 0:[loc16] + C;...
Page 193 ADDL ACC,loc32 ADDL ACC,loc32 Add 32-bit Value to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADDL ACC,loc32 0000 0111 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Add to the ACC register the 32-bit content of the location pointed to by the “loc32”...
Page 194 ADDL ACC,P << PM ADDL ACC,P << PM Add Shifted P to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADDL ACC,P << PM 0001 0000 1010 1100 Note: This instruction is an alias for the ”MOVA T,loc16” operation with “loc16 = @T” addressing mode. Operands Accumulator register Product register...
Page 195 ADDL loc32,ACC ADDL loc32,ACC Add Accumulator to Specified Location SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0000 0001 ADDL loc32, ACC − 0000 0000 LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Accumulator register Add to the ACC register the 32-bit content of the location pointed to by the Description “loc32”...
Page 196 ADDU ACC,loc16 ADDU ACC,loc16 Add Unsigned Value to Accumulator SYNTAX OPTIONS OPCODE OBJMODE ADDU ACC,loc16 0000 1101 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Add the 16-bit contents of the location pointed to by the “loc16” addressing mode to the ACC register.
Page 197 ADDUL P,loc32 ADDUL P,loc32 Add 32-bit Unsigned Value to P SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 0111 ADDUL P,loc32 − 0000 0000 LLLL LLLL Operands Product register loc32 Addressing mode (see Chapter 5) Description Add to the P register the 32-bit content of the location pointed to by the “loc32” addressing mode.
Page 198 ADDUL ACC, loc32 ADDUL ACC, loc32 Add 32-bit Unsigned Value to Accumulator SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 0011 ADDUL ACC, loc32 xxxx xxxx LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Add to the ACC register the unsigned 32-bit content of the location pointed to by the “loc32”...
Page 199 ADRK #8bit ADRK #8bit Add to Current Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE ADRK #8bit − 1111 1100 IIII IIII Operands #8bit 8-bit immediate constant value Description Add the 8-bit unsigned constant to the XARn register pointed to by ARP: XAR(ARP) = XAR(ARP) + 0:8bit;...
Page 200 AND ACC,#16bit << #0..16 AND ACC,#16bit << #0..16 Bitwise AND SYNTAX OPTIONS OPCODE OBJMODE AND ACC, #16bit << #0..15 − 0011 1110 0000 SHFT CCCC CCCC CCCC CCCC AND ACC, #16bit << #16 − 0101 0110 0000 1000 CCCC CCCC CCCC CCCC Operands Accumulator register #16bit...
Page 201 AND ACC, loc16 AND ACC, loc16 Bitwise AND SYNTAX OPTIONS OPCODE OBJMODE AND ACC, loc16 1000 1001 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Perform a bitwise AND operation on the ACC register with the zero-extended content of the location pointed to by the “loc16”...
Page 202 AND AX, loc16, #16bit AND AX, loc16, #16bit Bitwise AND SYNTAX OPTIONS OPCODE OBJMODE AND AX, loc16, #16bit − 1100 110A LLLL LLLL CCCC CCCC CCCC CCCC Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) #16bit 16-bit immediate constant value Description...
Page 203 AND IER,#16bit AND IER,#16bit Bitwise AND to Disable Specified CPU Interrupts SYNTAX OPTIONS OPCODE OBJMODE AND IER,#16bit − 0111 0110 0010 0110 CCCC CCCC CCCC CCCC Operands Interrupt enable register 16-bit immediate constant value (0x0000 to 0xFFFF) #16bit Description Disable specific interrupts by performing a bitwise AND operation with the IER register and the 16-bit immediate value.
Page 204 AND IFR,#16bit AND IFR,#16bit Bitwise AND to Clear Pending CPU Interrupts SYNTAX OPTIONS OPCODE OBJMODE AND IFR,#16bit − 0111 0110 0010 1111 CCCC CCCC CCCC CCCC Operands Interrupt flag register #16bit 16-bit immediate constant value (0x0000 to 0xFFFF) Description Clear specific pending interrupts by performing a bitwise AND operation with the IFR register and the 16-bit immediate value.
Page 205 AND loc16, AX AND loc16, AX Bitwise AND SYNTAX OPTIONS OPCODE OBJMODE AND loc16, AX − 1100 000A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Description Perform a bitwise AND operation on the contents of the location pointed to by the “loc16”...
Page 206 AND AX, loc16 AND AX, loc16 Bitwise AND SYNTAX OPTIONS OPCODE OBJMODE AND AX, loc16 − 1100 111A LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) Description Perform a bitwise AND operation on the contents of the specified AX register with the 16-bit contents of the location pointed to by the “loc16”...
Page 207 AND loc16,#16bitSigned AND loc16,#16bitSigned Bitwise AND SYNTAX OPTIONS OPCODE OBJMODE AND loc16,#16bitSigned − 0001 1000 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) #16bitSigned 16-bit signed immediate constant value Description Perform a bitwise AND operation on the 16-bit content of the location pointed to by the “loc16”...
Page 208 ANDB AX, #8bit ANDB AX, #8bit Bitwise AND 8-bit Value SYNTAX OPTIONS OPCODE OBJMODE ANDB AX, #8bit − 1001 000A CCCC CCCC Operands Accumulator high (AH) or accumulator low (AL) register #8bit 8-bit immediate constant value Description Perform a bitwise AND operation with the content of the specified AX register (AH or AL) with the given 8-bit unsigned immediate constant zero extended.
Page 209 Align Stack Pointer SYNTAX OPTIONS OPCODE OBJMODE − 0111 0110 0001 1011 Operands None Description Ensure that the stack pointer (SP) is aligned to an even address. If the least significant bit of SP is 1, SP points to an odd address and must be moved by incrementing SP by 1.
Page 210 ASR AX,#1...16 ASR AX,#1...16 Arithmetic Shift Right SYNTAX OPTIONS OPCODE OBJMODE ASR AX,#1...16 − 1111 1111 101A SHFT Operands Accumulator high (AH) or accumulator low (AL) register 1016 Shift value Description Perform an arithmetic right shift on the content of the specified AX register (AH or AL) by the amount given in the “shift value”...
Page 211 ASR AX,T ASR AX,T Arithmetic Shift Right SYNTAX OPTIONS OPCODE OBJMODE ASR AX,T − 1111 1111 0110 010A Operands Accumulator high (AH) or accumulator low (AL) register Upper 16 bits of the multiplicand (XT) register Description Perform an arithmetic shift right on the content of the specified AX register as specified by the four least significant bits of the T register, T(3:0) = shift value = 0…15.
Page 212 ASR64 ACC:P,#1..16 ASR64 ACC:P,#1..16 Arithmetic Shift Right of 64-bit Value SYNTAX OPTIONS OPCODE OBJMODE ASR64 ACC:P,#1..16 − 0101 0110 1000 SHFT Operands ACC:P Accumulator register (ACC) and product register (P) #1..16 Shift value Description Arithmetic shift right the 64-bit combined value of the ACC:P registers by the amount specified in the shift value field.
Page 213 ASR64 ACC:P,T ASR64 ACC:P,T Arithmetic Shift Right of 64-bit Value SYNTAX OPTIONS OPCODE OBJMODE ASR64 ACC:P,T − 0101 0110 0010 1100 Operands ACC:P Accumulator register (ACC) and product register (P) Upper 16 bits of the multiplicand register (XT) Description Arithmetic shift right the 64-bit combined value of the ACC:P registers by the amount specified in six least significant bits of the T register, T(5:0) = 0…63.
Page 214 ASRL ACC,T ASRL ACC,T Arithmetic Shift Right of Accumulator SYNTAX OPTIONS OPCODE OBJMODE ASRL ACC,T − 0101 0110 0001 0000 Operands Accumulator register Upper 16 bits of the multiplicand (XT) register Description Perform an arithmetic shift right on the content of the ACC register as specified by the five least significant bits of the T register, T(4:0) = 0…31.
Page 215 B 16bitOffset,COND B 16bitOffset,COND Branch SYNTAX OPTIONS OPCODE OBJMODE B 16bitOffset,COND − 1111 1111 1110 COND CCCC CCCC CCCC CCCC 16-bit signed immediate constant offset value (−32768 to +32767 range) Operands 16bit- Offset Offset Conditional codes: COND COND Syntax Description Flags Tested 0000 Not Equal To...
Page 216 BANZ 16bitOffset,ARn− − BANZ 16bitOffset,ARn− − Branch if Auxiliary Register Not Equal to Zero SYNTAX OPTIONS OPCODE OBJMODE BANZ 16bitOffset,ARn−− − 0000 0000 0000 1nnn CCCC CCCC CCCC CCCC Operands 16bit- 16-bit signed immediate constant value Offset Lower 16 bits of auxiliary registers XAR0 to XAR7 Description If the 16-bit content of the specified auxiliary register is not equal to 0, then the 16-bit sign offset is added to the PC value.
Page 217 BAR 16bitOffset,ARn,ARm,EQ/NEQ BAR 16bitOffset,ARn,ARm,EQ/NEQ Branch on Auxiliary Register Comparison SYNTAX OPTIONS OPCODE OBJMODE BAR 16bitOffset,ARn,ARm,EQ − 1000 1111 10nn nmmm CCCC CCCC CCCC CCCC BAR 16bitOffset,ARn,ARm,NEQ − 1000 1111 11nn nmmm CCCC CCCC CCCC CCCC Operands 16bit- 16-bit signed immediate constant offset value (−32768 to +32767 range) Offset Lower 16 bits of auxiliary registers XAR0 to XAR7 Lower 16 bits of auxiliary registers XAR0 to XAR7...
Page 218 BF 16bitOffset,COND BF 16bitOffset,COND Branch Fast SYNTAX OPTIONS OPCODE OBJMODE BF 16bitOffset,COND − 0101 0110 1100 COND CCCC CCCC CCCC CCCC 16-bit signed immediate constant offset value (−32768 to +32767 range) Operands 16bit- Offset Conditional codes: COND COND Syntax Description Flags Tested 0000 Not Equal To...
Page 219 C27MAP C27MAP Set the M0M1MAP Bit SYNTAX OPTIONS OPCODE OBJMODE C27MAP − 0101 0110 0011 1111 Note: This instruction is an alias for the “CLRC M0M1MAP” operation. Operands None Description Clear the M0M1MAP status bit, configuring the mapping of the M0 and M1 memory blocks for C27x object-compatible operation.
Page 220 C27OBJ C27OBJ Clear the OBJMODE Bit SYNTAX OPTIONS OPCODE OBJMODE C27OBJ − 0101 0110 0011 0110 Note: This instruction is an alias for the “CLRC OBJMODE” operation. Operands None Description Clear the OBJMODE status bit in Status Register ST1, configuring the device to execute C27x object code.
Page 221 C28ADDR C28ADDR Clear the AMODE Status Bit SYNTAX OPTIONS OPCODE OBJMODE C28ADDR − 0101 0110 0001 0110 Note: This instruction is an alias for the “CLRC AMODE” operation. Operands None Description Clear the AMODE status bit in Status Register ST1, putting the device in C27x/C28x addressing mode (see Chapter 5).
Page 222 C28MAP C28MAP Set the M0M1MAP Bit SYNTAX OPTIONS OPCODE OBJMODE C28MAP − 0101 0110 0001 1010 Note: This instruction is an alias for the “SETC M0M1MAP” instruction. Operands None Description Set the M0M1MAP status bit in Status register ST1, configuring the mapping of the M0 and M1 memory blocks for C28x operation.
Page 223 C28OBJ C28OBJ Set the OBJMODE Bit SYNTAX OPTIONS OPCODE OBJMODE C28OBJ − 0101 0110 0001 1111 Note: This instruction is an alias for the “SETC OBJMODE” instruction. Operands None Description Set the OBJMODE status bit, putting the device in C28x object mode (supports C2xLP source): Flags and Set the OBJMODE bit.
Page 224 CLRC AMODE CLRC AMODE Clear the AMODE Bit SYNTAX OPTIONS OPCODE OBJMODE CLRC AMODE − 0101 0110 0001 0110 AMODE Operands Status bit Description Clear the AMODE status bit in Status Register ST1, enabling C27x/C28x addressing (see Chapter 5). Note: This instruction does not flush the pipeline. AMODE The AMODE bit is cleared.
Page 225 CLRC M0M1MAP CLRC M0M1MAP Clear the M0M1MAP Bit SYNTAX OPTIONS OPCODE OBJMODE CLRC M0M1MAP − 0101 0110 0011 1111 Operands Status bit M0M1MAP Description Clear the M0M1MAP status bit in Status Register ST1, configuring the mapping of the M0 and M1 memory blocks for C27x operation. The memory blocks are mapped as follows: C27x Compatible Mapping C28 at Reset...
Page 226 CLRC OBJMODE CLRC OBJMODE Clear the OBJMODE Bit SYNTAX OPTIONS OPCODE OBJMODE CLRC OBJMODE − 0101 0110 0011 0110 Operands Status bit OBJ- MODE Description Clear the OBJMODE status bit, enabling the device to execute C27x object code. Note: The pipeline is flushed when this instruction is executed. Flags and The OBJMODE bit is cleared.
Page 227 CLRC OVC CLRC OVC Clear Overflow Counter SYNTAX OPTIONS OPCODE OBJMODE CLRC OVC − 0101 0110 0101 1100 Note: This instruction is an alias for the “ZAP OVC” operation. Operands Overflow counter bits in Status Register 0 (ST0) Description Clear the overflow counter (OVC) bits in ST0. Flags and The 6-bit overflow counter bits (OVC) are cleared.
Page 228 CLRC XF CLRC XF Clear XF Status Bit SYNTAX OPTIONS OPCODE OBJMODE CLRC XF − 0101 0110 0001 1011 Operands XF status bit and output signal Description Clear the XF status bit and pull the corresponding output signal low. Flags and The XF status bit is cleared.
Page 229 CLRC Mode CLRC Mode Clear Status Bits SYNTAX OPTIONS OPCODE OBJMODE CLRC mode − 1, 2 0010 1001 CCCC CCCC CLRC − 0010 1001 0000 0001 CLRC − 0010 1001 0000 0010 CLRC − 0010 1001 0000 0100 CLRC − 0010 1001 0000 1000 CLRC INTM...
Page 230 CLRC Mode Example Modify flag settings: SETC INTM,DBGM ; Set INTM and DBGM bits to 1 CLRC TC,C,SXM,OVM ; Clear TC, C, SXM, OVM bits to 0 CLRC #0xFF ; Clear all bits to 0 SETC #0xFF ; Set all bits to 1 SETC C,SXM,TC,OVM ;...
Page 231 CMP AX, loc16 CMP AX, loc16 Compare SYNTAX OPTIONS OPCODE OBJMODE CMP AX, loc16 − 0101 010A LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) Description The content of the specified AX register (AH or AL) is compared with the 16-bit content of the location pointed to by the “loc16”...
Page 232 CMP loc16,#16bit CMP loc16,#16bitSigned Compare SYNTAX OPTIONS OPCODE OBJMODE CMP loc16,#16bitSigned − 0001 1011 LLLL LLLL CCCC CCCC CCCC CCCC loc16 Operands Addressing mode (see Chapter 5) #16bitSigned 16-bit immediate signed constant value Description Compare the 16-bit contents of the location pointed to by the “loc16” addressing mode to the signed 16-bit immediate constant value.
Page 233 CMP loc16,#16bit Example Calculate: ; if( VarA > 20 ) VarA = 0; @VarA,#20 ; Set flags on (VarA − 20) MOVB @VarA,#0,GT ; Zero VarA if greater then 6-76...
Page 234 CMP64 ACC:P CMP64 ACC:P Compare 64-bit Value SYNTAX OPTIONS OPCODE OBJMODE CMP64 ACC:P − 0101 0110 0101 1110 Operands ACC:P Accumulator register (ACC) and product register (P) Description The 64-bit content of the combined ACC:P registers is compared against zero and the flags are set appropriately: if((V = 1) &...
Page 235 CMP64 ACC:P Example ; If 64-bit VarA > 64-bit VarB, branch: CMP64 ACC:P ; Clear V flag MOVL P,@VarA+0 ; Load P with low 32 bits of VarA MOVL ACC,@VarA+2 ; Load ACC with high 32 bits of VarA SUBUL P,@VarB+0 ;...
Page 236 CMPB AX, #8bit CMPB AX, #8bit Compare 8-bit Value SYNTAX OPTIONS OPCODE OBJMODE CMPB AX, #8bit − 0101 001A CCCC CCCC Operands Accumulator high (AH) or accumulator low (AL) register #8bit 8-bit immediate constant value Description Compare the content of the specified AX register (AH or AL) with the zero-extended 8-bit unsigned immediate constant.
Page 237 CMPL ACC,loc32 CMPL ACC,loc32 Compare 32-bit Value SYNTAX OPTIONS OPCODE OBJMODE CMPL ACC,loc32 − 0000 1111 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description The content of the ACC register is compared with the 32-bit location pointed to by the “loc32”...
Page 238 CMPL ACC,P << PM CMPL ACC,P << PM Compare 32-bit Value SYNTAX OPTIONS OPCODE OBJMODE CMPL ACC,P << PM − 1111 1111 0101 1001 Operands Accumulator register Product register <<PM Product shift mode Description The content of the ACC register is compared with the content of the P register, shifted by the amount specified by the product shift mode (PM).
Page 239 CMPR 0/1/2/3 CMPR 0/1/2/3 Compare Auxiliary Registers SYNTAX OPTIONS OPCODE OBJMODE CMPR 0 − 0101 0110 0001 1101 CMPR 1 − 0101 0110 0001 1001 CMPR 2 − 0101 0110 0001 1000 CMPR 3 − 0101 0110 0001 1100 Operands None Description Compare AR0 to the 16-bit auxiliary register pointed to by ARP.
Page 240 CSB ACC CSB ACC Count Sign Bits SYNTAX OPTIONS OPCODE OBJMODE CSB ACC − 0101 0110 0011 0101 Operands Accumulator register Description Count the sign bits in the ACC register by determining the number of leading 0s or 1s in the ACC register and storing the result, minus one, in the T register: T = 0, 1 sign bit T = 1, 2 sign bits T = 31, 32 sign bits...
Page 241 DEC loc16 DEC loc16 Decrement by 1 SYNTAX OPTIONS OPCODE OBJMODE DEC loc16 − 0000 1011 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Description Subtract 1 from the signed content of the location pointed to by the “loc16” addressing mode: Flags and After the operation if bit 15 of [loc16] is 1, set N;...
Page 242 DINT DINT Disable Maskable Interrupts (Set INTM Bit) SYNTAX OPTIONS OPCODE OBJMODE DINT − 0011 1011 0001 0000 Note: This instruction is an alias for the “SETC mode” operation with the ”mode” field = INTM. Operands None Description Disable all maskable CPU interrupts by setting the INTM status bit. DINT has no effect on the unmaskable reset or NMI interrupts.
Page 243 DMAC ACC:P,loc32,*XAR7/++ DMAC ACC:P,loc32,*XAR7/++ 16-Bit Dual Multiply and Accumulate SYNTAX OPTIONS OPCODE OBJMODE DMAC ACC:P,loc32,*XAR7 0101 0110 0100 1011 1100 0111 LLLL LLLL DMAC ACC:P,loc32,*XAR7++ 0101 0110 0100 1011 1000 0111 LLLL LLLL Operands ACC:P Accumulator register (ACC) and product register (P) loc32 Addressing mode (see Chapter 5) Note:...
Page 244 DMAC ACC:P,loc32,*XAR7/++ With some addressing mode combinations, you can get conflicting references. In such cases, the C28x will give the “loc16/loc32” field priority on changes to XAR7. For example: DMAC ACC:P,*−−XAR7,*XAR7++ ; −−XAR7 given priority DMAC ACC:P,*XAR7++,*XAR7 ; *XAR7++ given priority DMAC ACC:P,*XAR7,*XAR7++ ;...
Page 245 DMAC ACC:P,loc32,*XAR7/++ Example Calculate sum of product using dual 16-bit multiply: int16 X[N] ; Data information int16 C[N] ; Coefficient information (located in low 4M) ; Data and Coeff must be aligned to even address ; N must be an even number sum = 0;...
Page 246 DMOV loc16 DMOV loc16 Data Move Contents of 16-bit Location SYNTAX OPTIONS OPCODE OBJMODE DMOV loc16 1010 0101 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Note: For this operation, register−addressing modes cannot be used. The modes are: @ARn, @AH, @AL, @PH, @PL, @SP, @T. An illegal instruction trap will be generated.
Page 247 EALLOW EALLOW Enable Write Access to Protected Space SYNTAX OPTIONS OPCODE OBJMODE EALLOW − 0111 0110 0010 0010 Operands None Description Enable access to emulation space and other protected registers. This instruction sets the EALLOW bit in status register ST1. When this bit is set, the C28x CPU allows write access to the memory-mapped registers as well as other protected registers.
Page 248 EDIS EDIS Disable Write Access to Protected Registers SYNTAX OPTIONS OPCODE OBJMODE EDIS − 0111 0110 0001 1010 Operands None Description Disable access to emulation space and other protected registers. This instruction clears the EALLOW bit in status register ST1. When this bit is clear, the C28x CPU does not allow write access to the memory−mapped emulation registers and other protected registers.
Page 249 EINT EINT Enable Maskable Interrupts (Clear INTM Bit) SYNTAX OPTIONS OPCODE OBJMODE EINT − 0010 1001 0001 0000 Note: This instruction is an alias for the “CLRC mode” operation with the ”mode” field = INTM. Operands None Description Enable interrupts by clearing the INTM status bit. Flags and INTM This bit is cleared by the instruction to enable interrupts.
Page 250 ESTOP0 ESTOP0 Emulation Stop 0 SYNTAX OPTIONS OPCODE OBJMODE ESTOP0 − 0111 0110 0010 0101 Operands None Description Emulation Stop 0 This instruction is available for emulation purposes. It is used to create a software breakpoint. When an emulator is connected to the C28x and emulation is enabled, this instruction causes the C28x to halt, regardless of the state of the DBGM bit in status register ST1.
Page 251 ESTOP1 ESTOP1 Emulation Stop 1 SYNTAX OPTIONS OPCODE OBJMODE ESTOP1 − 0111 0110 0010 0100 Operands None Description Emulation Stop 1 This instruction is available for emulation purposes. It is used to create an embedded software breakpoint. When an emulator is connected to the C28x and emulation is enabled, this instruction causes the C28x to halt, regardless of the state of the DBGM bit in status register ST1.
Page 252 FFC XAR7,22bit FFC XAR7,22bit Fast Function Call SYNTAX OPTIONS OPCODE OBJMODE FFC XAR7,22bit − 0000 0000 11CC CCCC CCCC CCCC CCCC CCCC Operands XAR7 Auxiliary register XAR7 22bit 22-bit program-address (0x00 0000 to 0x3F FFFF range) Description Fast function call. The return PC value is stored into the XAR7 register and the 22-bit immediate destination address is loaded into the PC: XAR7(21:0) = PC + 2;...
Page 253 FLIP AX FLIP AX Flip Order of Bits in AX Register SYNTAX OPTIONS OPCODE OBJMODE FLIP AX − 0101 0110 0111 000A Operands Accumulator high (AH) or accumulator low (AL) register Description Bit reverse the contents of the specified AX register (AH or AL): temp = AX;...
Page 254 IACK #16bit IACK #16bit Interrupt Acknowledge SYNTAX OPTIONS OPCODE OBJMODE IACK #16bit − 0111 0110 0011 1111 CCCC CCCC CCCC CCCC Operands #16bit 16-bit constant immediate value (0x0000 to 0xFFFF range) Description Acknowledge an interrupt by outputting the specified 16-bit constant on the low 16 bits of the data bus.
Page 255 IDLE IDLE Put Processor in Idle Mode SYNTAX OPTIONS OPCODE OBJMODE IDLE − 0111 0110 0010 0001 Operands None Description Put the processor into idle mode and wait for enabled or nonmaskable in- terrupt. Devices using the 28x CPU may use the IDLE instruction in com- bination with external logic to achieve different low-power modes.
Page 256 IDLE Flags and IDLESTAT Before entering the idle mode, IDLESTAT is set; after exiting the idle mode Modes IDLESTAT is cleared. Repeat This instruction is not repeatable. If this instruction follows the RPT instruc- tion, it resets the repeat counter (RPTC) and executes only once. 6-99...
Page 257 IMACL P,loc32,*XAR7/++ IMACL P,loc32,*XAR7/++ Signed 32 X 32-Bit Multiply and Accumulate (Lower Half) SYNTAX OPTIONS OPCODE OBJMODE IMACL P,loc32,*XAR7 0101 0110 0100 1101 1100 0111 LLLL LLLL IMACL P,loc32,*XAR7++ 0101 0110 0100 1101 1000 0111 LLLL LLLL Operands Product register loc32 Addressing mode (see Chapter 5) Note:...
Page 258 IMACL P,loc32,*XAR7/++ On the C28x devices, memory blocks are mapped to both program and data space (unified memory), hence the ”*XAR7/++” addressing mode can be used to access data space variables that fall within the program space address range. With some addressing mode combinations, you can get conflicting references.
Page 259 IMACL P,loc32,*XAR7/++ Example ; Calculate sum of product using 32-bit multiply and retain ; 64-bit result: ; int32 X[N]; // Data information ; int32 C[N]; // Coefficient information (located in // low 4M) ; int64 sum = 0; ; for(i=0; i < N; i++) sum = sum + (X[i] * C[i]) >>...
Page 260 IMPYAL P,XT,loc32 IMPYAL P,XT,loc32 Signed 32-Bit Multiply (Lower Half) and Add Previous P SYNTAX OPTIONS OPCODE OBJMODE IMPYAL P,XT,loc32 − 0101 0110 0100 1100 0000 0000 LLLL LLLL Product register Operands Multiplicand register loc32 Addressing mode (see Chapter 5) Description Add the unsigned content of the P register, ignoring the product shift mode (PM), to the ACC register.
Page 261 IMPYAL P,XT,loc32 Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Calculate signed result: ; Y64 = (X0*C0 + X1*C1 + X2*C2) >> 2 −2 ;...
Page 262 IMPYL ACC,XT,loc32 IMPYL ACC,XT,loc32 Signed 32 X 32-Bit Multiply (Lower Half) SYNTAX OPTIONS OPCODE OBJMODE IMPYL ACC,XT,loc32 − 0101 0110 0100 0100 0000 0000 LLLL LLLL Operands Accumulator register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the “loc32”...
Page 263 IMPYL P,XT,loc32 IMPYL P,XT,loc32 Signed 32 X 32-Bit Multiply (Lower Half) SYNTAX OPTIONS OPCODE OBJMODE IMPYL P,XT,loc32 − 0101 0110 0000 0101 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the “loc32”...
Page 264 IMPYSL P,XT,loc32 IMPYSL P,XT,loc32 Signed 32-Bit Multiply (Low Half) and Subtract P SYNTAX OPTIONS OPCODE OBJMODE IMPYSL P,XT,loc32 − 0101 0110 0100 0011 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Subtract the unsigned content of the P register, ignoring the product shift mode (PM), from the ACC register.
Page 265 IMPYSL P,XT,loc32 Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Calculate signed result: ; Y64 = (−X0*C0 − X1*C1 − X2*C2) >> 2 −2 ;...
Page 266 IMPYXUL P,XT,loc32 IMPYXUL P,XT,loc32 Signed 32 X Unsigned 32-Bit Multiply (Lower Half) SYNTAX OPTIONS OPCODE OBJMODE IMPYXUL P,XT,loc32 − 0101 0110 0110 0101 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Multiply the signed 32-bit content of the XT register by the unsigned 32-bit content of the location pointed to by the “loc32”...
Page 267 IMPYXUL P,XT,loc32 Example ; Calculate result: Y64 = M64*X64 + B64 ; Y64 = Y1:Y0, M64 = M1:M0, X64 = X1:X0, B64 = B1:B0 MOVL XT,@X0 ; XT = X0 IMPYL P,XT,@M0 = low 32 bits of (uns M0 * uns X0) MOVL ACC,@B0 ;...
Page 268 IN loc16,*(PA) IN loc16,*(PA) Input Data From Port SYNTAX OPTIONS OPCODE OBJMODE IN loc16,*(PA) 1011 0100 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) *(PA) Immediate I/O space memory address Description Load the location pointed to by the “loc16” addressing mode with the content of the specified I/O location pointed to by ”*(PA)”: [loc16] = IOspace[PA];...
Page 269 IN loc16,*(PA) @AL,#0 ; AL = 0 UOUT *(IORegC),@AL ; IOspace[IORegC] = AL $10: 6-112...
Page 270 INC loc16 INC loc16 Increment by 1 SYNTAX OPTIONS OPCODE OBJMODE INC loc16 − 0000 1010 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Description Add 1 to the signed content of the location pointed to by the “loc16” addressing mode: [loc16] = [loc16] + 1;...
Page 271 INTR INTR Emulate Hardware Interrupt SYNTAX OPTIONS OPCODE OBJMODE INTR INTx − 0000 0000 0001 CCCC INTR DLOGINT − 0000 0000 0001 CCCC INTR RTOSINT − 0000 0000 0001 CCCC INTR NMI − 0111 0110 0001 0110 INTR EMUINT − 0111 0110 0001 1100 Operands INTx...
Page 272 INTR Part of the operation involves saving pairs of 16-bit CPU registers onto the stack pointed to by the SP register. Each pair of registers is saved in a single 32-bit operation. The register forming the low word of the pair is saved first (to an even address);...
Page 273 IRET IRET Interrupt Return SYNTAX OPTIONS OPCODE OBJMODE IRET − 0111 0110 0000 0010 Operands None Description Return from an interrupt. The IRET instruction restores the PC value and other register values that were automatically saved by an interrupt operation. The order in which the values are restored is opposite to the order in which they were saved.
Page 274 IRET DBGM PAGEO VMAP EAL- AMODE OBJ- MODE Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. 6-117...
Page 275 IRET Example ; Full interrupt context Save and Restore: ; Vector table: INTx: .long INTxService ; INTx interrupt vector ; Interrupt context save: INTxService: ; ACC, P, T, ST0, ST1, DP, AR0, ; AR1, IER, DPGSTAT registers saved ; on stack. ;...
Page 276 LB *XAR7 LB *XAR7 Long Indirect Branch SYNTAX OPTIONS OPCODE OBJMODE LB *XAR7 − 0111 0110 0010 0000 Operands *XAR7 indirect program-memory addressing using auxiliary register XAR7, can ac- cess full 4Mx16 program space range (0x000000 to 0x3FFFFF) Description Long branch indirect. Load the PC with the lower 22 bits of the XAR7 register: PC = XAR7(21:0);...
Page 277 LB 22bit LB 22bit Long Branch SYNTAX OPTIONS OPCODE OBJMODE LB 22bit − 0000 0000 01CC CCCC CCCC CCCC CCCC CCCC Operands 22bit 22-bit program-address (0x000000 to 0x3FFFFF range) Description Long branch. Load the PC with the selected 22-bit program address: PC = 22bit;...
Page 278 LC *XAR7 LC *XAR7 Long Indirect Call SYNTAX OPTIONS OPCODE OBJMODE LC *XAR7 − 0111 0110 0000 0100 Operands *XAR7 indirect program-memory addressing using auxiliary register XAR7, can ac- cess full 4Mx16 program space range (0x000000 to 0x3FFFFF) Description Indirect long call. The return PC value is pushed onto the software stack, pointed to by SP register, in two 16-bit operations.
Page 279 LC 22bit LC 22bit Long Call SYNTAX OPTIONS OPCODE OBJMODE LC 22bit − 0000 0000 10CC CCCC CCCC CCCC CCCC CCCC Operands 22bit 22-bit program-address (0x00 0000 to 0x3F FFFF range) Description Long function call. The return PC value is pushed onto the software stack, pointed to by SP register, in two 16-bit operations.
Page 280 LCR #22bit LCR #22bit Long Call Using RPC SYNTAX OPTIONS OPCODE OBJMODE LCR #22bit − 0111 0110 01CC CCCC CCCC CCCC CCCC CCCC Operands 22bit 22-bit program-address (0x00 0000 to 0x3F FFFF range) Description Long call using return PC pointer (RPC). The current RPC value is pushed onto the software stack, pointed to by SP register, in two 16-bit operations.
Page 281 LCR *XARn LCR *XARn Long Indirect Call Using RPC SYNTAX OPTIONS OPCODE OBJMODE LCR *XARn − 0011 1110 0110 0RRR Operands *XARn indirect program-memory addressing using auxiliary register XAR0 to XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) Description Long indirect call using return PC pointer (RPC).
Page 282 LOOPNZ loc16,#16bit LOOPNZ loc16,#16bit Loop While Not Zero SYNTAX OPTIONS OPCODE OBJMODE LOOPNZ loc16,#16bit − 5N+5 0010 1110 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) #16bit 16-bit immediate value (0x0000 to 0xFFFF range) Description Loop while not zero.
Page 283 LOOPNZ loc16,#16bit When any interrupt occurs, the current state of the LOOP bit is saved as ST1 is saved on the stack. The LOOP bit in ST1 is then cleared by the interrupt. The LOOP bit is a passive status bit. The LOOPNZ instruction changes LOOP, but LOOP does not affect the instruction.
Page 284 LOOPZ loc16,#16bit LOOPZ loc16,#16bit Loop While Zero SYNTAX OPTIONS OPCODE OBJMODE LOOPZ loc16,#16bit − 5N+5 0010 1100 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) #16bit 16-bit immediate value (0x0000 to 0xFFFF range) Description Loop while zero. while([loc16] &...
Page 285 LOOPZ loc16,#16bit When any interrupt occurs, the current state of the LOOP bit is saved as ST1 is saved on the stack. The LOOP bit in ST1 is then cleared by the interrupt. The LOOP bit is a passive status bit. The LOOPZ instruction changes LOOP, but LOOP does not affect the instruction.
Page 286 LPADDR LPADDR Set the AMODE Bit SYNTAX OPTIONS OPCODE OBJMODE LPADDR − 0101 0110 0001 1110 Note: LPADDR is an alias for the SETC AMODE Operation. Operands None Description Set the AMODE status bit, putting the device in C2xLP compatible addressing mode (see Chapter 5).
Page 287 LRET LRET Long Return SYNTAX OPTIONS OPCODE OBJMODE LRET − 0111 0110 0001 0100 Operands None Description Long return. The return address is popped, from the software stack into the PC, in two 16-bit operations: SP = SP – 1; temp(31:16) = [SP];...
Page 288 LRETE LRETE Long Return and Enable Interrupts SYNTAX OPTIONS OPCODE OBJMODE LRETE − 0111 0110 0001 0000 Operands None Description Long return and enable interrupts. The return address is popped, from the software stack into the PC, in two 16-bit operations. Next, the global interrupt flag (INTM) is cleared.
Page 289 LRETR LRETR Long Return Using RPC SYNTAX OPTIONS OPCODE OBJMODE LRETR − 0000 0000 0000 0110 Operands None Description Long return using return PC pointer (RPC). The return address stored in the RPC register is loaded onto the PC. Next, the RPC register is loaded from the software stack in two 16-bit operations: PC = RPC;...
Page 290 LSL ACC,#1..16 LSL ACC,#1..16 Logical Shift Left SYNTAX OPTIONS OPCODE OBJMODE LSL ACC,#1..16 1111 1111 0011 SHFT Operands Accumulator register #1..16 Shift value Description Perform a logical shift left on the content of the ACC register by the amount specified by the shift value. During the shift, the low order bits of the ACC register are zero filled and the last bit shifted out is stored in the carry flag bit: Last bit out Left shift...
Page 291 LSL ACC,T LSL ACC,T Logical Shift Left by T(3:0) SYNTAX OPTIONS OPCODE OBJMODE LSL ACC,T − 1111 1111 0101 0000 Operands Accumulator register Upper 16 bits of the multiplicand (XT) register Description Perform a logical shift left on the content of the ACC register by the amount specified by the four least significant bits of the T register, T(3:0) = 0…15.
Page 292 LSL AX,#1...16 LSL AX,#1...16 Logical Shift Left SYNTAX OPTIONS OPCODE OBJMODE LSL AX,#1…16 − 1111 1111 100A SHFT Operands Accumulator high (AH) or accumulator low (AL) register #1…16 Shift value Description Perform a logical shift left on the content of the specified AX register (AH or AL) by the amount given “shift value”...
Page 293 LSL AX,T LSL AX,T Logical Shift Left by T(3:0) SYNTAX OPTIONS OPCODE OBJMODE LSL AX,T − 1111 1111 0110 011A Operands Accumulator high (AH) or accumulator low (AL) register Upper 16 bits of the multiplicand (XT) register Description Perform a logical shift left on the content of the specified AX register by the amount specified by the four least significant bits of the T register, T(3:0).
Page 294 LSL64 ACC:P,#1..16 LSL64 ACC:P,#1..16 Logical Shift Left SYNTAX OPTIONS OPCODE OBJMODE LSL64 ACC:P,#1..16 − 0101 0110 1010 SHFT Operands ACC:P Accumulator register (ACC) and product register (P) #1..16 Shift value Description Logical shift left the 64-bit combined value of the ACC:P registers by the amount specified in the shift value field.
Page 295 LSL64 ACC:P,T LSL64 ACC:P,T 64-Bit Logical Shift Left by T(5:0) SYNTAX OPTIONS OPCODE OBJMODE LSL64 ACC:P,T − 0101 0110 0101 0010 Operands ACC:P Accumulator register (ACC) and product register (P) Upper 16 bits of the multiplicand register (XT) Description Logical shift left the 64-bit combined value of the ACC:P registers by the amount specified in the six least significant bits of the T register, T(5:0) = 0…63.
Page 296 LSLL ACC,T LSLL ACC,T Logical Shift Left by T (4:0) SYNTAX OPTIONS OPCODE OBJMODE LSLL ACC,T − 0101 0110 0011 1011 Operands Accumulator register Upper 16 bits of the multiplicand (XT) register Upper 16 bits of the multiplicand register (XT) Description Perform a logical shift left on the content of the ACC register by the amount specified by the five least significant bits of the T register, T(4:0) = 0…31.
Page 297 LSR AX,#1...16 LSR AX,#1...16 Logical Shift Right SYNTAX OPTIONS OPCODE OBJMODE LSR AX,#1…16 − 1111 1111 110A SHFT Operands Accumulator high (AH) or accumulator low (AL) register #1…16 Shift value Description Perform a logical right shift on the content of the specified AX register by the amount given by the “shift value”...
Page 298 LSR AX,T LSR AX,T Logical Shift Right by T(3:0) SYNTAX OPTIONS OPCODE OBJMODE LSR AX,T − 1111 1111 0110 001A Operands Accumulator high (AH) or accumulator low (AL) register Upper 16 bits of the multiplicand (XT) register Description Perform a logical shift right on the content of the specified AX register (AH or AL) as specified by the four least significant bits of the T register, T(3:0).
Page 299 LSR64 ACC:P,#1..16 LSR64 ACC:P,#1..16 64-Bit Logical Shift Right SYNTAX OPTIONS OPCODE OBJMODE LSR64 ACC:P,#1..16 − 0101 0110 1001 SHFT Operands ACC:P Accumulator register (ACC) and product register (P) #1..16 Shift value Description Logical shift right the 64-bit combined value of the ACC:P registers by the amount specified in the shift value field.
Page 300 LSR64 ACC:P,T LSR64 ACC:P,T 64-Bit Logical Shift Right by T(5:0) SYNTAX OPTIONS OPCODE OBJMODE LSR64 ACC:P,T − 0101 0110 0101 1011 Operands ACC:P Accumulator register (ACC) and product register (P) Upper 16 bits of the multiplicand register (XT) Description Logical shift right the 64-bit combined value of the ACC:P registers by the amount specified by the six least significant bits of the T register, T(5:0) = 0…63.
Page 301 LSRL ACC,T LSRL ACC,T Logical Shift Right by T (4:0) SYNTAX OPTIONS OPCODE OBJMODE LSRL ACC,T 0101 0110 0010 0010 − Operands Accumulator register Upper 16 bits of the multiplicand (XT) register Description Perform an logical shift right on the content of the ACC register as specified by the five least significant bits of the T register, T(4:0) = 0…31.
Page 302 MAC P,loc16,0:pma MAC P,loc16,0:pma Multiply and Accumulate SYNTAX OPTIONS OPCODE OBJMODE MAC P,loc16,0:pma − 0001 0100 LLLL LLLL CCCC CCCC CCCC CCCC Operands Product register loc16 Addressing mode (see Chapter 5) Immediate program memory address, access low 64K range of program 0:pma space only (0x000000 to 0x00FFFF) Description...
Page 303 MAC P,loc16,0:pma If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register.
Page 304 MAC P ,loc16,*XAR7/++ MAC P ,loc16,*XAR7/++ Multiply and Accumulate SYNTAX OPTIONS OPCODE OBJMODE MAC P, loc16, *XAR7 0101 0110 0000 0111 1100 0111 LLLL LLLL MAC P, loc16, *XAR7++ 0101 0110 0000 0111 1000 0111 LLLL LLLL Operands Product register loc16 Addressing mode (see Chapter 5) *XAR7...
Page 305 MAC P ,loc16,*XAR7/++ Flags and After the addition, the Z flag is set if the ACC value is zero, else Z is cleared. Modes Modes After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared. If the addition generates a carry, C is set;...
Page 306 MAX AX, loc16 MAX AX, loc16 Find the Maximum SYNTAX OPTIONS OPCODE OBJMODE MAX AX, loc16 0101 0110 0111 001A 0000 0000 LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing modes (see Chapter 5) Description Compare the signed contents of the specified AX register (AH or AL) with the signed content of the location pointed to by the “loc16”...
Page 307 MAXCUL P,loc32 MAXCUL P,loc32 Conditionally Find the Unsigned Maximum SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 0001 MAXCUL P,loc32 − 0000 0000 LLLL LLLL Operands Product register loc32 Addressing mode (see Chapter 5) Description Based on the state of the N and Z flags, conditionally compare the unsigned contents of the P register with the 32-bit, unsigned content of the location pointed to by the “loc32”...
Page 308 MAXCUL P,loc32 Saturate: MOVL @Var64+2,ACC ; Store result into Var64 MOVL @Var64,P 6-151...
Page 309 MAXL ACC,loc32 MAXL ACC,loc32 Find the 32-bit Maximum SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0110 0001 MAXL ACC,loc32 0000 0000 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Compare the content of the ACC register with the location pointed to by the “loc32”...
Page 310 MIN AX, loc16 MIN AX, loc16 Find the Minimum SYNTAX OPTIONS OPCODE OBJMODE MIN AX, loc16 0101 0110 0111 010A 0000 0000 LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing modes (see Chapter 5) Description Compare the signed content of the specified AX register (AH or AL) with the content of the signed location pointed to by the “loc16”...
Page 311 MINCUL P,loc32 MINCUL P,loc32 Conditionally Find the Unsigned Minimum SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 1001 MINCUL P,loc32 − xxxx xxxx LLLL LLLL Operands Product register loc32 Addressing mode (see Chapter 5) Description Based on the state of the N and Z flags, conditionally compare the unsigned contents of the P register with the 32-bit, unsigned content of the location pointed to by the “loc32”...
Page 312 MINL ACC,loc32 MINL ACC,loc32 Find the 32-bit Minimum SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 0000 MINL ACC,loc32 0000 0000 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Compare the content of the ACC register with the location pointed to by the “loc32”...
Page 313 MOV *(0:16bit), loc16 MOV *(0:16bit), loc16 Move Value SYNTAX OPTIONS OPCODE OBJMODE MOV *(0:16bit),loc16 1111 0100 LLLL LLLL CCCC CCCC CCCC CCCC Operands *(0:16bit) Immediate direct memory address, access low 64K range of data space only (0x00000000 to 0x0000FFFF) loc16 Addressing mode (see Chapter 5) Description Move the content of the location pointed to by the “loc16”...
Page 314 MOV ACC,#16bit<<#0..15 MOV ACC,#16bit<<#0..15 Load Accumulator With Shift SYNTAX OPTIONS OPCODE OBJMODE MOV ACC,loc16<<#0..15 − 1111 1111 0010 SHFT CCCC CCCC CCCC CCCC Operands Accumulator register #16bit 16-bit immediate constant value #0..15 Shift value (default is ”<< #0” if no value specified) Description Load the ACC register with the left shifted contents of the 16-bit immediate value.
Page 315 MOV ACC,loc16<<T MOV ACC,loc16<<T Load Accumulator With Shift SYNTAX OPTIONS OPCODE OBJMODE MOV ACC,loc16 << T − 0101 0110 0000 0110 0000 0000 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register, XT(31:16) Description Load the ACC register with the left-shifted contents of the 16-bit location pointed to by the “loc16”...
Page 316 MOV ACC, loc16<<#0..16 MOV ACC, loc16<<#0..16 Load Accumulator With Shift SYNTAX OPTIONS OPCODE OBJMODE MOV ACC,loc16<<#0 − 1000 0101 LLLL LLLL − 1110 0000 LLLL LLLL MOV ACC, loc16<<#1..15 − 0101 0110 0000 0011 0000 SHFT LLLL LLLL − 1110 SHFT LLLL LLLL MOV ACC, loc16<<#16 −...
Page 317 MOV AR6/7, loc16 MOV AR6/7, loc16 Load Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE MOV AR6, loc16 − 0101 1110 LLLL LLLL MOV AR7, loc16 − 0101 1111 LLLL LLLL Operands AR6/7 AR6 or AR7, auxiliary registers loc16 Addressing mode (see Chapter 5) Description Load AR6 or AR7 with the contents of the 16-bit location and leave the upper 16 bits of XAR6 and XAR7 unchanged:...
Page 318 MOV AX, loc16 MOV AX, loc16 Load AX SYNTAX OPTIONS OPCODE OBJMODE MOV AX, loc16 − 1001 001A LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) Description Load accumulator high register (AH) or accumulator low register (AL) register with the 16-bit contents of the location pointed to by the “loc16”...
Page 319 MOV DP, #10bit MOV DP, #10bit Load Data-Page Pointer SYNTAX OPTIONS OPCODE OBJMODE MOV DP, #10bit − 1111 10CC CCCC CCCC Operands Data page register #10bit 10-bit immediate constant value Description Load the data page register with a 10-bit constant leaving the upper 6 bits unchanged: DP(9:0) = 10bit;...
Page 320 MOV IER,loc16 MOV IER,loc16 Load the Interrupt-Enable Register SYNTAX OPTIONS OPCODE OBJMODE MOV IER,loc16 − 0010 0011 LLLL LLLL Operands Interrupt-enable register loc16 Addressing mode (see Chapter 5) Description Enable and disable selected interrupts by loading the content of the location pointed to by the “loc16”...
Page 321 MOV loc16, #16bit MOV loc16, #16bit Save 16-bit Constant SYNTAX OPTIONS OPCODE OBJMODE MOV loc16, #16bit 0010 1000 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) #16bit 16-bit constant immediate value Description Load the location pointed to by the “loc16” addressing mode with the 16-bit constant immediate value: [loc16] = 16bit;...
Page 322 MOV loc16, *(0:16bit) MOV loc16, *(0:16bit) Move Value SYNTAX OPTIONS OPCODE OBJMODE MOV loc16, *(0:16bit) 1111 0101 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) *(0:16bit) Immediate direct memory address, access low 64K range of data space only (0x00000000 to 0x0000FFFF) Description Move the content of the location specified by the constant direct memory...
Page 323 MOV loc16, #0 MOV loc16, #0 Clear 16-bit Location SYNTAX OPTIONS OPCODE OBJMODE MOV loc16, #0 0010 1011 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Immediate constant value of zero Description Load the location pointed to by the “loc16” addressing mode with the value 0x0000: [loc16] = 0x0000;...
Page 324 MOV loc16,ACC << 1..8 MOV loc16,ACC << 1..8 Save Low Word of Shifted Accumulator SYNTAX OPTIONS OPCODE OBJMODE MOV loc16, ACC << 1 1011 0001 LLLL LLLL MOV loc16, ACC << 2..8 0101 0110 0010 1101 0000 0SHF LLLL LLLL −...
Page 325 MOV loc16, ARn MOV loc16, ARn Store 16-bit Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE MOV loc16, ARn − 0111 1nnn LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) AR0 to AR7, lower 16 bits of auxiliary registers Description Load the contents of the 16-bit location with ARn: [loc16] = ARn;...
Page 326 MOV loc16, AX MOV loc16, AX Store AX SYNTAX OPTIONS OPCODE OBJMODE MOV loc16, AX 1001 011A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Description Load the addressed location pointed to by the “loc16” addressing mode with the 16-bit content of the specified AX register (AH or AL): [loc16] = AX;...
Page 327 MOV loc16, AX, COND MOV loc16, AX, COND Store AX Register Conditionally SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0010 101A MOV loc16, AX, COND − 0000 COND LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register COND Conditional codes: COND...
Page 328 MOV loc16, AX, COND Example ; Swap the contents of VarA and VarB if VarB is higher then VarA: AL,@VarA ; AL = VarA, XAR2 points to VarB AH,@VarB ; AH = VarB, XAR2 points to VarA AH,@AL ; Compare AH and AL @VarA,AH,HI ;...
Page 329 MOV loc16,IER MOV loc16,IER Store Interrupt-Enable Register SYNTAX OPTIONS OPCODE OBJMODE MOV loc16,IER − 0010 0000 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Interrupt enable register Description Save the content of the IER register in the location pointed to by the “loc16” addressing mode: [loc16] = IER;...
Page 330 MOV loc16,OVC MOV loc16,OVC Store the Overflow Counter SYNTAX OPTIONS OPCODE OBJMODE MOV loc16,OVC − 0101 0110 0010 1001 0000 0000 LLLL LLLL loc16 Operands Addressing mode (see Chapter 5) Overflow counter Description Store the 6 bits of the overflow counter (OVC) into the upper 6 bits of the location pointed to by the “loc16”...
Page 331 MOV loc16,P MOV loc16,P Store Lower Half of Shifted P Register SYNTAX OPTIONS OPCODE OBJMODE MOV loc16,P 0011 1111 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Product register Description The contents of the P register are shifted by the amount specified in the product shift mode (PM), and the lower half of the shifted value is stored into the 16-bit location pointed to by the “loc16”...
Page 332 MOV loc16, T MOV loc16, T Store the T Register SYNTAX OPTIONS OPCODE OBJMODE MOV, loc16,T − 0010 0001 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register (XT) Description Store the 16-bit T register contents into the location pointed to by the “loc16” addressing mode: [loc16] = T;...
Page 333 MOV OVC, loc16 MOV OVC, loc16 Load the Overflow Counter SYNTAX OPTIONS OPCODE OBJMODE MOV OVC, loc16 − 0101 0110 0000 0010 0000 0000 LLLL LLLL Operands 6-bit overflow counter Description Load the overflow counter (OVC) with the upper 6 bits of the location pointed to by the “loc16”...
Page 334 MOV PH, loc16 MOV PH, loc16 Load the High Half of the P Register SYNTAX OPTIONS OPCODE OBJMODE MOV PH, loc16 − 0010 1111 LLLL LLLL Operands Upper 16 bits of the product register (P) loc16 Addressing mode (see Chapter 5) Description Load the high 16 bits of the P register (PH) with the 16-bit location pointed to by the “loc16”...
Page 335 MOV PL, loc16 MOV PL, loc16 Load the Low Half of the P Register SYNTAX OPTIONS OPCODE OBJMODE MOVL PL, loc16 − 0010 0111 LLLL LLLL Operands Lower 16 bits of the product register (P) loc16 Addressing mode (see Chapter 5) Description Load the high 16 bits of the P register (PL) with the 16-bit location pointed to by the “loc16”...
Page 336 MOV PM, AX MOV PM, AX Load Product Shift Mode SYNTAX OPTIONS OPCODE OBJMODE MOV PM, AX − 0101 0110 0011 100A Operands Accumulator high (AH) or accumulator low (AL) registers. Description Load the product shift mode (PM) bits with the 3 least significant bits of register AX.
Page 337 MOV T, loc16 MOV T, loc16 Load the Upper Half of the XT Register SYNTAX OPTIONS OPCODE OBJMODE MOV T, loc16 − 0010 1101 LLLL LLLL Operands Upper 16 bits of the multiplicand register (XT) loc16 Addressing mode (see Chapter 5) Description Load the T register with the 16-bit contents of the location pointed to by the “loc16”...
Page 338 MOV TL, #0 MOV TL, #0 Clear the Lower Half of the XT Register SYNTAX OPTIONS OPCODE OBJMODE MOV TL, #0 − 0101 0110 0101 0110 Operands Upper 16 bits of the multiplicand register (XT) Immediate constant value of zero Description Load the lower half of the multiplicand register (TL) with zero, leaving the upper half (T) unchanged:...
Page 339 MOV XARn, PC MOV XARn, PC Save the Current Program Counter SYNTAX OPTIONS OPCODE OBJMODE MOV XARn, PC − 0011 1110 0101 1nnn Operands XARn XAR0 to XAR7, 32-bit auxiliary registers loc32 Addressing mode (see Chapter 5) 22-bit program counter Description Load XARn with the contents of the PC: XARn = 0:PC;...
Page 340 MOVA T,loc16 MOVA T,loc16 Load T Register and Add Previous Product SYNTAX OPTIONS OPCODE OBJMODE MOVA, T,loc16 0001 0000 LLLL LLLL Operands Upper 16 bits of the multiplicand register (XT) loc16 Addressing mode (see Chapter 5) Description Load the T register with the 16-bit content of the location pointed to by the “loc16”...
Page 341 MOVA T,loc16 Example ; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 −2 ; Set product shift to >> 2 T,@X2 ; T = X2 P,T,@C2 ;...
Page 342 MOVAD T, loc16 MOVAD T, loc16 Load T Register SYNTAX OPTIONS OPCODE OBJMODE MOVAD T, loc16 1010 0111 LLLL LLLL Operands Upper 16 bits of the multiplicand register (XT) loc16 Addressing mode (see Chapter 5) Note: For this operation, register-addressing modes cannot be used. The modes are: @ARn, @AH, @AL, @PH, @PL, @SP, @T.
Page 343 MOVAD T, loc16 Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ;...
Page 344 MOVB ACC,#8bit MOVB ACC,#8bit Load Accumulator With 8-bit Value SYNTAX OPTIONS OPCODE OBJMODE MOVB ACC,#8bit − 0000 0010 CCCC CCCC Operands Accumulator register #8bit 8-bit immediate unsigned constant value Description Load the ACC register with the specified 8-bit, zero-extended immediate constant: ACC = 0:8bit;...
Page 345 MOVB AR6/7, #8bit MOVB AR6/7, #8bit Load Auxiliary Register With an 8-bit Constant SYNTAX OPTIONS OPCODE OBJMODE MOVB AR6, #8bit − 1101 0110 CCCC CCCC MOVB AR7, #8bit − 1101 0111 CCCC CCCC Operands XARn XAR6 OR XAR7, 32-bit auxiliary registers #8bit 8-bit immediate constant value Description...
Page 346 MOVB AX, #8bit MOVB AX, #8bit Load AX With 8-bit Constant SYNTAX OPTIONS OPCODE OBJMODE MOVB AX, #8bit − 1001 101A CCCC CCCC Operands Accumulator high (AH) or accumulator low (AL) register #8bit 8-bit immediate constant value Description Load accumulator high register (AH) or accumulator low register (AL) with an unsigned 8-bit constant zero extended, leaving the other half of the accumulator register unchanged: AX = 0:8bit;...
Page 347 MOVB AX.LSB, loc16 MOVB AX.LSB, loc16 Load Byte Value SYNTAX OPTIONS OPCODE OBJMODE MOVB AX.LSB, loc16 − 1100 011A LLLL LLLL Operands AX.LS Least significant byte of accumulator high (AH.LSB) or accumulator low (AL.LSB) register loc16 Addressing mode (see Chapter 5) Description Load the least significant byte of the specified AX register (AH.LSB or AL.LSB) with 8 bits from the location pointed to by the “loc16”...
Page 348 MOVB AX.LSB, loc16 Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Swap the byte order in the 32-bit ”Var32” location. ; Before operation: Var32 = B3 | B2 | B1 | B0 ;...
Page 349 MOVB AX.MSB, loc16 MOVB AX.MSB, loc16 Load Byte Value SYNTAX OPTIONS OPCODE OBJMODE MOVB AX.MSB, loc16 − 0011 100A LLLL LLLL Operands AX.MS Most significant byte of accumulator high (AH.MSB) or accumulator low (AL.MSB) register loc16 Addressing mode (see Chapter 5) Description Load the most significant byte of the specified AX register (AH.MSB or AH.LSB) with 8 bits from the location pointed to by the “loc16”...
Page 350 MOVB AX.MSB, loc16 Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Swap the byte order in the 32-bit ”Var32” location. ; Before operation: Var32 = B3 | B2 | B1 | B0 ;...
Page 351 MOVB loc16,#8bit,COND MOVB loc16,#8bit,COND Conditionally Save 8-bit Constant SYNTAX OPTIONS OPCODE OBJMODE MOVB loc16,#8bit,COND − 0101 0110 1011 COND CCCC CCCC LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) #8bit 8-bit immediate constant value COND Conditional codes: COND Syntax Description Flags Tested 0000...
Page 352 MOVB loc16,#8bit,COND Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Calculate: ; if( VarA > 20 ) VarA = 0; @VarA,#20 ; Set flags on (VarA − 20) MOVB @VarA,#0,GT ;...
Page 353 MOVB loc16, AX.LSB MOVB loc16, AX.LSB Store LSB of AX Register SYNTAX OPTIONS OPCODE OBJMODE MOVB loc16, AX.LSB − 0011 110A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) AX.LS Least significant byte of accumulator high (AH.LSB) or accumulator low (AL.LSB) register Description Load 8 bits of the location pointed to by the “loc16”...
Page 354 MOVB loc16, AX.LSB Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Store the 32-bit contents of the ACC into the ; 32-bit contents of ”Var32” location in reverse byte order: ;...
Page 355 MOVB loc16, AX.MSB MOVB loc16, AX.MSB Store MSB of AX Register SYNTAX OPTIONS OPCODE OBJMODE MOVB loc16, AX.MSB − 1100 100A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) AX.MS Most significant byte of accumulator high (AH.MSB) or accumulator low (AL.MSB) register Description Load 8 bits of the location pointed to by the “loc16”...
Page 356 MOVB loc16, AX.MSB Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Store the 32-bit contents of the ACC into the ; 32-bit contents of ”Var32” location in reverse byte order: ;...
Page 357 MOVB XARn, #8bit MOVB XARn, #8bit Load Auxiliary Register With 8-bit Value SYNTAX OPTIONS OPCODE OBJMODE MOVB XAR0…5, #8bit − 1101 0nnn CCCC CCCC MOVB XAR6, #8bit − 1011 1110 CCCC CCCC MOVB XAR7, #8bit − 1011 0110 CCCC CCCC Operands XARn XAR0 to XAR7, 32-bit auxiliary registers...
Page 358 MOVDL XT,loc16 MOVDL XT,loc16 Store XT and Load New XT SYNTAX OPTIONS OPCODE OBJMODE MOVDL XT,loc16 1010 0110 LLLL LLLL Operands Multiplicand register loc32 Addressing mode (see Chapter 5) Note: For this operation, register-addressing modes cannot be used. The modes are: @XARn, @ACC, @P, @XT.
Page 359 MOVH loc16,ACC << 1..8 MOVH loc16,ACC << 1..8 Save High Word of Shifted Accumulator SYNTAX OPTIONS OPCODE OBJMODE MOVH loc16, ACC << 1 1011 0011 LLLL LLLL MOVH loc16, ACC << 2..8 0101 0110 0010 1111 0000 0SHF LLLL LLLL −...
Page 360 MOVH loc16, P MOVH loc16, P Save High Word of the P Register SYNTAX OPTIONS OPCODE OBJMODE MOVH loc16,P 0101 0111 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Product register Description The contents of the P register are shifted by the amount specified in the product shift mode (PM), and the upper half of the shifted value is stored into the 16-bit location pointed to by the “loc16”...
Page 361 MOVL ACC,loc32 MOVL ACC,loc32 Load Accumulator With 32 Bits SYNTAX OPTIONS OPCODE OBJMODE MOVL ACC,loc32 − 0000 0110 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Load the ACC register with the content of the location pointed to by the “loc32”...
Page 362 MOVL ACC,P << PM MOVL ACC,P << PM Load the Accumulator With Shifted P SYNTAX OPTIONS OPCODE OBJMODE MOVL ACC,P << PM − 0001 0110 1010 1100 Note: This instruction is an alias for the ”MOVP T,loc16” operation with “loc16 = @T” addressing mode. Operands Accumulator register Product register...
Page 363 MOVL loc32, ACC MOVL loc32, ACC Store 32-bit Accumulator SYNTAX OPTIONS OPCODE OBJMODE MOVL loc32, ACC − 0001 1110 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Store the contents of the ACC register into the location pointed to by the “loc32”...
Page 364 MOVL loc32,ACC,COND MOVL loc32,ACC,COND Conditionally Store the Accumulator SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0100 1000 MOVL loc32,ACC,COND − 0000 COND LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Accumulator register Conditional codes: COND COND Syntax Description Flags Tested Not Equal To Z = 0 0000...
Page 365 MOVL loc32,ACC,COND Flags and If (COND = true AND loc32 = @ACC), then after the move if bit 31 of Modes ACC is 1, N is set; otherwise N cleared. If (COND = true AND loc32 = @ACC), then after the move if (ACC = 0), then the Z bit is set;...
Page 366 MOVL loc32,P MOVL loc32,P Store the P Register SYNTAX OPTIONS OPCODE OBJMODE MOVL loc32,P − 1010 1001 LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Product register Description Store the P register contents into the location pointed to by the “loc32” addressing mode: [loc32] = P;...
Page 367 MOVL loc32, XARn MOVL loc32, XARn Store 32-bit Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE MOVL loc32, XAR0 − 0011 1010 LLLL LLLL MOVL loc32, XAR1 − 1011 0010 LLLL LLLL MOVL loc32, XAR2 − 1010 1010 LLLL LLLL MOVL loc32, XAR3 −...
Page 368 MOVL loc32,XT MOVL loc32,XT Store the XT Register SYNTAX OPTIONS OPCODE OBJMODE MOVL loc32,XT − 1010 1011 LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Multiplicand register Description Store the T register into 32-bit location pointed to by the “loc32” addressing mode: [loc32] = XT;...
Page 369 MOVL P,ACC MOVL P,ACC Load P From the Accumulator SYNTAX OPTIONS OPCODE OBJMODE MOVL P,ACC − 1111 1111 0101 1010 Operands Product register Accumulator register Description Load the P register with the content of the ACC register: P = ACC; Flags and None Modes...
Page 370 MOVL P,loc32 MOVL P,loc32 Load the P Register SYNTAX OPTIONS OPCODE OBJMODE MOVL P,loc32 − 1010 0011 LLLL LLLL Operands Product register loc32 Addressing mode (see Chapter 5) Description Load the P register with the 32-bit location pointed to by the “loc32” addressing mode: P = [loc32];...
Page 371 MOVL XARn, loc32 MOVL XARn, loc32 Load 32-bit Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE MOVL XAR0, loc32 − 1000 1110 LLLL LLLL MOVL XAR1, loc32 − 1000 1011 LLLL LLLL MOVL XAR2, loc32 − 1000 0110 LLLL LLLL MOVL XAR3, loc32 −...
Page 372 MOVL XARn, #22bit MOVL XARn, #22bit Load 32-bit Auxiliary Register With Constant Value SYNTAX OPTIONS OPCODE OBJMODE MOVL XAR0, #22bit − 1000 1101 00CC CCCC CCCC CCCC CCCC CCCC MOVL XAR1, #22bit − 1000 1101 01CC CCCC CCCC CCCC CCCC CCCC MOVL XAR2, #22bit −...
Page 373 MOVL XT,loc32 MOVL XT,loc32 Load the XT Register SYNTAX OPTIONS OPCODE OBJMODE MOVL XT, loc32 − 1000 0111 LLLL LLLL Operands Upper 16 bits of the multiplicand register (XT) loc32 Addressing mode (see Chapter 5) Description Load the XT register with the 32-bit content of the location pointed to by the “loc32”...
Page 374 MOVP T,loc16 MOVP T,loc16 Load the T Register and Store P in the Accumulator SYNTAX OPTIONS OPCODE OBJMODE MOVP T,loc16 − 0001 0110 LLLL LLLL Operands Upper 16 bits of the multiplicand register (XT) loc16 Addressing mode (see Chapter 5) Description Load the T register with the 16-bit content of the location pointed to by the “loc16”...
Page 375 MOVS T,loc16 MOVS T,loc16 Load T and Subtract P From the Accumulator SYNTAX OPTIONS OPCODE OBJMODE MOVS, T,loc16 0001 0001 LLLL LLLL Operands Upper 16 bits of the multiplicand register (XT) loc16 Addressing mode (see Chapter 5) Description Load the T register with the 16-bit content of the location pointed to by the “loc16”...
Page 376 MOVS T,loc16 Example ; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) ; X2 = X1 ; X1 = X0 −2 ; Set product shift to >> 2 MOVP T,@X2 ;...
Page 377 MOVU ACC,loc16 MOVU ACC,loc16 Load Accumulator With Unsigned Word SYNTAX OPTIONS OPCODE OBJMODE MOVU ACC,loc16 − 0000 1110 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Load the low half of the accumulator (AL) with the 16-bit contents of the addressed location pointed to by the “loc16”...
Page 378 MOVU loc16,OVC MOVU loc16,OVC Store the Unsigned Overflow Counter SYNTAX OPTIONS OPCODE OBJMODE MOVU loc16,OVC − 0101 0110 0010 1000 0000 0000 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Overflow counter Description Store the 6 bits of the overflow counter (OVC) into the lower 6 bits of the location pointed to by the “loc16”...
Page 379 MOVU OVC,loc16 MOVU OVC,loc16 Load Overflow Counter With Unsigned Value SYNTAX OPTIONS OPCODE OBJMODE MOVU OVC,loc16 − 0101 0110 0110 0010 0000 0000 LLLL LLLL Operands 6-bit overflow counter Description Load the overflow counter (OVC) with the lower 6 bits of the location pointed to by the “loc16”...
Page 380 MOVW DP, #16bit MOVW DP, #16bit Load the Entire Data Page SYNTAX OPTIONS OPCODE OBJMODE MOVW DP, #16bit − 0111 0110 0001 1111 CCCC CCCC CCCC CCCC Operands Data page register #16bit 16-bit immediate constant value Description Load the data page register with a 16-bit constant: DP(15:0) = 16bit;...
Page 381 MOVX TL,loc16 MOVX TL,loc16 Load Lower Half of XT With Sign Extension SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0010 0001 MOVX TL,loc16 − xxxx xxxx LLLL LLLL Operands Lower 16 bits of the multiplicand register (XT) loc32 Addressing mode (see Chapter 5) Description Load the lower 16 bits of the multiplicand register (TL) with the 16-bit contents of the location pointed to by the “loc16”...
Page 382 MOVZ ARn, loc16 MOVZ ARn, loc16 Load Lower Half of XARn and Clear Upper Half SYNTAX OPTIONS OPCODE OBJMODE MOVZ AR0…5, loc16 − 0101 1nnn LLLL LLLL MOVZ AR6, loc16 − 1000 1000 LLLL LLLL MOVZ AR7, loc16 − 1000 0000 LLLL LLLL Operands AR0 to AR7, lower 16 bits of auxiliary registers loc16...
Page 383 MOVZ DP, #10bit MOVZ DP, #10bit Load Data Page and Clear High Bits SYNTAX OPTIONS OPCODE OBJMODE MOVZ DP, #10bit − 1011 10CC CCCC CCCC Operands Data page register #10bit 10-bit immediate constant value Description Load the data page register with a 10-bit constant and clear the upper 6 bits: DP(9:0) = 10bit;...
Page 384 MPY ACC,loc16, #16bit MPY ACC,loc16, #16bit 16 X 16-bit Multiply SYNTAX OPTIONS OPCODE OBJMODE MPY ACC, loc16,#16bit − 0011 0100 LLLL LLLL CCCC CCCC CCCC CCCC Operands Accumulator register loc16 Addressing mode (see Chapter 5) #16bit 16-bit immediate constant value Description Load the T register with the 16-bit content of the location pointed to by the “loc16”...
Page 385 MPY ACC, T, loc16 MPY ACC, T, loc16 16 X 16-bit Multiply SYNTAX OPTIONS OPCODE OBJMODE MPY ACC,T,loc16 − 0001 0010 LLLL LLLL Operands Accumulator register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Multiply the signed 16-bit content of the T register by the signed 16-bit contents of the location pointed to by the “loc16”...
Page 386 MPY P,loc16,#16bit MPY P,loc16,#16bit 16 X 16-Bit Multiply SYNTAX OPTIONS OPCODE OBJMODE MPY P,loc16,#16bit − 1000 1100 LLLL LLLL CCCC CCCC CCCC CCCC Operands Product register loc16 Addressing mode (see Chapter 5) #16bit 16-bit immediate constant value Description Multiply the signed 16-bit contents of the location pointed to by the “loc16” addressing mode by the 16-bit immediate value and store the 32-bit result in the P register: P = signed [loc16] * signed 16bit;...
Page 387 MPY P,T,loc16 MPY P,T,loc16 16 X 16 Multiply SYNTAX OPTIONS OPCODE OBJMODE MPY P,T,loc16 − 0011 0011 LLLL LLLL Operands Product register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Multiply the signed 16-bit content of the T register by the signed 16-bit contents of the location pointed to by the “loc16”...
Page 388 MPYA P,loc16,#16bit MPYA P,loc16,#16bit 16 X 16-Bit Multiply and Add Previous Product SYNTAX OPTIONS OPCODE OBJMODE MPYA P,loc16,#16bit − 0001 0101 LLLL LLLL CCCC CCCC CCCC CCCC Operands Product register loc16 Addressing mode (see Chapter 5) #16bit 16-bit immediate constant value Description Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM) bits, to the ACC register.
Page 389 MPYA P,loc16,#16bit Example ; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2), ; C0, C1 and C2 are constants −2 ; Set product shift to >> 2 MOVB ACC,#0 ; Zero ACC P,@X2,#C2 ;...
Page 390 MPYA P,T,loc16 MPYA P,T,loc16 16 X 16-bit Multiply and Add Previous Product SYNTAX OPTIONS OPCODE OBJMODE MPYA P,T,loc16 0001 0111 LLLL LLLL Operands Product register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Add the previous product (stored in the P register), shifted as specified by the product shift mode (PM), to the ACC register.
Page 391 MPYA P,T,loc16 Example ; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) −2 ; Set product shift to >> 2 MOVP T,@X2 ; ACC = P, T = X2 MPYS P,T,@C2 ;...
Page 392 MPYB ACC,T,#8bit MPYB ACC,T,#8bit Multiply by 8-bit Constant SYNTAX OPTIONS OPCODE OBJMODE MPYB ACC,T,#8bit − 0011 0101 CCCC CCCC Operands Accumulator register Multiplicand register #8bit 8-bit immediate constant value Description Multiply the signed 16-bit content of the T register by the unsigned 8-bit constant value zero extended and store the result in the ACC register: ACC = signed T * 0:8bit Flags and...
Page 393 MPYB P,T,#8bit MPYB P,T,#8bit Multiply Signed Value by Unsigned 8-bit Constant SYNTAX OPTIONS OPCODE OBJMODE MPYB P,T,#8bit − 0011 0001 CCCC CCCC Operands Product register Multiplicand register #8bit 8-bit immediate constant value Description Multiply the signed 16-bit content of the T register by the unsigned 8-bit immediate constant value zero extended and store the 32-bit result in the P register: P = signed T * 0:8bit;...
Page 394 MPYS P,T,loc16 MPYS P,T,loc16 16 X 16-bit Multiply and Subtract SYNTAX OPTIONS OPCODE OBJMODE MPYS P,T,loc16 0001 0011 LLLL LLLL Operands Product register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Subtract the previous product (stored in the P register), shifted as specified by the product shift mode (PM), from the ACC register.
Page 395 MPYS P,T,loc16 Example ; Calculate using 16-bit multiply: ; Y = (X0*C0) >> 2) + (X1*C1 >> 2) + (X2*C2 >> 2) −2 ; Set product shift to >> 2 MOVP T,@X2 ; ACC = P, T = X2 MPYS P,T,@C2 ;...
Page 396 MPYU P,T,loc16 MPYU P,T,loc16 Unsigned 16 X 16 Multiply SYNTAX OPTIONS OPCODE OBJMODE MPYU P,T,loc16 − 0011 0111 LLLL LLLL Operands Product register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Multiply the signed 16-bit content of the T register by the signed 16-bit contents of the location pointed to by the “loc16”...
Page 397 MPYU ACC,T,loc16 MPYU ACC,T,loc16 16 X 16-bit Unsigned Multiply SYNTAX OPTIONS OPCODE OBJMODE MPYU ACC,T,loc16 − 0011 0110 LLLL LLLL Operands Accumulator register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Multiply the unsigned 16-bit content of the T register by the unsigned 16-bit content of the location pointed to by the “loc16”...
Page 398 MPYXU ACC, T, loc16 MPYXU ACC, T, loc16 Multiply Signed Value by Unsigned Value SYNTAX OPTIONS OBJMODE MPYXU ACC, T, loc16 − 0011 0000 LLLL LLLL Operands Accumulator register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Multiply the signed 16-bit content of the T register by the unsigned 16-bit content of the location pointed to by the “loc16”...
Page 399 MPYXU P,T,loc16 MPYXU P,T,loc16 Multiply Signed Value by Unsigned Value SYNTAX OPTIONS OPCODE OBJMODE MPYXU P,T,loc16 − 0011 0010 LLLL LLLL Operands Product register Multiplicand register loc16 Addressing mode (see Chapter 5) Description Multiply the signed 16-bit content of the T register by the signed 16-bit contents of the location pointed to by the “loc16”...
Page 400 NASP NASP Unalign Stack Pointer SYNTAX OPTIONS OPCODE OBJMODE NASP − 0111 0110 0001 0111 Operands None Description If the SPA bit is 1, the NASP instruction decrements the stack pointer (SP) by 1 and then clears the SPA status bit. This undoes a stack pointer alignment performed earlier by the ASP instruction.
Page 401 NEG ACC NEG ACC Negate Accumulator SYNTAX OPTIONS OPCODE OBJMODE NEG ACC − 1111 1111 0101 0100 Operands Accumulator register Description Negate the contents of the ACC register: if(ACC = 0x8000 0000) V = 1; if(OVM = 1) ACC = 0x7FFF FFFF; else ACC = 0x8000 0000;...
Page 402 NEG AX NEG AX Negate AX Register SYNTAX OPTIONS OPCODE OBJMODE NEG AX − 1111 1111 0101 110A Operands Accumulator high (AH) or accumulator low (AL) register Description Replace the contents of the specified AX register with the negative of AX: if(AX = 0x8000) AX = 0x8000;...
Page 403 NEG64 ACC:P NEG64 ACC:P Negate Accumulator Register and Product Register SYNTAX OPTIONS OPCODE OBJMODE NEG64 ACC:P − 0101 0110 0101 1000 Operands ACC:P Accumulator register (ACC) and product register (P) Description Negate the 64-bit content of the combined ACC:P registers: if(ACC:P = 0x8000 0000 0000 0000) V = 1;...
Page 404 NEG64 ACC:P Example ; Negate the contents of the 64-bit Var64 and saturate: MOVL ACC,@Var64+2 ; Load ACC with high 32-bits of Var64 MOVL P,@Var64+0 ; Load P with low 32-bits of Var64 SETC ; Enable overflow mode (saturate) NEG64 ACC:P ;...
Page 405 NEGTC ACC NEGTC ACC If TC is Equivalent to 1, Negate ACC SYNTAX OPTIONS OPCODE OBJMODE NEGTC ACC − 0101 0110 0011 0010 Operands Accumulator register Description Based on the state of the test control (TC) bit, conditionally replace the content of the ACC register with its negative: if( TC = 1 ) if(ACC = 0x8000 0000)
Page 406 NEGTC ACC Example ; Calculate signed: Quot16 = Num16/Den16, Rem16 = Num16%Den16 CLRC ; Clear TC flag, used as sign flag ACC,@Den16 << 16 ; AH = Den16, AL = 0 ABSTC ; Take abs value, TC = sign ^ TC T,@AH ;...
Page 407 NOP {*ind}{ARPn} NOP {*ind}{ARPn} No Operation With Optional Indirect Address Modification SYNTAX OPTIONS OPCODE OBJMODE NOP {*ind}{,ARPn} 0111 0111 LLLL LLLL Operands {*ind} Indirect address mode (see chapter 5) ARPn Auxiliary register pointer (ARP0 to ARP7) Description Modify the indirect address operand as specified and change the auxiliary register pointer (ARP) to the given auxiliary register.
Page 408 NORM ACC, *ind NORM ACC, *ind Normalize ACC and Modify Selected Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE NORM ACC, * 0101 0110 0010 0100 NORM ACC, *++ 0101 0110 0101 1010 NORM ACC, *− − 0101 0110 0010 0000 NORM ACC, *0++ 0101 0110 0111 0111 NORM ACC, *0−...
Page 409 NORM ACC, *ind Example ; Normalize the contents of VarA, ; XAR2 will contain shift value at the end of the operation: MOVL ACC,@VarA ; ACC = VarA MOVB XAR2,#0 ; Initialize XAR2 to zero *,ARP2 ; Set ARP pointer to point to XAR2 Skip,EQ ;...
Page 410 NORM ACC,XARn++/− − NORM ACC,XARn++/−− Normalize ACC and Modify Selected Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE NORM ACC,XARn++ 1111 1111 0111 1nnn NORM ACC,XARn− − 1111 1111 0111 0nnn Operands Accumulator register XARn XAR0 to XAR7, auxiliary registers post incremented or decremented ++/−−...
Page 411 NORM ACC,XARn++/− − Example ; Normalize the contents of VarA, ; XAR2 will contain shift value at the end of the operation: MOVL ACC,@VarA ; ACC = VarA MOVB XAR2,#0 ; Initialize XAR2 to zero Skip,EQ ; Skip if ACC value is zero ;...
Page 412 NOT ACC NOT ACC Complement Accumulator SYNTAX OPTIONS OPCODE OBJMODE NOT ACC − 1111 1111 0101 0101 Operands Accumulator register Description The content of the ACC register is replaced with its complement: ACC = ACC XOR 0xFFFFFFFF; Flags and After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Modes After the operation, the Z flag is set if the ACC is zero, else Z is cleared.
Page 413 NOT AX NOT AX Complement AX Register SYNTAX OPTIONS OPCODE OBJMODE NOT AX − 1111 1111 0101 111A Operands Accumulator high (AH) or accumulator low (AL) register Description Replace the contents of the specified AX register (AH or AL) with its complement: AX = AX XOR 0xFFFF;...
Page 414 OR ACC, loc16 OR ACC, loc16 Bitwise OR SYNTAX OPTIONS OPCODE OBJMODE OR ACC, loc16 1010 1111 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Perform a bitwise OR operation on the ACC register with the zero-extended content of the location pointed to by the “loc16”...
Page 415 OR ACC,#16bit << #0..16 OR ACC,#16bit << #0..16 Bitwise OR SYNTAX OPTIONS OPCODE OBJMODE OR ACC,#16bit << #0..15 − 0011 1110 0001 SHFT CCCC CCCC CCCC CCCC OR ACC,#16bit << #16 − 0101 0110 0100 1010 CCCC CCCC CCCC CCCC Operands Accumulator register #16bit...
Page 416 OR AX, loc16 OR AX, loc16 Bitwise OR SYNTAX OPTIONS OPCODE OBJMODE OR AX, loc16 − 1100 101A LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) Description Perform a bitwise OR operation on the specified AX register with the contents of the location pointed to by the “loc16”...
Page 417 OR IER,#16bit OR IER,#16bit Bitwise OR SYNTAX OPTIONS OPCODE OBJMODE OR IER,#16bit − 0111 0110 0010 0011 CCCC CCCC CCCC CCCC Operands Interrupt enable register #16bit- 16-bit immediate constant value Mask Description Enable specific interrupts by performing a bitwise OR operation with the IER register and the 16-bit immediate value.
Page 418 OR IFR,#16bit OR IFR,#16bit Bitwise OR SYNTAX OPTIONS OPCODE OBJMODE OR IFR,#16bit − 0111 0110 0010 0111 CCCC CCCC CCCC CCCC Operands Interrupt flag register #16bit 16-bit immediate constant value Description Enable specific interrupts by performing a bitwise OR operation with the IFR register and the 16-bit immediate value.
Page 419 OR loc16,#16bit OR loc16,#16bit Bitwise OR SYNTAX OPTIONS OPCODE OBJMODE OR loc16,#16bit − 0001 1010 LLLL LLLL CCCC CCCC CCCC CCCC Addressing mode (see Chapter 5) Operands loc16 #16bit 16-bit immediate constant value Perform a bitwise OR operation on the content of the location pointed to by Description the “loc16”...
Page 420 OR loc16, AX OR loc16, AX Bitwise OR SYNTAX OPTIONS OPCODE OBJMODE OR loc16, AX − 1001 100A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Aaccumulator high (AH) or accumulator low (AL) register Description Perform a bitwise OR operation on the contents of location pointed to by the “loc16”...
Page 421 ORB AX,#8bit ORB AX,#8bit Bitwise OR 8-bit Value SYNTAX OPTIONS OPCODE OBJMODE ORB AX, #8bit − 0101 000A CCCC CCCC Operands Accumulator high (AH) or accumulator low (AL) register #8bit 8-bit immediate constant value Description Perform a bitwise OR operation on the specified AX register with the 8-bit unsigned immediate constant zero extended.
Page 422 OUT *(PA),loc16 OUT *(PA),loc16 Output Data to Port SYNTAX OPTIONS OPCODE OBJMODE OUT *(PA),loc16 − 1011 1100 LLLL LLLL CCCC CCCC CCCC CCCC Operands *(PA) Immediate I/O space memory address loc16 Addressing mode (see Chapter 5) Description Store the 16-bit value from the location pointed to by the “loc16” addressing mode into the I/O space location pointed to by the *(PA) operand): IOspace[0x0000PA] = [loc16];...
Page 423 OUT *(PA),loc16 @AL,*(IORegC) ; AL = IOspace[IORegC] @AL,#0x2000 ; Set flags on (AL − 0x2000) $10,NEQ ; Branch if not equal @AL,#0 ; AL = 0 UOUT *(IORegC),@AL ; IOspace[IORegC] = AL $10: 6-266...
Page 424 POP ACC POP ACC Pop Top of Stack to Accumulator SYNTAX OPTIONS OPCODE OBJMODE POP ACC − 0001 1110 1011 1110 Operands Accumulator Description Predecrement SP by 2. Load ACC with the 32-bit value pointed to by SP: −= 2; ACC = [SP];...
Page 425 POP ARn:ARm POP ARn:ARm Pop Top of Stack to 16-bit Auxiliary Registers SYNTAX OPTIONS OPCODE OBJMODE POP AR1:AR0 − 0111 0110 0000 0111 − POP AR3:AR2 0111 0110 0000 0101 POP AR5:AR4 − 0111 0110 0000 0110 Operands ARn: AR1:AR0 or AR3:AR2 or AR5:AR4 auxiliary registers Description AR1:AR0 or AR3:AR2 or AR5:AR4 Predecrement SP by 2.
Page 426 POP AR1H:AR0H POP AR1H:AR0H Pop Top of Stack to Upper Half of Auxiliary Registers SYNTAX OPTIONS OPCODE OBJMODE POP AR1H:AR0H − 0000 0000 0000 0011 Operands AR1H: Upper 16-bits of XAR1 and XAR0 auxiliary registers AR0H Description Predecrement SP by 2. Load the contents of AR0H with the value pointed to by SP and AR1H with the value pointed to by SP+1.
Page 427 POP DBGIER POP DBGIER Pop Top of Stack to DBGIER SYNTAX OPTIONS OPCODE OBJMODE POP DBGIER − 0111 0110 0001 0010 Operands DBGIER Debug interrupt-enable register Description Predecrement SP by 1. Load the contents of DBGIER with the value pointed to by SP: −= 1;...
Page 428 POP DP POP DP Pop Top of Stack to the Data Page SYNTAX OPTIONS OPCODE OBJMODE POP DP − 0111 0110 0000 0011 Operands Data-page register Description Predecrement SP by 1. Load the contents of DP with the value pointed to by SP −= 1;...
Page 429 POP DP:ST1 POP DP:ST1 Pop Top of Stack to DP and ST1 SYNTAX OPTIONS OPCODE OBJMODE POP DP:ST1 − 0111 0110 0000 0001 Operands DP:S data page register and status register 1 Description Predecrement SP by 2. Load ST1 with the value pointed to by SP and load DP with the value pointed to by SP+1: SP −= 2;...
Page 430 POP IFR POP IFR Pop Top of Stack to IFR SYNTAX OPTIONS OPCODE OBJMODE POP IFR − 0000 0000 0000 0010 Operands Interrupt flag register Description Predecrement SP by 1. Load the contents of IFR with the value pointed to by SP −= 1;...
Page 431 POP loc16 POP loc16 Pop Top of Stack SYNTAX OPTIONS OPCODE OBJMODE POP loc16 − 0010 1010 LLLL LLLL Operands loc16 Addressing mode (See Chapter 5) Description Predecrement SP by 1. Load the contents of loc16 with the 16-bit value pointed to by SP.
Page 432 POP P POP P Pop top of Stack to P SYNTAX OPTIONS OPCODE OBJMODE POP P − 0111 0110 0001 0001 Operands Product register Description Predecrement SP by 2. Load P with the 32-bit value pointed to by SP: SP −= 2; = [SP];...
Page 433 POP RPC POP RPC Pop RPC Register From Stack SYNTAX OPTIONS OPCODE OBJMODE POP RPC − 0000 0000 0000 0111 Operands Return program counter register Description Predecrement SP by 2. Load the contents of RPC with the value pointed to by SP: SP −= 2;...
Page 434 POP ST0 POP ST0 Pop Top of Stack to ST0 SYNTAX OPTIONS OPCODE OBJMODE POP ST0 − 0111 0110 0001 0011 Operands status register 0 Description Predecrement SP by 1. Load the contents of ST0 with the value pointed to by SP −= 1;...
Page 435 POP ST1 POP ST1 Pop Top of Stack to ST1 SYNTAX OPTIONS OPCODE OBJMODE POP ST1 − 0111 0110 0000 0000 Operands Status register 1 Description Predecrement SP by 1. Load the contents of ST0 with the value pointed to by SP −= 1;...
Page 436 POP T:ST0 POP T:ST0 Pop Top of Stack to T and ST0 SYNTAX OPTIONS OPCODE OBJMODE POP T:ST0 − 0111 0110 0001 0101 Operands T:ST0 The upper 16-bits of the multiplicand register and status register 0 Description Predecrement SP by 2. Load ST0 with the value pointed to by SP and load T with the value pointed to by SP+1.
Page 437 POP XARn POP XARn Pop Top of Stack to 32-bit Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE POP XAR0 − 0011 1010 1011 1110 POP XAR1 − 1011 0010 1011 1110 POP XAR2 − 1010 1010 1011 1110 POP XAR3 − 1010 0010 1011 1110 POP XAR4 −...
Page 438 POP XT POP XT Pop Top of Stack to XT SYNTAX OPTIONS OPCODE OBJMODE POP XT − 1000 0111 1011 1110 Operands Multiplicand register Description Predecrement SP by 2. Load XT with the 32-bit value pointed to by SP: SP −= 2; = [SP];...
Page 439 PREAD loc16,*XAR7 PREAD loc16,*XAR7 Read From Program Memory SYNTAX OPTIONS OPCODE OBJMODE PREAD loc16,*XAR7 0010 0100 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) *XAR7 Indirect program−memory addressing using auxiliary register XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) Load the data memory−location pointed to by the “loc16”...
Page 440 PREAD loc16,*XAR7 MOVL XAR2,#Array2 ; XAR2 = pointer to Array2 #(N−1) ; Repeat next instruction N times ||PREAD *XAR2++,*XAR7 ; Array2[i] = Array1[i], ; i++ 6-283...
Page 441 PUSH ACC PUSH ACC Push Accumulator Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH ACC − 0001 1110 1011 1101 Note: This instruction is an alieas for the MOV*SP++, ACC instruction. Operands Accumulator register Description Push the 32-bit contents of ACC onto the stack pointed to by SP. Post-increment SP by 2: [SP] = ACC;...
Page 442 PUSH ARn:ARm PUSH ARn:ARm Push 16-bit Auxiliary REgisters Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH AR1:AR0 − 0111 0110 0000 1101 PUSH AR3:AR2 − 0111 0110 0000 1111 PUSH AR5:AR4 − 0111 0110 0000 1100 Operands ARn: AR1:AR0 or AR3:AR2 or AR5:AR4 auxiliary registers Description Push the contents of two 16-bit auxiliary registers (ARn and ARm) onto the stack pointed to by SP.
Page 443 PUSH AR1H:AR0H PUSH AR1H:AR0H Push AR1H and Ar0H Registers on Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH AR1H:AR0H − 0000 0000 0000 0101 Operands Upper 16-bits of XAR1 and XAR0 auxiliary registers AR1H: AR0H Description Push the contents of AR0H followed by the contents of AR1H onto the stack pointed to by SP.
Page 444 PUSH DBGIER PUSH DBGIER Push DBGIER Register Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH DBGIER − 0111 0110 0000 1110 Operands DBGIER Debug interrupt enable register Description Push the 16-bit contents of DBGIER onto the stack pointed to by SP. Post-increment SP by 1: [SP] = DBGIER;...
Page 445 PUSH DP PUSH DP Push DP Register Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH DP − 0111 0110 0000 1011 Operands Data-page register Description Push the 16-bit contents of DP onto the stack pointed to by SP. Post-increment SP by 1: [SP] = DP;...
Page 446 PUSH DP:ST1 PUSH DP:ST1 Push DP and ST1 Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH DP:ST1 − 0111 0110 0000 1001 Operands DP:ST1 Data-page register and status register 1 Description Push the 16- bit contents of ST1 followed by the 16-bit contents of DP onto the stack pointed to by SP.
Page 447 PUSH IFR PUSH IFR Push IFR Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH IFR − 0111 0110 0000 1010 Operands Interrupt flag register Description Push the 16-bit contents of IFR onto the stack pointed to by SP. Post-increment SP by 1: [SP] = IFR;...
Page 448 PUSH loc16 PUSH loc16 Push 16-bit Value on Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH loc16 − 0010 0010 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Description Push a 16-bit value pointed to by the “loc16” operand on the stack pointed to by SP.
Page 449 PUSH P PUSH P Push P Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH P − 0111 0110 0001 1101 Operands Product register Description Push the 32-bit contents of P onto the stack pointed to by SP Post-increment SP by 2: [SP] = P;...
Page 450 PUSH RPC PUSH RPC Push RPC Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH RPC − 0000 0000 0000 0100 Operands Return program counter register Description Push the contents of the RPC register onto the stack pointed to by SP. Post-increment SP by 2: [SP] = RPC;...
Page 451 PUSH ST0 PUSH ST0 Push ST0 Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH ST0 − 0111 0110 0001 1000 Operands Status register 0 Description Push the 16-bit contents of ST0 onto the stack pointed to by SP. Post-increment SP by 1: [SP] = ST0;...
Page 452 PUSH ST1 PUSH ST1 Push ST1 Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH ST1 − 0111 0110 0000 1000 Operands Status register 1 Description Push the 16-bit contents of ST1 onto the stack pointed to by SP. Post-increment SP by 1: [SP] = ST1;...
Page 453 PUSH T:ST0 PUSH T:ST0 Push T and ST0 Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH T:ST0 − 0111 0110 0001 1001 Operands T:ST0 The upper 16-bits of the multiplicand register and status register 0 Description Push the 16- bit contents of ST0 followed by the 16-bit contents of T onto the stack pointed to by SP.
Page 454 PUSH XARn PUSH XARn Push 32-bit Auxiliary Register Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH XAR0 − 0011 1010 1011 1101 PUSH XAR1 − 1011 0010 1011 1101 PUSH XAR2 − 1010 1010 1011 1101 PUSH XAR3 − 1010 0010 1011 1101 PUSH XAR4 −...
Page 455 PUSH XT PUSH XT Push XT Onto Stack SYNTAX OPTIONS OPCODE OBJMODE PUSH XT − 1010 1011 1011 1101 Operands Multiplicand register Description Push the 32-bit contents of XT onto the stack pointed to by SP. Post-increment SP by 2: [SP] = XT;...
Page 456 PWRITE *XAR7,loc16 PWRITE *XAR7,loc16 Write to Program Memory SYNTAX OPTIONS OPCODE OBJMODE PWRITE *XAR7, loc16 0010 0110 LLLL LLLL Operands *XAR7 Indirect program−memory addressing using auxiliary register XAR7, can access full 4Mx16 program space range (0x000000 to 0x3FFFFF) loc16 Addressing mode (see Chapter 5) Description Load the program−memory location pointed to by the ”*XAR7”...
Page 457 QMACL P,loc32,*XAR7/++ QMACL P,loc32,*XAR7/++ Signed 32 X 32-bit Multiply and Accumulate (Upper Half) SYNTAX OPTIONS OPCODE OBJMODE QMACL P,loc32,*XAR7 0101 0110 0100 1111 1100 0111 LLLL LLLL QMACL P,loc32,*XAR7++ 0101 0110 0100 1111 1000 0111 LLLL LLLL Operands Product register loc32 Addressing mode (see Chapter 5) Note:...
Page 458 QMACL P,loc32,*XAR7/++ If overflow mode bit is set; then the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register.
Page 459 QMPYAL P,XT,loc32 QMPYAL P,XT,loc32 Signed 32-bit Multiply (Upper Half) and Add Previous P SYNTAX OPTIONS OPCODE OBJMODE QMPYAL P,XT,loc32 − 0101 0110 0100 0110 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Signed 32-bit x 32-bit multiply and accumulate the previous product.
Page 460 QMPYAL P,XT,loc32 Example ; Calculate signed result: ; Y32 = (X0*C0 + X1*C1 + X2*C2) >> (32 + 2) −2 ; Set product shift mode to “>> 2” ZAPA ; Zero ACC, P, OVC MOVL XT,@X0 ; XT = X0 QMPYL P,XT,@C0 = high 32−bits of (X0*C0)
Page 461 QMPYL P,XT,loc32 QMPYL P,XT,loc32 Signed 32 X 32-bit Multiply (Upper Half) SYNTAX OPTIONS OPCODE OBJMODE QMPYL P,XT,loc32 − 0101 0110 0110 0111 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the “loc32”...
Page 462 QMPYL ACC,XT,loc32 QMPYL ACC,XT,loc32 Signed 32 X 32-bit Multiply (Upper Half) SYNTAX OPTIONS OPCODE OBJMODE QMPYL ACC,XT,loc32 − 0101 0110 0110 0011 0000 0000 LLLL LLLL Operands Product register Multiplicand register Accumulator register Description Multiply the signed 32-bit content of the XT register by the signed 32-bit content of the location pointed to by the “loc32”...
Page 463 QMPYSL P,XT,loc32 QMPYSL P,XT,loc32 Signed 32-bit Multiply (Upper Half) and Subtract Previous P SYNTAX OPTIONS OPCODE OBJMODE QMPYSL P,XT,loc32 − 0101 0110 0100 0101 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Signed 32-bit x 32-bit multiply and subtract the previous product.
Page 464 QMPYSL P,XT,loc32 Example ; Calculate signed result: ; Y32 = −(X0*C0 + X1*C1 + X2*C2) >> (32 + 2) −2 ; Set product shift mode to “>> 2” ZAPA ; Zero ACC, P, OVC MOVL XT,@X0 ; XT = X0 QMPYL P,XT,@C0 = high 32−bits of (X0*C0)
Page 465 QMPYUL P,XT,loc32 QMPYUL P,XT,loc32 Unsigned 32 X 32-bit Multiply (Upper Half) SYNTAX OPTIONS OPCODE OBJMODE QMPYUL P,XT,loc32 − 0101 0110 0100 0111 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Multiply the unsigned 32-bit content of the XT register by the unsigned 32-bit content of the location pointed to by the “loc32”...
Page 466 QMPYXUL P,XT,loc32 QMPYXUL P,XT,loc32 Signed X Unsigned 32-bit Multiply (Upper Half) SYNTAX OPTIONS OPCODE OBJMODE QMPYXUL P,XT,loc32 − 0101 0110 0100 0010 0000 0000 LLLL LLLL Operands Product register Multiplicand register loc32 Addressing mode (see Chapter 5) Description Multiply the signed 32-bit content of the XT register by the unsigned 32-bit content of the location pointed to by the “loc32”...
Page 467 ROL ACC ROL ACC Rotate Accumulator Left SYNTAX OPTIONS OPCODE OBJMODE ROL ACC 1111 1111 0101 0011 Operands Accumulator register Description Rotate the content of the ACC register left by one bit, filling bit 0 with the content of the carry flag and loading the carry flag with the bit shifted out: Rotate Left Flags and After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
Page 468 ROR ACC ROR ACC Rotate Accumulator Right SYNTAX OPTIONS OPCODE OBJMODE ROR ACC 1111 1111 0101 0010 Operands Accumulator register Description Rotate the content of the ACC register right by one bit, filling bit 31 with the content of the carry flag and loading the carry flag with the bit shifted out: Rotate Right Flags and After the operation, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
Page 469 RPT #8bit/loc16 RPT #8bit/loc16 Repeat Next Instruction SYNTAX OPTIONS OPCODE OBJMODE RPT #8bit − 1111 0110 CCCC CCCC RPT loc16 − 1111 0111 LLLL LLLL Operands #8bit 8-bit constant immediate value (0 to 255 range) loc16 Addressing mode (see Chapter 5) Description Repeat the next instruction.
Page 470 SAT ACC SAT ACC Saturate Accumulator SYNTAX OPTIONS OPCODE OBJMODE SAT ACC − 1111 1111 0101 0111 Operands Accumulator register Description Saturate the ACC register to reflect the net overflow represented in the 6-bit overflow counter (OVC): if( OVC > 0 ) ACC = 0x7FFF FFFF;...
Page 471 SAT64 ACC:P SAT64 ACC:P Saturate 64-bit Value ACC:P SYNTAX OPTIONS OPCODE OBJMODE SAT64 ACC:P − 0101 0110 0011 1110 Operands ACC:P Accumulator register (ACC) and product register (P) Description Saturate the 64-bit content of the combined ACC:P registers to reflect the net overflow represented in the overflow counter (OVC): if(OVC >...
Page 472 SAT64 ACC:P Example ; Add 64-bit VarA, VarB and VarC, sat and store result in VarD: ; Clear overflow counter MOVL P,@VarA+0 ; Load P with low 32-bits of VarA ADDUL P,@VarB+0 ; Add to P unsigned low 32-bits of VarB ADDUL P,@VarC+0 ;...
Page 473 SB 8bitOffset,COND SB 8bitOffset,COND SYNTAX OPTIONS OPCODE OBJMODE SB 8bitOffset,COND − 0110 COND CCCC CCCC Operands 8bitOffset 8-bit signed immediate constant offset value (−128 to +127 range) COND Conditional codes: COND Syntax Description Flags Tested 0000 Not Equal To Z = 0 0001 Equal To Z = 1...
Page 474 SBBU ACC,loc16 SBBU ACC,loc16 Subtract Unsigned Value Plus Inverse Borrow SYNTAX OPTIONS OPCODE OBJMODE SBBU ACC,loc16 − 0001 1101 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Subtract the 16-bit contents of the location pointed to by the “loc16” addressing mode, zero extended, and subtract the compliment of the carry flag bit from the ACC register: ACC = ACC −...
Page 475 SBF 8bitOffset,EQ/NEQ/TC/NTC SBF 8bitOffset,EQ/NEQ/TC/NTC Short Branch Fast SYNTAX OPTIONS OPCODE OBJMODE SBF 8bitOffset,EQ − 1110 1100 CCCC CCCC SBF 8bitOffset,NEQ − 1110 1101 CCCC CCCC SBF 8bitOffset,TC − 1110 1110 CCCC CCCC SBF 8bitOffset,NTC − 1110 1111 CCCC CCCC Operands 8bitOffset 8-bit signed immediate constant offset value (−128 to +127 range) Description Flags Tested...
Page 476 SBRK #8bit SBRK #8bit Subtract From Current Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE SBRK,#8bit − 1111 1101 CCCC CCCC Operands #8bit 8-bit constant immediate value Description Subtract the 8-bit unsigned constant from the XARn register pointed to by ARP: XAR(ARP) = XAR(ARP) − 0:8bit; Flags and The 3-bit ARP points to the current valid auxiliary register, XAR0 to XAR7.
Page 477 SETC Mode SETC Mode Set Multiple Status Bits SYNTAX OPTIONS OPCODE OBJMODE SETC Mode − 0011 1011 CCCC CCCC SETC SXM − 0011 1011 0000 0001 SETC OVM − 0011 1011 0000 0010 SETC TC − 0011 1011 0000 0100 SETC C −...
Page 478 SETC Mode Example ; Modify flag settings: SETC INTM,DBGM ; Set INTM and DBGM bits to 1 CLRC TC,C,SXM,OVM ; Clear TC, C, SXM, OVM bits to 0 CLRC #0xFF ; Clear all bits to 0 SETC #0xFF ; Set all bits to 1 SETC C,SXM,TC,OVM ;...
Page 479 SETC M0M1MAP SETC M0M1MAP Set the M0M1MAP Status Bit SYNTAX OPTIONS OPCODE OBJMODE SETC M0M1MAP − 0101 0110 0001 1010 Operands M0M1MAP Status bit Description Set the M0M1MAP status bit, configuring the mapping of the M0 and M1 memory blocks for C28x/C2XLP operation. The memory blocks are mapped as follows: M0M1MAP bit Data Space...
Page 480 SETC OBJMODE SETC OBJMODE Set the OBJMODE Status Bit SYNTAX OPTIONS OPCODE OBJMODE SETC OBJMODE − 0101 0110 0001 1111 Operands OBJMODE Status bit Description Set the OBJMODE status bit, putting the device in C28x object mode (supports C2XLP source): Flags and Set the OBJMODE bit.
Page 481 SETC XF SETC XF Set XF Bit and Output Signal SYNTAX OPTIONS OPCODE OBJMODE SETC XF − 0101 0110 0010 0110 Operands Status bit and output signal Description Set the XF status bit and pull the corresponding output signal high. Flags and The XF status bit is set.
Page 482 SFR ACC,#1..16 SFR ACC,#1..16 Shift Accumulator Right SYNTAX OPTIONS OPCODE OBJMODE SFR ACC,#1..16 1111 1111 0100 SHFT Operands Accumulator register #1..16 Shift value Description Right shift the content of the ACC register by the amount specified in the shift field. The type of shift (arithmetic or logical) is determined by the state of the sign extension mode (SXM) bit: if(SXM = 1) // sign extension mode enabled...
Page 483 SFR ACC,T SFR ACC,T Shift Accumulator Right SYNTAX OPTIONS OPCODE OBJMODE SFR ACC,T − 1111 1111 0101 0001 Operands Accumulator register Upper 16-bits of the multiplicand (XT) register Description Right shift the content of the ACC register by the amount specified in the four least significant bits of the T register, T(3:0) = 0..15.
Page 484 SPM shift SPM shift Set Product Mode Shift Bits SYNTAX OPTIONS OPCODE OBJMODE SPM +1 − 1111 1111 0110 1000 SPM 0 − 1111 1111 0110 1001 SPM −1 − 1111 1111 0110 1010 SPM −2 − 1111 1111 0110 1011 SPM −3 −...
Page 485 SPM shift Example ; Calculate: Y32 = M16*X16 >> 4 + B32 CLRC AMODE ; Make sure AMODE = 0 −4 ; Set product shift mode to “>> 4” T,@X16 = X16 P,XT,@M16 = X16*M16 MOVL ACC,@B32 ; ACC = B32 ADDL ACC,P <<...
Page 486 SQRA loc16 SQRA loc16 Square Value and Add P to ACC SYNTAX OPTIONS OPCODE OBJMODE SQRA loc16 0101 0110 0001 0101 0000 0000 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Description Add the previous product (stored in the P register), shifted by the amount specified by the product shift mode (PM), to the ACC register.
Page 487 SQRA loc16 Example ; Calculate sum of squares using 16-bit multiply: ; int16 X[N] ; Data information ; sum = 0; ; for(i=0; i < N; i++) sum = sum + (X[i] * X[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X −5 ;...
Page 488 SQRS loc16 SQRS loc16 Square Value and Subtract P From ACC SYNTAX OPTIONS OPCODE OBJMODE SQRS loc16 0101 0110 0001 0001 xxxx xxxx LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Description Subtract the previous product (stored in the P register), shifted by the amount specified by the product shift mode (PM), from the ACC register.
Page 489 SQRS loc16 Example ; Calculate sum of negative squares using 16-bit multiply: ; int16 X[N] ; Data information ; sum = 0; ; for(i=0; i < N; i++) sum = sum − (X[i] * X[i]) >> 5; MOVL XAR2,#X ; XAR2 = pointer to X −5 ;...
Page 490 SUB ACC,loc16 << #0...16 SUB ACC,loc16 << #0...16 Subtract Shifted Value From Accumulator SYNTAX OPTIONS OPCODE OBJMODE SUB ACC,loc16 << #0 1010 1110 LLLL LLLL − 1000 0000 LLLL LLLL SUB ACC,loc16 << #1..15 0101 0110 0000 0000 0000 SHFT LLLL LLLL −...
Page 491 SUB ACC,loc16 << #0...16 Repeat If the operation is repeatable, then the instruction will be executed N+1 times. The state of the Z, N, C flags will reflect the final result. The V flag will be set if an intermediate overflow occurs. The OVC flag will count intermediate overflows, if overflow mode is disabled.
Page 492 SUB ACC,loc16 <<T SUB ACC,loc16 <<T Subtract Shifted Value From Accumulator SYNTAX OPTIONS OPCODE OBJMODE SUB ACC,loc16 <<T 0101 0110 0010 0111 0000 0000 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Upper 16−bits of the multiplicand register, XT(31:16) Description Subtract from the ACC register the left−shifted contents of the 16-bit location pointed to by the “loc16”...
Page 493 SUB ACC,loc16 <<T Example ; Calculate signed value: ACC = (VarA << SB) − (VarB << SB) SETC ; Turn sign extension mode on T,@SA ; Load T with shift value in SA ACC,@VarA << T ; Load in ACC shifted contents of VarA T,@SB ;...
Page 494 SUB ACC,#16bit << #0..15 SUB ACC,#16bit << #0..15 Subtract Shifted Value From Accumulator SYNTAX OPTIONS OPCODE OBJMODE SUB ACC,#16bit << #0..15 − 1111 1111 0000 SHFT CCCC CCCC CCCC CCCC Operands Accumulator register #16bit 16-bit immediate constant value #0..15 Shift value (default is ”<< #0” if no value specified) Description Subtract the left shifted 16-bit immediate constant value from the ACC register.
Page 495 SUB AX, loc16 SUB AX, loc16 Subtract Specified Location From AX SYNTAX OPTIONS OPCODE OBJMODE SUB AX, loc16 − 1001 111A LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) Description Subtract the 16−bit content of the location pointed to by the “loc16” addressing mode from the specified AX register (AH or AL) and store the results in AX: AX = AX −...
Page 496 SUB loc16, AX SUB loc16, AX Reverse-Subtract Specified Location From AX SYNTAX OPTIONS OPCODE OBJMODE SUB loc16, AX − 0111 010A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Description Subtract the content of the specified AX register (AH or AL) from the 16-bit content of the location pointed to by the “loc16”...
Page 497 SUBB ACC,#8bit SUBB ACC,#8bit Subtract 8-bit Value SYNTAX OPTIONS OPCODE OBJMODE SUBB ACC,#8bit − 0001 1001 CCCC CCCC Operands Accumulator register #8bit 8-bit immediate constant value Description Subtract the zero−extended, 8-bit constant from the ACC register: ACC = ACC − 0:8bit; Flags and After the subtraction, the Z flag is set if ACC is zero, else Z is cleared.
Page 498 SUBB SP,#7bit SUBB SP,#7bit SYNTAX OPTIONS OPCODE OBJMODE SUBB SP,#7bit − 1111 1110 1CCC CCCC Operands Stack pointer #7bit 7-bit immediate constant value Description Subtract a 7-bit unsigned constant to SP and store the result in SP: SP = SP − 0:7bit; Flags and None Modes...
Page 499 SUBB XARn,#7bit SUBB XARn,#7bit Subtract 7-Bit From Auxiliary Register SYNTAX OPTIONS OPCODE OBJMODE SUBB XARn, #7bit − 1101 1nnn 1CCC CCCC Operands XARn XAR0 to XAR7, 32-bit auxiliary registers #7bit 7−bit immediate constant value Description Subtract the 7−bit unsigned constant from XARn and store the result in XARn: XARn = XARn −...
Page 500 SUBBL ACC, loc32 SUBBL ACC, loc32 Subtract 32-bit Value Plus Inverse Borrow SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 0100 SUBBL ACC, loc32 − 0000 0000 LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Accumulator register Description Subtract from the ACC the 32-bit location pointed to by the “loc32” addressing mode and the logical inversion of the value in the carry flag bit: ACC = ACC −...
Page 501 SUBBL ACC, loc32 SUBBL ACC,@VarB+2 ; Subtract from ACC the contents of ; the high 32-bits of VarB with borrow MOVL @VarC+2,ACC ; Store high 32-bit result into VarC 6-344...
Page 502 SUBCU ACC,loc16 SUBCU ACC,loc16 Subtract Conditional 16 Bits SYNTAX OPTIONS OPCODE OBJMODE SUBCU ACC,loc16 0001 1111 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Perform 16-bit conditional subtraction, which can be used for unsigned modulus division: temp(32:0) = ACC <<...
Page 503 SUBCU ACC,loc16 Example 2 ; Calculate signed: Quot16 = Num16Den16, Rem16 = Num16%Den16 CLRC ; Clear TC flag, used as sign flag ACC,@Den16 << 16 ; AH = Den16, AL = 0 ABSTC ; Take abs value, TC = sign ^ TC T,@AH ;...
Page 504 SUBCUL ACC,loc32 SUBCUL ACC,loc32 Subtract Conditional 32 Bits SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0001 0111 SUBCUL ACC,loc32 0000 0000 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Perform 32-bit conditional subtraction, which can be used for unsigned modulus division: temp(32:0) = ACC <<...
Page 505 SUBCUL ACC,loc32 Example 1 ; Calculate unsigned: Quot32 = Num32/Den32, Rem32 = Num32%Den32 MOVB ACC,#0 ; Zero ACC MOVL P,@Num32 ; Load P register with Num32 ; Repeat operation 32 times ||SUBCUL ACC,@Den32 ; Conditional subtract with Den32 MOVL @Rem32,ACC ;...
Page 506 SUBCUL ACC,loc32 Example 4 ; Calculate signed: Quot64 = Num364Den32, Rem32 = Num64%Den32 MOVL ACC,@Num64+2 ; Load ACC:P with 64-bit numerator MOVL P,@Num64+0 TBIT @AH,#15 ; TC = sign of numerator $10,NTC ; Take absolute value of numerator NEG64 ACC:P $10: MOVL @XAR3,P...
Page 507 SUBL ACC, loc32 SUBL ACC, loc32 Subtract 32-bit Value SYNTAX OPTIONS OPCODE OBJMODE SUBL ACC, loc32 − 0000 0011 LLLL LLLL Operands Accumulator register loc32 Addressing mode (see Chapter 5) Description Subtract the 32-bit location pointed to by the “loc32” addressing mode from the ACC register : ACC = ACC −...
Page 508 SUBL ACC,P << PM SUBL ACC,P << PM Subtract 32-bit Value SYNTAX OPTIONS OPCODE OBJMODE SUBL ACC,P << PM 0001 0001 1010 1100 Note: This instruction is an alias for the ”MOVS T,loc16” operation with “loc16 = @T” addressing mode. Operands Accumulator register Product register...
Page 509 SUBL ACC,P << PM SUBL ACC,P << PM ; ACC = (S:B << 11) − (M*X >> 4) MOVH @Y,ACC << 5 ; Store Q15 result into Y 6-352...
Page 510 SUBL loc32, ACC SUBL loc32, ACC Subtract 32-bit Value SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0100 0001 SUBL loc32, ACC − 0000 0000 LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Accumulator register Description Subtract the content of the ACC register from the location pointed to by the “loc32”...
Page 511 SUBR loc16,AX SUBR loc16,AX Reverse-Subtract Specified Location From AX SYNTAX OPTIONS OPCODE OBJMODE SUBR loc16,AX − 1110 101A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Description Subtract the 16−bit content of the location pointed to by the “loc16” addressing mode from the specified AX register (AH or AL), and store the result in location pointed to by ”loc16”: [loc16] = AX −...
Page 512 SUBRL loc32, ACC SUBRL loc32, ACC Reverse-Subtract Specified Location From ACC SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0100 1001 SUBRL loc32, ACC − 0000 0000 LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Accumulator register Description Subtract from the ACC register the 32-bit location pointed to by the “loc32” addressing mode and store the result in the location pointed to by “loc32”: [loc32] = ACC −...
Page 513 SUBU ACC, loc16 SUBU ACC, loc16 Subtract Unsigned 16-bit Value SYNTAX OPTIONS OPCODE OBJMODE SUBU ACC, loc16 0000 0001 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Subtract the 16-bit contents of the location pointed to by the “loc16” addressing mode from the ACC register.
Page 514 SUBUL ACC, loc32 SUBUL ACC, loc32 Subtract Unsigned 32-bit Value SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 0101 SUBUL ACC, loc32 − 0000 0000 LLLL LLLL Operands loc32 Addressing mode (see Chapter 5) Accumulator register Description Subtract from the ACC register the 32-bit the location pointed to by the “loc32”...
Page 515 SUBUL P,loc32 SUBUL P,loc32 Subtract Unsigned 32-bit Value SYNTAX OPTIONS OPCODE OBJMODE 0101 0110 0101 1101 SUBUL P,loc32 − 0000 0000 LLLL LLLL Operands Product register loc32 Addressing mode (see Chapter 5) Description Subtract from the P register the 32-bit content of the location pointed to by the “loc32”...
Page 516 TBIT loc16,#bit TBIT loc16,#bit Test Specified Bit SYNTAX OPTIONS OPCODE OBJMODE TBIT loc16,#16bit − 0100 BBBB LLLL LLLL Operands loc16#bit Addressing mode (see Chapter 5) Immediate constant bit index from 0 to 15 Description Test the specified bit of the data value in the location pointed to by the “loc16”...
Page 517 TBIT loc16,T TBIT loc16,T Test Bit Specified by Register SYNTAX OPTIONS OPCODE OBJMODE TBIT loc16,T − 0101 0110 0010 0101 0000 0000 LLLL LLLL Operands loc16 T Addressing mode (see Chapter 5) Upper 16 bits of the multiplicand register (XT) Description Test the bit specified by the four least significant bits of the T register, T(3:0) = 0…15 of the data value in the location pointed to by the “loc16”...
Page 518 TCLR loc16,#bit TCLR loc16,#bit Test and Clear Specified Bit SYNTAX OPTIONS OPCODE OBJMODE TCLR loc16,#bit − 0101 0110 0000 1001 0000 BBBB LLLL LLLL Operands loc16, Addressing mode (see Chapter 5) #bit Immediate constant bit index from 0 to 15 Description Test the specified bit of the data value in the location pointed to by the “loc16”...
Page 519 TEST ACC TEST ACC Test for Accumulator Equal to Zero SYNTAX OPTIONS OPCODE OBJMODE TEST ACC − 1111 1111 0101 1000 Operands Accumulator register Description Compare the ACC register to zero and set the status flag bits accordingly: Modify flags on (ACC − 0x00000000); Flags and If bit 31 of the ACC is 1, N is set;...
Page 520 TRAP #VectorNumber TRAP #VectorNumber Software Trap SYNTAX OPTIONS OPCODE OBJMODE TRAP #VectorNumber − 0000 0000 001C CCCC Operands Vector CPU interrupt vector 0 to 31 Number Description The TRAP instruction transfers program control to the interrupt service routine that corresponds to the vector specified in the instruction. It does not affect the interrupt flag register (IFR) or the interrupt enable register (IER), regardless of whether the chosen interrupt has corresponding bits in these registers.
Page 521 TRAP #VectorNumber Part of the operation involves saving pairs of 16-bit core registers onto the stack pointed to by the SP register. Each pair of registers is saved in a single 32-bit operation. The register forming the low word of the pair is saved first (to an even address);...
Page 522 TSET loc16,#16bit TSET loc16,#16bit Test and Set Specified Bit SYNTAX OPTIONS OPCODE OBJMODE TSET loc16,#16bit − 0101 0110 0000 1101 0000 BBBB LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) #bit Immediate constant bit index from 0 to 15 Description Test the specified bit of the data value in the location pointed to by the “loc16”...
Page 523 UOUT *(PA),loc16 UOUT *(PA),loc16 Unprotected Output Data to I/O Port SYNTAX OPTIONS OPCODE OBJMODE UOUT *(PA),loc16 1011 0000 LLLL LLLL CCCC CCCC CCCC CCCC Operands *(PA) Immediate I/O space memory address loc16 Addressing mode (see Chapter 5) Description Store the 16-bit value from the location pointed to by the “loc16” addressing mode into the I/O space location pointed to by ”*(PA): IOspace[0x000:PA] = loc16;...
Page 524 UOUT *(PA),loc16 Example ; IORegA address = 0x0300; ; IOREgB address = 0x0301; ; IOREgC address = 0x0302; ; IORegA = 0x0000; ; IORegB = 0x0400; ; IORegC = VarA; ; if( IORegC = 0x2000 ) ; IORegC = 0x0000; IORegA .set 0x0300...
Page 525 XB *AL XB *AL C2 xLP Source-Compatible Indirect Branch SYNTAX OPTIONS OPCODE OBJMODE XB *AL − 0101 0110 0001 0100 Operands Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Description Unconditional indirect branch by loading the low 16 bits of PC with the contents of register AL and forcing the upper 6 bits of the PC to 0x3F: PC = 0x3F:AL;...
Page 526 XB pma,*,ARPn XB pma,*,ARPn C2xLP Source-Compatible Branch with ARP Modification SYNTAX OPTIONS OPCODE OBJMODE XB pma,*,ARPn − 0011 1110 0111 0nnn CCCC CCCC CCCC CCCC Operands 16-bit immediate program -memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) ARPn 3-bit auxiliary register pointer (ARP0 to ARP7) Description...
Page 527 XB pma,COND XB pma,COND C2 xLP Source-Compatible Branch SYNTAX OPTIONS OPCODE OBJMODE XB pma,COND − 0101 0110 1101 COND CCCC CCCC CCCC CCCC Operands 16-bit immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) COND Conditional codes: COND...
Page 528 XB pma,COND Example ; Branch to subroutines in SwitchTable selected by Switch value. ; This example only works for code located in upper 64K of ; program space: SwitchTable: ; Switch address table: .word Switch0 ; Switch0 address .word Switch1 ;...
Page 529 XBANZ pma,*ind{,ARPn} XBANZ pma,*ind{,ARPn} C2 x LP Source-Compatible Branch If ARn Is Not Zero SYNTAX OPTIONS OPCODE OBJMODE XBANZ pma,* − 0101 0110 0000 1100 CCCC CCCC CCCC CCCC XBANZ pma,*++ − 0101 0110 0000 1010 CCCC CCCC CCCC CCCC XBANZ pma,*−−...
Page 530 XBANZ pma,*ind{,ARPn} Flags and None Modes Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ; Copy the contents of Array1 to Array2: ; int32 Array1[N]; ;...
Page 531 XCALL *AL XCALL *AL C2 x LP Source-Compatible Function Call SYNTAX OPTIONS OPCODE OBJMODE XCALL *AL − 0101 0110 0011 0100 Operands Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Description Indirect call with destination address in AL.
Page 532 XCALL pma,*,ARPn XCALL pma,*,ARPn C2 x LP Source-Compatible Function Call SYNTAX OPTIONS OPCODE OBJMODE XCALL pma,*,ARPn − 0011 1110 0110 1nnn CCCC CCCC CCCC CCCC Operands 16-bit immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) ARPn 3-bit auxiliary register pointer (ARP0 to ARP7) Description...
Page 533 XCALL pma,COND XCALL pma,COND C2xLP Source-Compatible Function Call SYNTAX OPTIONS OPCODE OBJMODE XCALL pma,COND − 0101 0110 1110 COND CCCC CCCC CCCC CCCC Operands 16-bit immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) COND Conditional codes: COND Syntax...
Page 534 XCALL pma,COND Flags and If the V flag is tested by the condition, then V is cleared. Modes Repeat This instruction is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter (RPTC) and executes only once. Example ;...
Page 535 XMAC P,loc16,*(pma) XMAC P,loc16,*(pma) C2xLP Source-compatible Multiply and Accumulate SYNTAX OPTIONS OPCODE OBJMODE XMAC P,loc16,*(pma) 1000 0100 LLLL LLLL CCCC CCCC CCCC CCCC Operands Product register loc16 Addressing mode (see Chapter 5) *(pma) Immediate program memory address, access high 64K range of program space only (0x3F0000 to 0x3FFFFF) Description Add the previous product (stored in the P register), shifted as specified by the...
Page 536 XMAC P,loc16,*(pma) The value in the PM bits sets the shift mode for the output operation from the product register. If the product shift value is positive (logical left shift operation), then the low bits are zero filled. If the product shift value is negative (arithmetic right shift operation), the upper bits are sign extended.
Page 537 XMACD P,loc16,*(pma) XMACD P,loc16,*(pma) C2xLP Source-Compatible Multiply and Accumulate With Data Move SYNTAX OPTIONS OPCODE OBJMODE XMACD P,loc16,*(pma) 1010 0100 LLLL LLLL CCCC CCCC CCCC CCCC Operands Product register loc16 Addressing mode (see Chapter 5) Note: For this operation, register-addressing modes cannot be used. The modes are: @ARn, @AH, @AL, @PH, @PL, @SP, @T.
Page 538 XMACD P,loc16,*(pma) If overflow mode bit is set, the ACC value will saturate maximum positive (0x7FFFFFFF) or maximum negative (0x80000000) if the operation overflowed. The value in the PM bits sets the shift mode for the output operation from the product register.
Page 539 XOR ACC,loc16 XOR ACC,loc16 Bitwise Exclusive OR SYNTAX OPTIONS OPCODE OBJMODE XOR ACC,loc16 1011 0111 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Perform a bitwise XOR operation on the ACC register with the zero-extended content of the location pointed to by the “loc16” address mode.
Page 540 XOR ACC,#16bit << #0..16 XOR ACC,#16bit << #0..16 Bitwise Exclusive OR SYNTAX OPTIONS OPCODE OBJMODE XOR ACC,#16bit << #0..15 − 0011 1110 0010 SHFT CCCC CCCC CCCC CCCC XOR ACC,#16bit << #16 − 0101 0110 0100 1110 CCCC CCCC CCCC CCCC Operands Accumulator register #16bit...
Page 541 XOR AX,loc16 XOR AX,loc16 Bitwise Exclusive OR SYNTAX OPTIONS OPCODE OBJMODE XOR AX, loc16 − 0111 000A LLLL LLLL Operands Accumulator high (AH) or accumulator low (AL) register loc16 Addressing mode (see Chapter 5) Description Perform a bitwise exclusive OR operation on the specified AX register (AH or AL) and the contents of the location pointed to by the “loc16”...
Page 542 XOR loc16, AX XOR loc16, AX Bitwise Exclusive OR SYNTAX OPTIONS OPCODE OBJMODE XOR loc16, AX − 1111 001A LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Accumulator high (AH) or accumulator low (AL) register Description Perform a bitwise exclusive OR operation on the 16-bit contents of location pointed to by the “loc16”...
Page 543 XOR loc16,#16bit XOR loc16,#16bit Bitwise Exclusive OR SYNTAX OPTIONS OPCODE OBJMODE XOR loc16,#16bit − 0001 1100 LLLL LLLL CCCC CCCC CCCC CCCC Operands loc16 Addressing mode (see Chapter 5) #16bit 16-bit immediate constant value Description Perform a bitwise XOR operation on the content of the location pointed to by the “loc16”...
Page 544 XORB AX, #8bit XORB AX, #8bit Bitwise Exclusive OR 8-bit Value SYNTAX OPTIONS OPCODE OBJMODE XORB AX, #8bit − 1111 000A CCCC CCCC Operands Accumulator high (AH) or accumulator low (AL) register #8bit 8-bit immediate constant value Description Perform a bitwise exclusive OR operation on the specified AX register and the 8-bit unsigned immediate constant zero extended.
Page 545 XPREAD loc16, *(pma) XPREAD loc16, *(pma) C2xLP Source-Compatible Program Read SYNTAX OPTIONS OPCODE OBJMODE XPREAD loc16,*(pma) 1010 1100 MMMM MMMM LLLL LLLL LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) *(pma) Immediate program-memory address, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Description Load the 16-bit data-memory location pointed to by the “loc16”...
Page 546 XPREAD loc16, *AL XPREAD loc16, *AL C2xLP Source-Compatible Program Read SYNTAX OPTIONS OPCODE OBJMODE XPREAD loc16,*AL 0101 0110 0011 1100 0000 0000 LLLL LLLL Operands loc16 Addressing mode (see Chapter 5) Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) Description Load the 16-bit data-memory location pointed to by the “loc16”...
Page 547 XPWRITE *A,loc16 XPWRITE *A,loc16 C2xLP Source-Compatible Program Write SYNTAX OPTIONS OPCODE OBJMODE XPWRITE *AL,loc16 0101 0110 0011 1101 0000 0000 LLLL LLLL Operands Indirect program-memory addressing using register AL, can only access high 64K of program space range (0x3F0000 to 0x3FFFFF) loc16 Addressing mode (see Chapter 5) Description...
Page 548 XRET XRET C2xLP Source-Compatible Return SYNTAX OPTIONS OPCODE OBJMODE XRET − 0101 0110 1111 1111 Note: XRET is an alias for RETC unconditional. Operands None Description Return conditionally. If the specified condition is true, a 16-bit value is popped from the stack and stored into the low 16 bits of the PC while the upper 6 bits of the PC are forced to 0x3F;...
Page 549 XRETC COND XRETC COND C2xLP Source-Compatible Conditional Return SYNTAX OPTIONS OPCODE OBJMODE XRETC COND − 0101 0110 1111 COND Operands COND Conditional codes: COND Syntax Description Flags Tested 0000 Not Equal To Z = 0 0001 Equal To Z = 1 0010 Greater Then Z = 0 AND N = 0...
Page 550 XRETC COND Example ; Return from FuncA if VarA does not equal zero, else set VarB ; to zero and return. This example only works for code located ; in upper 64K of program space: XCALL FuncA ; Call FuncA FuncA: ;...
Page 551 ZALR ACC,loc16 ZALR ACC,loc16 Zero AL and Load AH With Rounding SYNTAX OPTIONS OPCODE OBJMODE ZALR ACC,loc16 − 0101 0110 0001 0011 0000 0000 LLLL LLLL Operands Accumulator register loc16 Addressing mode (see Chapter 5) Description Load low accumulator (AL) with the value 0x8000 and load high accumulator (AH) with the 16-bit contents pointed to by the ”loc16”...
Page 552 ZAP OVC ZAP OVC Clear Overflow Counter SYNTAX OPTIONS OPCODE OBJMODE ZAP OVC − 0101 0110 0101 1100 Operands overflow counter bits in Status Register 0 (ST0) Description Clear the overflow counter (OVC) bits in Status Register 0 (ST0). Flags and The 6-bit overflow counter bits (OVC) are cleared.
Page 553 ZAPA ZAPA Zero Accumulator and P Register SYNTAX OPTIONS OPCODE OBJMODE ZAPA − 0101 0110 0011 0011 Operands None Description Zero the ACC and P registers as well as the overflow counter (OVC): ACC = 0; P = 0; OVC = 0; Flags and The N bit is set.
Page 554: Diagnostics And Recovery
Chapter 7 Emulation Features The CPU in the C28x contains hardware extensions for advanced emulation features that can assist you in the development of your application system (software and hardware). This chapter describes the emulation features that are available on all C28x devices using only the JTAG port (with TI exten- sions).
Page 555: Overview Of Emulation Features
Overview of Emulation Features 7.1 Overview of Emulation Features The CPU’s hardware extensions for advanced emulation features provide simple, inexpensive, and speed-independent access to the CPU for sophisti- cated debugging and economical system development, without requiring the costly cabling and access to processor pins required by traditional emulator systems.
Page 556: Jtag Header To Interface A Target To The Scan Controller
Debug Interface 7.2 Debug Interface The target-level TI debug interface uses the five standard IEEE 1149.1 (JTAG) signals (TRST, TCK, TMS, TDI, and TDO) and the two TI extensions (EMU0 and EMU1). Figure 7−1 shows the 14-pin JTAG header that is used to inter- face the target to a scan controller, and Table 7−1 (page 7-4) defines the pins.
Page 557: Pin Header Signal Descriptions
Debug Interface Table 7−1. 14-Pin Header Signal Descriptions Emulator Target State † State † Signal Description EMU0 Emulation pin 0 EMU1 Emulation pin 1 Ground PD (V Presence detect. Indicates that the emulation cable is connected and that the target is pow- ered up.
Page 558: Selecting Device Operating Modes By Using Trst, Emu0, And Emu1
Debug Interface Table 7−2. Selecting Device Operating Modes By Using TRST, EMU0, and EMU1 JTAG Cable Active? TRST EMU1 EMU0 Device Operating Mode Slave mode. Disables the CPU and memory portions of the C28x. Another processor treats the C28x as a peripheral. High Reserved for testing High...
Page 559: Debug Terminology
Debug Terminology 7.3 Debug Terminology The following definitions will help you to understand the information in the rest of this chapter: Background code. The body of code that can be halted during debug- ging because it is not time-critical. Foreground code. The code of time-critical interrupt service routines, which are executed even when background code is halted.
Page 560: Execution Control Modes
Execution Control Modes 7.4 Execution Control Modes The C28x supports two debug execution control modes: Stop mode Real-time mode Stop mode provides complete control of program execution, allowing for the disabling of all interrupts. Real-time mode allows time-critical interrupt service routines to be performed while execution of other code is halted.
Page 561: Stop Mode Execution States
Execution Control Modes The CPU can service all interrupts in this state. When an interrupt occurs simultaneously with a debug event, the debug event has priority; however, if interrupt processing began before the debug event occurred, the debug event cannot be processed until the interrupt service routine begins. Figure 7−2 illustrates the relationship among the three states.
Page 562: Real-Time Mode
Execution Control Modes 7.4.2 Real-Time Mode Real-time mode provides for the debugging of code that interacts with inter- rupts that must not be disabled. Real-time mode allows you to suspend back- ground code at break events while continuing to execute time-critical interrupt service routines (also referred to as foreground code).
Page 563: Real-Time Mode Execution States
Execution Control Modes used, the CPU can service the interrupt. If a STEP 1 command was used, the CPU cannot, even if the interrupt is NMI or RS. In real-time mode, if the DBGM bit is 1 (debug events are disabled), a RUN 1 or STEP 1 command forces continuous execution of instructions until DBGM is cleared.
Page 564: Summary Of Stop Mode And Real-Time Mode
Execution Control Modes Caution about breakpoints within time-critical interrupt service routines Do not use breakpoints within time-critical interrupt service routines. They will cause the device to enter the debug-halt state, just as if the breakpoint were located in normal code. Once in the debug-halt state, the CPU services re- quests for RS, NMI, and those interrupts enabled in the DBGIER and the IER.
Page 565: Stop Mode Versus Real-Time Mode
Execution Control Modes Figure 7−4. Stop Mode Versus Real-Time Mode Single-instruction state Run state Cannot observe CPU Cannot observe CPU Can service an interrupt Can service interrupts if RUN 1 used † Debugger command Debugger command, breakpoint, or analysis stop Debugger command After executing one instruction...
Page 566: Interrupt Handling Information By Mode And State
Execution Control Modes Table 7−3. Interrupt Handling Information By Mode and State Mode State If This Interrupt Occurs ... The Interrupt Is ... Stop Debug-halt Not serviced Not serviced Maskable interrupt Latched in IFR but not serviced Single-instruction If running: Serviced If stepping: Not serviced If running: Serviced If stepping: Not serviced...
Page 567 Execution Control Modes Note: Unless you are using a real-time operating system, do not enable the real- time operating system interrupt (RTOSINT). RTOSINT is completely dis- abled when bit 15 in the IER is 0 and bit 15 in the DBGIER is 0. 7-14...
Page 568: Aborting Interrupts With The Aborti Instruction
Aborting Interrupts With the ABORTI Instruction 7.5 Aborting Interrupts With the ABORTI Instruction Generally, a program uses the IRET instruction to return from an interrupt. The IRET instruction restores all the values that were saved to the stack during the automatic context save.
Page 569: Dt-Dma Mechanism
DT-DMA Mechanism 7.6 DT-DMA Mechanism The debug-and-test direct memory access (DT-DMA) mechanism provides access to memory, CPU registers, and memory-mapped registers (such as emulation registers and peripheral registers) without direct CPU intervention. DT-DMAs intrude on CPU time; however, you can block them by setting the debug enable mask bit (DBGM) in ST1.
Page 570: Process For Handling A Dt-Dma Request
DT-DMA Mechanism Figure 7−5. Process for Handling a DT-DMA Request DT-DMA mechanism requests access Rude Request polite or rude? Polite DBGM = 0? Access denied Mode Preemptive nonpreemptive or preemptive? Force a hole Nonpreemptive Wait for hole Access performed Some key concepts of the DT-DMA mechanism are: Even if DBGM = 0, when the mechanism is in nonpreemptive mode, it must wait for a hole.
Page 571 DT-DMA Mechanism The DT-DMA mechanism does not cause a program-flow discontinuity. No interrupt-like save/restore is performed. When a preemptive DT-DMA forces a hole, no program address counters increment during that cycle. A DT-DMA request awakens the device from the idle state (initiated by the IDLE instruction).
Page 572: Analysis Breakpoints, Watchpoints, And Counter(S)
Analysis Breakpoints, Watchpoints, and Counter(s) 7.7 Analysis Breakpoints, Watchpoints, and Counter(s) All C28x devices include two analysis units AU1 and AU2. Analysis Unit 1 (AU1) counts events or monitors address buses. Analysis Unit 2 (AU2) moni- tors address and data buses. You can configure these two analysis units as analysis breakpoints or watchpoints.
Page 573: Benchmark Counter/Event Counter(S)
Analysis Breakpoints, Watchpoints, and Counter(s) When comparing two addresses, you can set two watchpoints. When comparing an address and a data value, you can set only one watchpoint. When performing a read watchpoint, the address is available a few cycles earlier than the data; the watchpoint logic accounts for this.
Page 574: Typical Analysis Unit Configurations
Analysis Breakpoints, Watchpoints, and Counter(s) code 2 pipeline phase. The counter counts wait states caused by instructions that are fetched but not executed. In most cases, these effects cancel each other out. Benchmarking is best used for larger portions of code. Do not rely heavily on the precision of the benchmarking.
Page 575 Analysis Breakpoints, Watchpoints, and Counter(s) A benchmark counter/event counter The benchmark counter is only available with analysis unit 1. This counter can be used as a benchmark counter to count cycles or instructions. It can also be used to count AU2 events. Configuration of the analysis resources is supported in Code Composer Stu- dio.
Page 576: Data Logging
Data Logging 7.8 Data Logging Data logging enables the C28x to send selected memory values to a host proc- essor using the standard JTAG port and an XDS510 or other compatible scan controller. You control data logging activity with your application code. To perform data logging, you must create a linear buffer of 32-bit words to hold a packet of information.
Page 577 Data Logging (DMA_CNTRL). EVT_CNTRL is described in Table 7−5 (page 7-26), and DMA_CNTRL is described in Table 7−4 (page 7-25). Note: The application must not read from the end address of the buffer during the data logging operation. When the end address appears on the address bus, the C28x ends the transfer.
Page 578: Addrl (At Data-Space Address 00 083816)
Data Logging Table 7−4. Start Address and DMA Registers Address Name Access Description 00 0838 ADDRL Start address register (lower 16 bits) 15:0 Lower 16 bits of start address 00 0839 ADDRH Word counter/start address register (upper 6 bits) 15:8 Word counter.
Page 579: Refl (At Data-Space Address 00 084A16)
Data Logging Table 7−5. End-Address Registers Address Name Access Description 00 0848 MASKL Set to 0 00 0849 MASKH Set to 0 00 084A REFL Data logging end reference address (lower 16 bits) 15:0 Lower 16 bits of start address 00 084B REFH Data logging end reference address (upper 6 bits)
Page 580: Data Log Interrupt (Dlogint)
Data Logging 3) Wait at least three cycles so that the write to the control register (done in the write phase of the pipeline) occurs before the read from the ID register in step 4. You can fill in the extra cycles with NOP (no operation) instruc- tions or with other instructions that do not involve accessing the emulation registers.
Page 581: Examples Of Data Logging
Data Logging 7.8.4 Examples of Data Logging Example 7−1 shows how to log 20 32-bit words, starting at address 00 0100 in data memory. The accesses are preemptive (they have higher priority than the CPU) and rude (they ignore the state of the DBGM bit). In addition, data logging can occur during time-critical interrupt service routines.
Page 582: Initialization Code For Data Logging With End Address
Data Logging Example 7−2. Initialization Code for Data Logging With End Address ; Base addresses ADMA .set 0838h DEVT .set 0848h ; Offsets DMA_ADDRL .set DMA_ADDRH .set DMA_CNTRL .set DMA_ID .set MASKL .set MASKH .set REFL .set REFH .set EVT_CNTRL .set EVT_ID .set EALLOW...
Page 583: Valid Combinations Of Analysis Resources
Sharing Analysis Resources 7.9 Sharing Analysis Resources You can use analysis breakpoints, watchpoints, and a benchmark/event counter through the debugger, and you can use data logging through applica- tion code. Table 7−6 lists the analysis resources, and Figure 7−10 shows which resources are available to be used at the same time.
Page 584: Diagnostics And Recovery
Diagnostics and Recovery 7.10 Diagnostics and Recovery Debug registers within the CPU keep track of the state of several key signals. This allows diagnosis of such problems as a floating READY signal, NMI sig- nal, or RS (reset) signal. Should the debug software attempt an operation that does not complete after a certain time-out period (as determined by the debug software), it attempts to determine the probable cause and display the situa- tion to you.
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Page 586: A.2 Register Figures
Appendix A Appendix A Register Quick Reference For the status and control registers of the ’28x, this appendix summarizes: Their reset values The instructions available for accessing them The functions of their bits Topic Page Reset Values of and Instructions for Accessing the Registers .
Page 587: Reset Values Of The Status And Control Registers
Reset Values of and Instructions for Accessing the Registers A.1 Reset Values of and Instructions for Accessing the Registers Table A−1 lists the CPU status and control registers, their reset values, and the instructions that are available for accessing the registers. Table A−1.
Page 588 Register Figures A.2 Register Figures The following figures summarize the content of the ’28x status and control reg- isters. Each figure in this section provides information in this way: The value shown in the register is the value after reset. Each unreserved bit field or set of bits has a callout that very briefly de- scribes its effect on the processor.
Page 589: A−1. Status Register St0
Register Figures Figure A−1. Status register ST0 É É É É É É OVC/OVCU É É É Negative flag Sign-extension mode Negative condition false Sign extension suppressed Negative condition true Sign extension mode selected Overflow flag ACC overflow mode Flag is reset Results overflow normally Overflow detected Overflow mode selected...
Page 590: Status Register St1, Bits15−8
Register Figures Figure A−2. Status register ST1, Bits15−8 É É É É É É É É É É MOM1MAP OBJMODE AMODE É É É É É XF status bit Address mode bit XFS output signal low C28x/C27x processing mode XFS output signal is high C2xLP addressing modes Object compatibility mode bit Auxiliary register pointer...
Page 591: Status Register St1, Bits 7−0
Register Figures Figure A−3. Status Register ST1, Bits 7−0 É É É É É É É É É ‡ É É É É É É É É É IDLESTAT EALLOW LOOP VMAP PAGE0 DBGM INTM É É É É É É É É É Stack pointer alignment bit Stack pointer has not been Interrupt enable mask bit...
Page 592: Interrupt Flag Register (Ifr
Register Figures Figure A−4. Interrupt flag register (IFR) Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 593: Interrupt Enable Register (Ier)
Register Figures Figure A−5. Interrupt enable register (IER) Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 594: A−6. Debug Interrupt Enable Register (Dbgier)
Register Figures Figure A−6. Debug interrupt enable register (DBGIER) Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 595: B.1 Introduction
Appendix B Appendix A Submitting ROM Codes to TI This appendix defines the scope of code-customized DSPs and describes the procedures for developing prototype and production units. Information on sub- mitting object code and on ordering customer ROM-coded devices is also included.
Page 596 When the code has been finalized, the code can be submitted to Texas Instruments for masking into the on-chip program ROM. Figure B−1 illustrates the procedural flow for developing and ordering TMS320 masked parts.
Page 597: Tms320 Rom Code Prototype And Production Flowchart
Introduction Figure B−1. TMS320 ROM Code Prototype and Production Flowchart Customer submits Customer submits Customer submits custom code device requirements new code release form TI performs ROM receipt Customer approves ROM receipt TI orders masks, manufactures, and ships prototypes Customer approves prototype Customer releases...
Page 598: B.2 Code Submission
Customers must also sign a release that states: Any masked ROM device may be resymbolized as TI standard prod- uct and resold as though it were an unprogrammed version of the de- vice, at the convenience of Texas Instruments.
Page 599: B.3 Rom Layout
ROM Layout B.3 ROM Layout 1K OTP-ROM will be reserved for TI internal testing. This space will follow the 1K OTP-ROM meant for the customer. Locations 0x3F7FF8 – 0x3F7FFF will contain the CSM passwords similar to the flash parts. Submitting ROM Codes to TI...
Page 600: B.4 Rom Code Generation Flow
ROM Code Generation Flow B.4 ROM Code Generation Flow Step 1: Submission of code to TI There are three different possibilities while submitting a code for ROM: 1) A single COFF file that contains code for both “customer-OTP” as well as “customer ROM” may be submitted. 2) Code could be provided in two different COFF files, one for “cus- tomer-OTP”...
Page 601: Checksum Computation Memory Locations
ROM Code Generation Flow “Customer-OTP” area, including the D-number. Addresses 0x3D7BFE and 0x3D7BFF, which are eventually used to store the checksum are not used in the computation. TI-OTP area containing TI test code. Addresses 0x3D7FFE and 0x3D7FFF, which are eventually used to store the checksum are not used in the computation.
Page 602 ROM Code Generation Flow 0x3F7FF5 † High-word of checksum (for Customer-ROM) 0x3F7FF6 ROM entry-point (Branch instruction) 0x3F7FF7 ROM entry-point (Branch instruction) 0x3F7FF8 CSM passwords …. 0x3F7FFF † These addresses are reserved for the ROM code generation flow and cannot be used by customer code. Using these locations to store the D-number and checksum does not compromise code security.
Page 603: C.1 Summary Of Architecture Differences Between C2Xlp And C28X
Appendix C Appendix A C2xLP and C28x Architectural Differences This appendix highlights some of the architecture differences between the C2xLP and the C28x. Not all of the changes are listed here. An emphasis is placed on those changes of which you need to be aware while migrating from a C2xLP-based design to a C28x design.
Page 604: General Features
Summary of Architecture Differences Between C2xLP and C28x C.1 Summary of Architecture Differences Between C2xLP and C28x The C28x CPU features many improvements over the C2xLP CPU. A summa- ry of the enhancements is given here. Table C−1. General Features Feature C2xLP C28x...
Page 605: Register Changes From C2Xlp To C28X
Registers C.2 Registers The register modifications to the C2xLP are shown in Figure C−1. Registers that are shaded show the changes or enhancements on the C28x. The itali- cized names on the left are the original C2xLP names for the registers. The names on the right are the C28x names for the registers.
Page 606: Xar0 − Xar7
Registers C.2.1 CPU Register Changes A brief description of the register modifications is given below. For a complete description of each register, see descriptions in the C2xLP and C28x Refer- ence Guides. Multiplicand register. The 32-bit multiplicand register is called XT on the C28x.
Page 607: C.2.2 Data Page (Dp) Pointer Changes
Registers ST0/ST1 Status Registers. The C28x status register bit positions are different compared to the C2xLP. Figure C−3 shows the differences. Data Page Pointer. On the C2xLP the DP is part of status register ST0. The DP on the C28x is a separate register and is increased from 9 to 16 bits.
Page 608: Direct Addressing Mode Mapping
Registers AMODE == 0, the page size is reduced by half. This was done to accommo- date other useful addressing modes. The mapping of the direct addressing modes between the C2xLP and the C28x is as shown in Figure C−2. Figure C−2.
Page 609: Status Register Comparison Between C2Xlp And C28X
Registers C.2.3 Status Register Changes Figure C−3. Status Register Comparison Between C2xLP and C28x C2xLP Status Register ST0 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 610: C2Xlp Product Mode Shifter
Registers Zero flag. Z is new on the C28x. It is involved in determining if the results of certain operations are 0. It is also used for conditional operations. Negative flag. N is new on the C28x. It is involved in determining if the results of certain operations are negative.
Page 611 Registers OVC: Overflow counter. OVC is new on the C28x. It can be viewed as an extension of the accumulator. For signed operations, the OVC counter is an extension of the overflow mode. For unsigned opera- tions, the OVC counter (OVCU) is an extension of the carry mode. DBGM: Debug enable mask bit.
Page 612: Reset Conditions Of Internal Registers
Register Reset Conditions The functionality of the remaining bits is the same on C28x as they are on C2xLP. It should be noted that although the functionality did not change, the bit position in the registers did. These bits are: Sign extension mode (SXM) Overflow mode (OVM) Test/control flag (TC)
Page 613: Status Register Bits
Register Reset Conditions Table C−5. Status Register Bits C2xLP Bit C2xLP Reset Value C28x Bit Name C28x Reset Value Name XXXXXXXXX INTM 000 (left shift 1) 00 (no shift) INTM DBGM PAGE0 VMAP LOOP EALLOW IDLESTAT AMODE OBJMODE CNF not implement- M0M1MAP C2xLP and C28x Architectural Differences C-11...
Page 614: C.3 Memory Map
Memory Map C.3 Memory Map The major changes between the C2xLP and C28x memory maps are outlined in this section. There are several differences between the C2xLP and C28x memory maps. These improvements are due to the expanded architecture of the C28x.
Page 615: Memory Map Comparison (See Note A)
Memory Map Figure C−4. Memory Map Comparison (See Note A) Block Start C28x memory map for C2xLP C2xLP memory map Address Data Space Program Space Data Space - 64K I/O space − 64K VECTORS (32 x 32) 0x0000-0000 Memory (enabled if VMAP = 0) Registers 0x0000-0040 0x0000-0060...
Page 616: B0 Memory Map
Memory Map Data memory. The C2xLP has three internal memory regions (B0, B1, B2) totaling 544 words. The C28x has two internal memory regions (M0,M1) total- ing 1K words each. Note that for strict C2xLP compatibility, the memory re- gions are placed at the same addresses as noted in Table C−6. Table C−6.
Page 617: D.1 Introduction
Appendix D Appendix A C2xLP Migration Guidelines The C28x DSP is source-code compatible with C2xLP DSP based devices. The C28x DSP assembler accepts all C2xLP mnemonics with the exception of a few instructions. This chapter provides guidelines for C2xLP code migra- tion to a C28x device.
Page 618 Introduction D.1 Introduction This chapter provides guidelines that are intended for conversion from C2xLP assembly source to C28x object code. The conversion steps highlight the ar- chitectural changes between C2xLP and C28x operating modes. Future re- leases of documents will contain code conversion examples and software li- brary modules facilitating the conversion from C2xLP mixed C and assembly source to C28x object code.
Page 619: D.2 Recommended Migration Flow
Recommended Migration Flow D.2 Recommended Migration Flow Use the following steps (shown in Figure D−1) to migrate code: 1) Install the latest development tools for the C28x DSP (e.g. Code Compos- er Studiot version 2.x or higher) 2) Build the project with following C28x assembler options: −m20 ;...
Page 620: Flow Chart Of Recommended Migration Steps
Recommended Migration Flow Figure D−1. Flow Chart of Recommended Migration Steps Start Step 1 Migrate to Code Composer Studio for the C28x DSP Step 2 Configure your project with −m20, −mw, and −g assembler options to enable acceptance of C2xLP mnemonics. Also build a linker command file *.cmd for your C28x device.
Page 621 Recommended Migration Flow 6) Link the assembled code with the linker command file generated in Step 2. Relink if necessary to avoid any linker related errors. 7) Assemble or reassemble using the C28x assembler until the assembly is successful with no errors. The tables in section D.5 will help to resolve most of the errors during the assembly process.
Page 622: D.3 Mixing C2Xlp And C28X Assembly
Mixing C2xLP and C28x Assembly D.3 Mixing C2xLP and C28x Assembly At this point your original C2xLP code will be running on the C28x device. To facilitate further migra- tion to C28x code, there are special assembler directives that will facilitate mixing of C2xLP code and C28x code segments.
Page 623: Code To Save Contents Of Imr (Ier) And Disabling Lower Priority Interrupts At Beginning Of Isr
Code Examples D.4 Code Examples D.4.1 Boot Code for C28x operating mode initalization Note: The following code fragment must be placed in your code just after reset. This code will place the device in the proper operating mode to execute C2xLP converted code: Code Explanation...
Page 624: Code To Enable An Interrupt
Code Examples Table D−3. Code to Enable an Interrupt C2xLP C28x SETC INTM IER,#INTx LACL #INTx ;operation is atomic and SACL ;will not be interrupted. CLRC INTM Table D−4. Code to Clear the IFR Register C2xLP C28x ;write 1 to clear ;write 0 to clear SETC INTM...
Page 625: Full Context Save/Restore Comparison
Code Examples Table D−5. Full Context Save/Restore Comparison C2xLP Full Context Save/Restore C28x Full Context Save/Restore ;C28x automatically saves the ;following registers: INTx_ISR: ;T,ST0,AH,AL,PH,PL,AR1,AR0,DP,ST1, ; context save ;DBGSTAT,IER,PC *, AR1 INTx_ISR: #1,*+ ;interrupt context save #0,*+ PUSH AR1H:AR0H ; 32−bit SACH PUSH XAR2...
Page 626: C2Xlp And C28X Differences In Interrupts
Reference Tables for C2xLP Code Migration Topics D.5 Reference Tables for C2xLP Code Migration Topics Table D−6 through Table D−10 explain the major differences between the C2xLP and C28x architectures and in their respective code generation pro- cess. These tables are organized to highlight the differences in interrupts, CPU registers, memory maps, instructions, registers, and syntax.
Page 627: C2Xlp And C28X Differences In Status Registers
Reference Tables for C2xLP Code Migration Topics Table D−6. C2xLP and C28x Differences in Interrupts (Continued) Migration topic C2xLP C28x Interrupt enable and return CLRC INTM next_instn from function call next_instn CLRC INTM Interrupts Vector Uses Branch statements at the 32−bit absolute addresses.
Page 628: C2Xlp And C28X Differences In Memory Maps
Reference Tables for C2xLP Code Migration Topics Table D−7. C2xLP and C28x Differences in Status Registers (Continued) INTM bit in ST0 Cannot be saved if ST0 register Saved along with ST0 register is saved Data page pointer DP save/restored along with DP is a register, hence explicit store/ ST0.
Page 629: C2Xlp And C28X Differences In Instructions And Registers
Reference Tables for C2xLP Code Migration Topics Table D−8. C2xLp and C28x Differences in Memory Maps (Continued) Migration topic C2xLP C28x CNF bit mapping of B0 CNF bit maps B0 in data and Not applicable Block program memory CNF =0 − B0 in data memory Range: 0x0300−0x03FF : 0x0400−0x04FF CNF =1 −...
Page 630 Reference Tables for C2xLP Code Migration Topics Table D−9. C2xLP and C28x Differences in Instructions and Registers (Continued) Migration topic C2xLP C28x GREG register Memory mapped register Memory mapped register in XINTF Global Space may or may not be im- plemented on a particular device.
Page 631: D−10. Code Generation Tools And Syntax Differences
Reference Tables for C2xLP Code Migration Topics Table D−10. Code Generation Tools and Syntax Differences Migration topic C2xLP C28x Mnemonic Source or destination not always Instructions are always of the form specified. mnemonic destination, source LACL, source MOV destination,source SACL, destination Direct addressing syntax LACL dma MOV ACC, @@dma ;...
Page 632 Reference Tables for C2xLP Code Migration Topics Table D−10. Code Generation Tools and Syntax Differences (Continued) Migration topic C2xLP C28x Number radix usage x .set 9 .set 09 ;Assembler ;accepts Avoid leading zeros, else the assem- ;this as bler will be use this as octal number. ;decimal 9 Order of precedence in ex- Expressions in assembly state-...
Page 633: E.1 Condition Tests On Flags
Appendix E Appendix A C2xLP Instruction Set Compatibility This appendix highlights the differences in syntax between the C2xLP and the C28x instructions, and details which C2xLP compatible instructions are re- peatable on the C28x. The C28x assembler accepts both C28x and C2xLP as- sembly source syntax.
Page 634: C28X And C2Xlp Flags
Condition Tests on Flags E.1 Condition Tests on Flags On the C28x, all EQ/NEQ/GT/LT/LEQ conditional tests are performed on the state of the Z and N flags. On the C2xLP, the same condition tests are per- formed on the contents of the ACC register. Table E−1.
Page 635: C2Xlp Instructions And C28X Equivalent Instructions
Condition Tests on Flags E.2 C2xLP vs. C28x Mnemonics Table E−2 lists the C2xLP instructions with the C28x equivalent syntax. The C28x assembler will accept either the C2xLP syntax or the equivalent C28x syntax. The disassembler will decode and display the C28x syntax. The C2xLP cycle count numbers shown are for zero wait-state internal memory, where n equals the number of repetitions (i.e., if an instruction is re- peated, using the RPT instruction for repeatable instructions, n times it is exe-...
Page 636 Condition Tests on Flags Table E−2. C2xLP Instructions and C28x Equivalent Instructions (Continued) C2xLP C28x Instruc- Mnemonic Cycles Size Instruc- Mnemonic Cycles Size tion tion BACC BANZ pma,*ind[,ARn] XBANZ pma,*ind[,ARAPn] BANZ pma,*BR0+/*BR0−[,ARn] Not applicable BCND pma[,COND] pma,COND #8bitOff,COND BCND pma,COND1,COND2,.., skip,opposite of COND1 CONDn skip,opposite of COND2...
Page 637 Condition Tests on Flags Table E−2. C2xLP Instructions and C28x Equivalent Instructions (Continued) C2xLP C28x Instruc- Mnemonic Cycles Size Instruc- Mnemonic Cycles Size tion tion CLRC XF/OVM/SXM/TC/C CLRC XF/OVM/SXM/TC/C CLRC Not applicable CMPL CMPR 0/1/2/3 CMPR 0/1/2/3 DMOV loc16 DMOV loc16 IDLE IDLE...
Page 638 Condition Tests on Flags Table E−2. C2xLP Instructions and C28x Equivalent Instructions (Continued) C2xLP C28x Instruc- Mnemonic Cycles Size Instruc- Mnemonic Cycles Size tion tion loc16 MOVAD T,loc16 loc16 MOVP T,loc16 loc16 MOVS T,loc16 pma,loc16 XMAC P,loc16,*(pma) MACD pma,loc16 XMACD P,loc16,*(pma) *ind[,ARn] *ind[,ARPn]...
Page 639 Condition Tests on Flags Table E−2. C2xLP Instructions and C28x Equivalent Instructions (Continued) C2xLP C28x Instruc- Mnemonic Cycles Size Instruc- Mnemonic Cycles Size tion tion XRETC † RETC COND XRETC COND RETC COND1,COND2,..,CONDn $10,opposite of COND1 $10,opposite of COND2 XRETC CONDn $10: loc16...
Page 640 Condition Tests on Flags Table E−2. C2xLP Instructions and C28x Equivalent Instructions (Continued) C2xLP C28x Instruc- Mnemonic Cycles Size Instruc- Mnemonic Cycles Size tion tion SPLK #0x0000,loc16 loc16,#0 SPLK #16bit,loc16 loc16,#16bit 1 (or 2 (or 3 (or −6) SQRA loc16 SQRA loc16 SQRS...
Page 641: Repeatable Instructions For The C2Xlp And C28X
Repeatable Instructions E.3 Repeatable Instructions Not all of the repeatable instructions on the C2xLP are repeatable on the C28x. The ones that were not made repeatable do not make sense to repeat from a functionality standpoint. Also, some instructions that were not repeatable on the C2xLP are repeatable on the C28x.
Page 642 Repeatable Instructions Table E−3. Repeatable Instructions for the C2xLP and C28x (Continued) C2xLP C28x Repeatable Repeatable C2xLP Instruction LACT mem LAR AR,mem LDP mem LPH mem LST #n,mem LT mem LTA mem LTD mem LTP mem LTS mem MAC pma,mem MACD pma,mem MAR {ind}[,nextARP] MPY mem...
Page 643 Repeatable Instructions Table E−3. Repeatable Instructions for the C2xLP and C28x (Continued) C2xLP C28x Repeatable Repeatable C2xLP Instruction PSHD mem PUSH SACH mem[,shift] SACL mem[,shift] SAR AR,mem SETC CNF/XF/INTM/OVM/SXM/TC/C SPAC SPH mem SPL mem SPLK #lk,mem SQRA mem SQRS mem SST #n,mem SUB mem[,shift1] SUBB mem...
Page 644: F.1 Architecture Changes
Appendix F Appendix A Migration From C27x to C28x This appendix highlights the architecture differences between the C27x and the C28x and describes how to migrate your code from a C27x-based design to a C28x-based design. Topic Page Architecture Changes .
Page 645: C28X Registers
Architecture Changes F.1 Architecture Changes Certain changes to the architecture that are important when migrating from the C27x to the C28x include: Changes to registers Full context save and restore B0/B1 memory map consideration F.1.1 Changes to Registers The register modifications from the C27x are shown in Figure F−1. Shaded registers highlight the changes or enhancements for the C28x.
Page 646: St0 Register Bits
Architecture Changes A brief description of the register modifications is given below: XT(32), TL(16): The T register is increased to 32-bits and called the XT register. The existing C27x T register portion represents the upper 16-bits of the new 32-bit register. The additional 16-bits, called the TL portion, represents the lower 16-bits.
Page 647: St1 Register Bits
Architecture Changes Table F−2. ST1 Register Bits Bit(s) Syntax Description Reset Value INTM Interrupt Enable Mask Bit 1 (disabled) DBGM DeBug Enable Mask Bit 1 (disabled) PAGE0 PAGE0 Direct/Stack Address Mode VMAP Vector Map Bit VMAP input Stack Pointer Align Bit LOOP Loop Instruction Status Bit EALLOW...
Page 648: F.1.2 Full Context Save And Restore
Architecture Changes F.1.2 Full Context Save and Restore On both C27x and C28x, the registers in Figure F−2 are automatically saved on the stack on an interrupt or trap operation and automatically restored on an IRET instruction. Figure F−2. Full Context Save/Restore DBGSTAT Due to the register changes described in section F.1.1.
Page 649: Code For A Full Context Save/Restore For C28X Vs C27X
Architecture Changes Figure F−3. Code for a Full Context Save/Restore for C28x vs C27x C28x Full Context Save/Restore −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− C27X Full Context Save/Rest IntX: ; 8 cycles −−−−−−−−−−−−−−−−−−−−−−−−−−−− PUSH AR1H:AR0H ; 32−bit IntX: ; 8 cycles PUSH XAR2 ; 32−bit push AR3:AR2 PUSH...
Page 650: Mapping Of Memory Blocks B0 And B1 On C27X
Architecture Changes Figure F−4. Mapping of Memory Blocks B0 and B1 on C27x C27x Program Space Data Space 00 0000 00 0400 00 07FF On a C28x device at reset, these blocks are mapped uniformly in both program and data space as shown in Figure F−5. This can cause issues when running C27x object code that relies on the C27x mapping.
Page 651: Building A C27X Object File From C27X Source
Architecture Changes F.1.4 C27x Object Compatibility At reset, the C28x operates in C27x object mode (OBJMODE == 0). In this mode, the C28x CPU is 100% object-code compatible and cycle-count com- patible with the C27x. In this case, you will compile your code just as you would for a C27x design as shown in Figure F−6.
Page 652: Building A C28X Object File From Mixed C27X/C28X Source
Moving to a C28x Object F.2 Moving to a C28x Object The C28x instruction set is a superset of the C27x instruction set. The syntax of a number of instructions however has changed slightly due to the modifica- tions in registers as previously described. (For a summary of syntax changes, see Section F.3.1 Instruction Syntax Changes).
Page 653 Moving to a C28x Object mode (OBJMODE == 0), the upper bits of XARn registers may contain nonzero values. You MUST zero out the upper bits of the XARn registers when switching from OBJMODE == 1 to OBJMODE == 0. It is recommended that you not switch modes frequently in your code.
Page 654: F.3 Migrating To C28X Object Code
Migrating to C28x Object Code F.3 Migrating to C28x Object Code This section describes additional changes to C27x necessary for migrating your C27x code to pure C28x code. F.3.1 Instruction Syntax Changes Syntax changes were necessary for clarity and because of changes in the aux- iliary registers stretched pointers.
Page 655: Instruction Syntax Change
Migrating to C28x Object Code Table F−3. Instruction Syntax Change C27x Syntax C28x Syntax ADDB ARn,#7bit ADDB XARn,#7bit ADDB XAR6/7,#7bit SUBB ARn,#7bit SUBB XARn,#7bit SUBB XAR6/7,#7bit AR0/../5,loc16 MOVZ AR0/../5,loc16 MOVB AR0/../5,#8bit MOVB XAR0/../5,#8bit XAR6/7,loc32 MOVL XAR6/7,loc32 MOVL XAR6/7,loc32 XAR6/7,#22bit MOVL XAR6/7,#22bit MOVL XAR6/7,#22bit...
Page 656: F.3.2 Repeatable Instructions
Migrating to C28x Object Code For conditional branches on the C28x, the UNC code must always be specified for unconditional tests. This will help to distinguish between unconditional C2xLP branches (which have the same mnemonic ”B”). F.3.2 Repeatable Instructions On the C28x, additional instructions have been made repeatable. The follow- ing two tables list those instructions that are repeatable on the C28x device.
Page 657: F.3.3 Changes To The Subcu Instruction
Migrating to C28x Object Code C27x Operations That Are Made Repeatable On C28x include the following: loc16,AX ACC,loc16 << 16 ADDU ACC,loc16 ACC,loc16 << 16 SUBU ACC,loc16 ADDL ACC,loc32 ACC,1..16 ACC,1..16 MOVH loc16,P loc16,P MOVA T,loc16 MOVS T,loc16 MPYA P,T,loc16 MPYS P,T,loc16 F.3.3...
Page 658 Migrating to C28x Object Code The C flag is affected by the unsigned 33-bit compare operation. The Z, N flags reflect the value in the ACC after the operation is complete. The operation of the C, N, Z flags should be identical to the C27x implementa- tion.
Page 659: F−8. Compiling C28X Source
Compiling C28x Source Code F.4 Compiling C28x Source Code Once you move your code to C28x native instructions, you will no longer use the −m27 switch to allow for C27x source as shown in Figure F−8. Figure F−8. Compiling C28x Source C28x Source CL2000 C28x Object...
Page 660 Appendix G Appendix A Glossary 16-bit operation: An operation that reads or writes 16 bits. 32-bit operation: An operation that reads or writes 32 bits. absolute branch: A branch to an address that is permanently assigned to a memory location. See also offset branch. ACC: See accumulator (ACC).
Page 661 Glossary AH.LSB: Least significant byte of AH. The name given to bits 23 through 16 of the accumulator. AH.MSB: Most significant byte of AH. The name given to bits 31 through 24 of the accumulator. AL: Low word of the accumulator. The name given to bits 15 through 0 of the accumulator.
Page 662 Glossary auxiliary register: One of eight registers used as a pointer to a memory location. The register is operated on by the auxiliary register arithmetic unit (ARAU) and is selected by the auxiliary register pointer (ARP). See also AR0−AR5, AR6/AR7, and XAR6/XAR7. auxiliary-register indirect addressing mode: The indirect addressing mode that allows you to use the name of an auxiliary register in an oper- and that uses that register as a pointer.
Page 663 Glossary C bit: See carry (C) bit. call: 1) The operation of saving a return address and then forcing program control to a new address. 2) An instruction that performs such an opera- tion. See also return. carry (C) bit: A bit in status register ST0 that reflects whether an addition has generated a carry or a subtraction has generated a borrow.
Page 664 Glossary D1 phase: See decode 1 (D1) phase. D2 phase: See decode 2 (D2) phase. data logging: Transferring one or more packets of data from CPU registers or memory to an external host processor. data log interrupt (DLOGINT): A maskable interrupt triggered by the on- chip emulation logic when a data logging transfer has been completed.
Page 665: Debug Interrupt Enable Register (Dbgier)
Glossary debug event: An action such as the decoding of a software breakpoint instruction, the occurrence of an analysis breakpoint/watchpoint, or a re- quest from a host processor that may result in special debug behavior, such as halting the device or pulsing one of the debug interface signals EMU0 or EMU1.
Page 666 Glossary direct addressing modes: The addressing modes that access data space as if it were 65 536 separate blocks of 64 words each. DP direct address- ing mode uses the data page pointer (DP) to select a data page from 0 to 65 535.
Page 667 Glossary enable bit: See interrupt enable bits. execute an instruction: Take an instruction from the decode 2 phase of the pipeline through the write phase of the pipeline. execute (E) phase: The seventh of eight pipeline phases an instruction passes through. In this phase, the CPU performs all multiplier, shifter, and arithmetic-logic-unit (ALU) operations.
Page 668 Glossary high word: The 16 MSBs of a 32-bit value. See also low word. host processor: The processor running the user interface for a debugger. IC: See instruction counter (IC). IDLESTAT (IDLE status) bit: A bit in status register ST1 that indicates when an IDLE instruction has the CPU in the idle state (IDLESTAT = 1).
Page 669 Glossary indirect addressing modes: Addressing modes that use pointers to ac- cess memory. The available pointers are auxiliary registers AR0−AR5, extended auxiliary registers XAR6 and XAR7, and the stack pointer (SP). instruction boundary: The point where the CPU has finished one instruc- tion and is considering what it will do next —...
Page 670 Glossary interrupt flag bit: A bit in the interrupt flag register (IFR). If the interrupt flag bit is 1, the corresponding interrupt has been requested by hardware and is awaiting approval by the CPU. interrupt flag register (IFR): The register that contains the interrupt flag bits for the maskable interrupts.
Page 671 Glossary JTAG: Joint Test Action Group. The Joint Test Action Group was formed in 1985 to develop economical test methodologies for systems designed around complex integrated circuits and assembled with surface-mount technologies. The group drafted a standard that was subsequently adopted by IEEE as IEEE Standard 1149.1-1990, “IEEE Standard Test Access Port and Boundary-Scan Architecture”.
Page 672 Glossary LSB: When used in a syntax of the MOVB instruction, LSB means least sig- nificant byte. Otherwise, LSB means least significant bit. See least signif- icant bit (LSB) and least significant byte (LSByte). LSByte: See least significant byte (LSByte). maskable interrupt: An interrupt that can be disabled by software so that the CPU does not service it until it is enabled by software.
Page 673 Glossary N (negative flag) bit: A bit in status register ST0 that indicates whether the result of a calculation is a negative number (N = 1). N is set to match the MSB of the result. nested interrupt: An interrupt that occurs within an interrupt service routine. NMI: A hardware interrupt that is nonmaskable, like reset (RS), but does not reset the CPU.
Page 674 Glossary overflow counter (OVC): A 6-bit counter in status register ST0 that can be used to track overflows in the accumulator (ACC). The OVC is enabled only when the overflow mode (OVM) bit in ST0 is 0. When OVM = 0, the OVC is incremented by 1 for every overflow in the positive direction (too large a positive number) and decremented by 1 for every overflow in the negative direction (too large a negative number).
Page 675 Glossary peripheral-interface logic: Hardware that is responsible for handling com- munications between a processor and a peripheral. PH: The high word (16 MSBs) of the P register. phases: See pipeline phases. pipeline: The hardware in the CPU that takes each instruction through eight independent phases for fetching, decoding, and executing.
Page 676 Glossary product shift mode (PM) bits: A 3-bit field in status register ST0 that en- ables you to select one of eight product shift modes. The product shift mode determines whether or how the P register value is shifted before being used by an instruction.
Page 677 Glossary ready signals: When the core requests a read from or write to a memory device or peripheral device, that device can take more time to finish the data transfer than the core allots by default. Each device must use one of the core’s ready signals to insert wait states into the data transfer when it needs more time.
Page 678 Glossary RISC: See reduced instruction set computer (RISC). rotate operation: An operation performed by the ROL (rotate accumulator left) or ROR (rotate accumulator right) instruction. The operation, which involves a shift by 1 bit, can be seen as the rotation of a 33-bit value that is the concatenation of the carry bit (C) and the accumulator (ACC).
Page 679 Glossary 16-bit operation: An operation that reads or writes 16 bits. software interrupt: An interrupt initiated by an instruction. See also hard- ware interrupt. SP: See stack pointer (SP). SPA bit: See stack pointer alignment (SPA) bit. ST0: See status registers ST0 and ST1. ST1: See status registers ST0 and ST1.
Page 680 Glossary T register: The primary function of this register, also called the multiplicand register, is to hold one of the values to be multiplied during a multiplica- tion. The following shift instructions use the four LSBs to hold the shift count: ASR (arithmetic shift right), LSL (logical shift left), LSR (logical shift right), and SFR (shift accumulator right).
Page 681 Glossary V bit (overflow flag): A bit in status register ST0 that indicates when the re- sult of an operation causes an overflow in the location holding the result (V = 1). If no overflow occurs, V is not modified. vector: See interrupt vector.
Page 682 Index Index address buses 1-9 address counters FC, IC, and PC 4-5 address maps 1-8 ABORTI 6-18 address reach C-5 ABORTI instruction 7-15 address register arithmetic unit (ARAU) 1-5, 2-2 ABS ACC 6-19 addressing modes 5-1, 5-2 ABSTC ACC 6-20 byte 5-31 access to CPU registers during emulation 7-16 direct 2-10...
Page 683 Index AND ACC, loc16 6-43, 6-44 debug enable mask (DBGM) 2-37 debug interrupt enable register (DBGIER) 3-10 AND AX, loc16, #16bit 6-45 emulation access enable (EALLOW) 2-35 AND IER,#16bit 6-46 IDLE status (IDLESTAT) 2-35 AND IFR,#16bit 6-47 interrupt enable register (IER) 3-9 AND loc16, AX 6-48 interrupt flag register (IFR) 3-7 AND AX, loc16 6-49...
Page 684 Index C28x and C2xLP Flags, table E-2 code clear IFR D-8 C28x features C-2 conversion from C2xLP D-8 C28x Product Mode Shifter, table C-8 IER/IFR D-7 C28x Status Register ST0 C-7 interrupt D-8 C28x Status Register ST1 C-7 migration reference tables D-10 C2xLP D-1 code examples D-7 C2xLP and C28x architectural differences C-1...
Page 685 Index data-/program-write data bus (DWDB) 1-9 direct addressing mode C-5 Direct Addressing Mode Mapping, figure C-6 data-read address bus (DRAB) 1-9 direct addressing mode on the C2xLP C-5 data-read data bus (DRDB) 1-9 direct memory access mechanism data-write address bus (DWAB) 1-9 for emulation 7-16 DBGIER A-2 disable write access to protected registers 6-91...
Page 686 Index debug 7-6 examples code D-7 I/O space C-14 data logging with end address 7-29 IACK #16bit 6-97 data logging with word counter 7-28 IC (instruction counter) 4-5 execution control modes IDLE 6-98 real-time mode 7-9 IDLE status bit (IDLESTAT) 2-35 stop mode 7-7 IDLESTAT C-9 IDLESTAT bit 2-35...
Page 687 Index ASP (align stack pointer) 6-52 POP ACC (pop top of stack to accumula- tor) 6-267 ASRAX (arithmetic shift right) 6-53 B (branch) 6-58 PREAD (read from program memory) 4-16 PREAD loc16,*XAR7 (read from C27MAP (set the M0M1MAP bit) 6-62 program memory) 6-282 C27OBJ (clear the OBJMODE bit) 6-63 PUSH ACC (push accumulator onto...
Page 688 Index control registers (IFR, IER, DBGIER) 2-14 LCR *XARn 6-124 data log interrupt (DLOGINT) 3-6, 7-27 load auxiliary register 6-160 effect on instructions in pipeline 4-4 load AX 6-161 general purpose 3-6 load data page pointer 6-162 handling information by emulation load the interrupt enable register 6-163 mode and state 7-13 load the overflow counter 6-176...
Page 689 Index Mapping of memory blocks B0 and B1 on C27 F-7 MOV loc16, AX, COND 6-170 maskable interrupts 3-6 MOV loc16,IER 6-172 definition 3-2 MOV loc16,OVC 6-173 flow chart of operation 3-12 MOV loc16,P 6-174 MAX AX, loc16 6-149 MOV OVC, loc16 6-176 MAXCUL P,loc32 6-150 MOV PH, loc16 6-177 MAXL ACC,loc32 6-152...
Page 690 Index MOVU OVC,loc16 6-222 MOVW DP, #16bit 6-223 MOVX TL,loc16 6-224 OBJMODE C-9, F-4, F-9 MOVZ AR005, loc16 6-225 OBJMODE bit 1-2 MOVZ DP, #10bit 6-226 operating modes, selecting by using TRST, EMU0, and EMU1 7-5 MPY ACC, loc16,#16bit 6-227 operations MPY ACC,T,loc16 6-228 multiply 2-41...
Page 691 Index wait states 4-10 program−space read and write 1-10 program-address counters 4-5 pipeline phases 4-2 PM bits 2-19 program-read data bus (PRDB) 1-9 PUSH ACC 6-284 POP ACC 6-267 push accumulator onto stack 6-284 POP AR1:AR0 6-268 PUSH AR1:AR0 6-285 POP AR1H:AR0H 6-269 PUSH AR1H:AR0H 6-286 POP AR3:AR2 6-268...
Page 692 Index real-time mode 7-7, 7-9 Reset Conditions of Internal figure of execution states 7-10 Registers, table C-10 real-time mode versus stop mode, figure 7-12 reset input signal (RS) 3-23 reset of CPU 3-23 real-time operating system interrupt (RTOSINT) 3-6, 7-14 Reset Values of the Status and Control Registers, table A-2 Register Addressing Mode 5-2...
Page 693 Index SETC M0M1MAP 6-322 Stack Addressing Mode 5-2, 5-9 Stack Pointer C-4 SETC mode 6-320 stack pointer (SP) 2-11 SETC OBJMODE 6-323 Stack pointer alignment bit C-9 SETC XF 6-324 stack pointer alignment bit (SPA) 2-36 SFR ACC,#1..16 6-325 Stack space C-14 SFR ACC,T 6-326 start address register (data logging) 7-25 shift operations 2-44...
Page 694 Index SUBB SP,#7bit 6-341 TMS320C24x D-1 SUBBL ACC, loc32 6-343 TMS320C24xx D-1 TRAP #VectorNumber 6-363 SUBCU ACC, loc16 6-345 TRAP instruction 3-18, D-10 SUBCU instruction F-14 TRST signal 7-4, 7-5 SUBCUL ACC,loc32 6-347 TSET loc16,#16bit 6-365 SUBL ACC, loc32 6-350 types of signals 1-6 SUBL ACC,P <...
Page 695 Index XCALL *AL 6-374 XORB AX, #8bit 6-387 XPREAD loc16,*(pma) 6-388 XCALL pma,*,ARPn 6-375 XPREAD loc16,*AL 6-389 XCALL pma,COND 6-376 XPWRITE *AL,loc16 6-390 XF F-4 XRET 6-391 XF pin status bit C-9 XRETC COND 6-392 XMAC P,loc16,*(pma) 6-378 XMACD P,loc16,*(pma) 6-380 XOR AX, loc16 6-384 XOR ACC,#16bit <...