Control Output; Overview - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual

CONTROL OUTPUT

OVERVIEW

The AD9361 provides real-time status information on up to
eight dedicated pins. Information such as when calibrations are
running and the state of the overload detectors in the receive
signal path are just a few of the many options available. This
section describes the signals and their behavior in detail while
also showing how to program the registers so that the desired
signals are available on the appropriate balls. This section also
provides some information about how a BBP could use the
signals in an application. The control outputs are configured
using the ad9361_ctrl_outs_setup function.
As shown in Table 44, the control output signals are mapped as
a table. The Control Output Pointer selects the row (address)
that will be sent to the output pins. And the bits in Control
Output Enable individually select which output pins will be
active. The AD9361 will hold low any pins not enabled.
Some internal signals are available on more than one
combination of Control Output Pointer and Control Output
Enable. For example, to enable a control output that indicates
that the Rx1 gain has changed, the Control Output Pointer
Table 43. Control Output Bit Descriptions
Register
Address Name
0x035 Control Output Pointer
0x036 Control Output Enable
Table 44. Control Output Table
Register
0x035 D7 D6
00 Cal Done Tx CP Cal Done
01 Tx RF PLL Lock Rx RF PLL Lock
02 BB DC Cal Busy RF DC Cal Busy
03 CH1 ADC Low CH1 Lg LMT
Power Ovrg
04 CH 2 Rx Gain[6] CH2 Rx Gain[5]
05 CH2 Gain CH1 Gain
Change Change
06 CH1 Low Power CH1 Lg LMT
Ovrg
07 CH1 Low Power CH1 Lg LMT
Ovrg
08 CH1 Stronger CH1 Gain Lock
Signal
09 RxOn CH1 RSSI
Preamble
Ready
0A CH1 Tx Int3 CH1 Tx HB3
Overflow Overflow
0B Cal Seq State[3] Cal Seq State
[2]
D7 D6 D5
En ctrl7 En ctrl6 En ctrl5
Control Output Bit Position
D5 D4
Rx CP Cal Rx BB Filter
Done Tuning Done
BBPLL Lock 0
CH1 Rx Quad CH1 Tx Quad
Cal Busy Cal Busy
CH1 Lg ADC CH1 Sm ADC
Ovrg Ovrg
CH2 Rx CH2 Rx Gain[3]
Gain[4]
CH2 Low CH2 Lg LMT
Power Ovrg
CH1 Lg ADC CH1 Rx Gain[6]
Ovrg
CH1 Lg ADC CH1 Sm ADC
Ovrg Ovrg
CH1 Energy CH1 Gain
Lost Change
CH1 RSSI TxOn
Symbol Ready
CH1 Tx HB2 CH1 Tx QEC
Overflow Overflow
Cal Seq State Cal Seq State
[1] [0]
Rev. A
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register could be set to 0x08 and the Control Output Enable
register would then be set to 0x10. The same signal is also
available by setting Control Output Pointer to 0x05 and Control
Output Enable to 0x40 or alternatively with Control Output
Pointer set to 0x1E and Control Output Enable set to 0x04. Any
one of these options is valid. The BBP can only monitor the
signals in one row at a time because Register Control Output
Pointer can only have a single value loaded at any given time.
Thus, selecting one over the other depends on which other
signals the BBP needs to monitor simultaneously. From the
example, if the BBP also needs to know when the AuxADC
word is valid, only the option of setting Control Output Pointer
to 0x1E will allow this combination of the two signals. In this
case, Control Output Enable would need to be set to 0x05. The
BBP can also set more of the bits in Control Output Enable even
if it does not monitor those signals.
Some of the signals are helpful in a production system while
some others are useful for debug. In either case, Analog Devices
recommends connecting the
inputs on the BBP so that the BBP can monitor real-time
conditions in the AD9361.
D4 D3 D2
Control Output Pointer[7:0]
En ctrl4 En ctrl3 En ctrl2
D3 D2
Tx BB Filter Gain Step Cal
Tuning Done Busy
0 0
CH2 Rx Quad CH2 Tx Quad
Cal Busy Cal Busy
CH2 Low Power CH2 Lg LMT
Ovrg
CH2 Rx Gain[2] CH2 Lg LMT
Ovrg
CH2 Lg ADC CH2 Gain Lock
Ovrg
CH1 Rx Gain[5] CH1 Rx
Gain[4]
CH1 AGC SM[2] CH1 AGC
SM[1]
CH2 Stronger CH2 Gain Lock
Signal
CH2 RSSI CH2 RSSI
Preamble Symbol Ready
Ready
CH1 Tx HB1 CH1 Tx FIR
Overflow Overflow
ENSM[3] ENSM[2]
UG-570
AD9361 control outputs to BBP
D1 D0 Default
0x00
En ctrl1 En ctrl0 FF
D1 D0
Rx Synth VCO Tx Synth VCO
Cal Busy Cal Busy
0 0
Gain Step Cal Tx Mon Cal
Busy Busy
CH2 Lg ADC CH2 Sm ADC
Ovrg Ovrg
CH2 Lg ADC CH2 Gain
Ovrg Lock
CH2 Energy CH2 Stronger
Lost Signal
CH1 Rx CH1 Rx
Gain[3] Gain[2]
CH1 AGC CH1 Gain
SM[0] Lock
CH2 Energy CH2 Gain
Lost Change
CH1 Rx FIR
Overflow
ENSM[1] ENSM[0]
R/W
R/W
R/W