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Bit 5—BUZZ Output Enable (BUZZE): This bit enables/disables BUZZ output via the PF1 pin.
The WDT1 input clock, selected with PSS and CKS2 to CKS0, is output as the BUZZ signal. See
Section 15.2.4, Pin Function Control Register (PFCR) for details of BUZZ output.
Bit 5
BUZZE
Description
0
Functions as PF1 input pin.
1
Functions as BUZZ output pin.
Bit 4—LCAS Output Pin Select Bit (LCASS): Selects output pin for LCAS signal.
Bit 4
LCASS
Description
0
Outputs LCAS signal from PF2.
1
Outputs LCAS signal from PF6.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.
(Initial value)
(Initial value)
147
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